Index: uspace/drv/infrastructure/rootamdm37x/rootamdm37x.c
===================================================================
--- uspace/drv/infrastructure/rootamdm37x/rootamdm37x.c	(revision a5a73c0e7bf5dab45dcb463e8b588364f1325e6b)
+++ uspace/drv/infrastructure/rootamdm37x/rootamdm37x.c	(revision 71d09d6e1da31c7024293452978a24f0987dfd58)
@@ -64,4 +64,12 @@
 } amdm37x_t;
 
+#ifdef DEBUG_CM
+static void log(volatile void *place, uint32_t val, volatile void* base, size_t size, void *data, bool write)
+{
+	printf("PIO %s: %p(%p) %#"PRIx32"\n", write ? "WRITE" : "READ",
+	    (place - base) + data, place, val);
+}
+#endif
+
 static int amdm37x_hw_access_init(amdm37x_t *device)
 {
@@ -94,4 +102,11 @@
 		return ret;
 
+#ifdef DEBUG_CM
+	pio_trace_enable(device->tll, AMDM37x_USBTLL_SIZE, log, (void*)AMDM37x_USBTLL_BASE_ADDRESS);
+	pio_trace_enable(device->cm.clocks, CLOCK_CONTROL_CM_SIZE, log, (void*)CLOCK_CONTROL_CM_BASE_ADDRESS);
+	pio_trace_enable(device->cm.core, CORE_CM_SIZE, log, (void*)CORE_CM_BASE_ADDRESS);
+	pio_trace_enable(device->cm.usbhost, USBHOST_CM_SIZE, log, (void*)USBHOST_CM_BASE_ADDRESS);
+	pio_trace_enable(device->uhh, AMDM37x_UHH_SIZE, log, (void*)AMDM37x_UHH_BASE_ADDRESS);
+#endif
 	return EOK;
 }
@@ -116,6 +131,7 @@
 
 #ifdef DEBUG_CM
-	printf("DPLL5 could be on: %x %x.\n",
-	    device->cm.clocks->idlest_ckgen, device->cm.clocks->idlest2_ckgen);
+	printf("DPLL5 could be on: %"PRIx32" %"PRIx32".\n",
+	    pio_read_32((ioport32_t*)&device->cm.clocks->idlest_ckgen),
+	    pio_read_32((ioport32_t*)&device->cm.clocks->idlest2_ckgen));
 #endif
 
@@ -134,6 +150,7 @@
 		    USBHOST_CM_ICLKEN_EN_USBHOST, 5);
 #ifdef DEBUG_CM
-	printf("DPLL5 (and everything else) should be on: %x %x.\n",
-	    device->cm.clocks->idlest_ckgen, device->cm.clocks->idlest2_ckgen);
+	printf("DPLL5 (and everything else) should be on: %"PRIx32" %"PRIx32".\n",
+	    pio_read_32((ioport32_t*)&device->cm.clocks->idlest_ckgen),
+	    pio_read_32((ioport32_t*)&device->cm.clocks->idlest2_ckgen));
 #endif
 	} else {