Index: kernel/arch/arm32/Makefile.inc =================================================================== --- kernel/arch/arm32/Makefile.inc (revision c4c2406caea2227486ba46e0c0ca00fff2b1fe13) +++ kernel/arch/arm32/Makefile.inc (revision 71d09d6e1da31c7024293452978a24f0987dfd58) @@ -33,5 +33,5 @@ ATSIGN = % -GCC_CFLAGS += -march=armv4 -fno-omit-frame-pointer -mapcs-frame +GCC_CFLAGS += -fno-omit-frame-pointer -mapcs-frame -march=$(subst _,-,$(PROCESSOR)) -mno-unaligned-access BITS = 32 @@ -74,4 +74,8 @@ endif +ifeq ($(MACHINE),beagleboardxm) + ARCH_SOURCES += arch/$(KARCH)/src/mach/beagleboardxm/beagleboardxm.c +endif + ifeq ($(CONFIG_PL050),y) ARCH_SOURCES += genarch/src/drivers/pl050/pl050.c Index: kernel/arch/arm32/_link.ld.in =================================================================== --- kernel/arch/arm32/_link.ld.in (revision c4c2406caea2227486ba46e0c0ca00fff2b1fe13) +++ kernel/arch/arm32/_link.ld.in (revision 71d09d6e1da31c7024293452978a24f0987dfd58) @@ -9,4 +9,6 @@ #ifdef MACHINE_gta02 #define KERNEL_LOAD_ADDRESS 0xb0a08000 +#elif defined MACHINE_beagleboardxm +#define KERNEL_LOAD_ADDRESS 0x80a00000 #else #define KERNEL_LOAD_ADDRESS 0x80a00000 Index: kernel/arch/arm32/include/asm.h =================================================================== --- kernel/arch/arm32/include/asm.h (revision c4c2406caea2227486ba46e0c0ca00fff2b1fe13) +++ kernel/arch/arm32/include/asm.h (revision 71d09d6e1da31c7024293452978a24f0987dfd58) @@ -43,7 +43,17 @@ #include -/** No such instruction on ARM to sleep CPU. */ +/** No such instruction on old ARM to sleep CPU. + * + * ARMv7 introduced wait for event and wait for interrupt (wfe/wfi). + * ARM920T has custom coprocessor action to do the same. See ARM920T Technical + * Reference Manual ch 4.9 p. 4-23 (103 in the PDF) + */ NO_TRACE static inline void cpu_sleep(void) { +#ifdef PROCESSOR_armv7_a + asm volatile ( "wfe" :: ); +#elif defined(MACHINE_gta02) + asm volatile ( "mcr p15,0,R0,c7,c0,4" :: ); +#endif } Index: kernel/arch/arm32/include/barrier.h =================================================================== --- kernel/arch/arm32/include/barrier.h (revision c4c2406caea2227486ba46e0c0ca00fff2b1fe13) +++ kernel/arch/arm32/include/barrier.h (revision 71d09d6e1da31c7024293452978a24f0987dfd58) @@ -47,6 +47,24 @@ #define write_barrier() asm volatile ("" ::: "memory") -#define smc_coherence(a) -#define smc_coherence_block(a, l) +/* + * There are multiple ways ICache can be implemented on ARM machines. Namely + * PIPT, VIPT, and ASID and VMID tagged VIVT (see ARM Architecture Reference + * Manual B3.11.2 (p. 1383). However, CortexA8 Manual states: "For maximum + * compatibility across processors, ARM recommends that operating systems target + * the ARMv7 base architecture that uses ASID-tagged VIVT instruction caches, + * and do not assume the presence of the IVIPT extension. Software that relies + * on the IVIPT extension might fail in an unpredictable way on an ARMv7 + * implementation that does not include the IVIPT extension." (7.2.6 p. 245). + * Only PIPT invalidates cache for all VA aliases if one block is invalidated. + * + * @note: Supporting ASID and VMID tagged VIVT may need to add ICache + * maintenance to other places than just smc. + */ + +/* Available on both all supported arms, + * invalidates entire ICache so the written value does not matter. */ +#define smc_coherence(a) asm volatile ( "mcr p15, 0, r0, c7, c5, 0") +#define smc_coherence_block(a, l) smc_coherence(a) + #endif Index: kernel/arch/arm32/include/cpu.h =================================================================== --- kernel/arch/arm32/include/cpu.h (revision c4c2406caea2227486ba46e0c0ca00fff2b1fe13) +++ kernel/arch/arm32/include/cpu.h (revision 71d09d6e1da31c7024293452978a24f0987dfd58) @@ -41,5 +41,5 @@ -/** Struct representing ARM CPU identifiaction. */ +/** Struct representing ARM CPU identification. */ typedef struct { /** Implementator (vendor) number. */ Index: kernel/arch/arm32/include/mach/beagleboardxm/beagleboardxm.h =================================================================== --- kernel/arch/arm32/include/mach/beagleboardxm/beagleboardxm.h (revision 71d09d6e1da31c7024293452978a24f0987dfd58) +++ kernel/arch/arm32/include/mach/beagleboardxm/beagleboardxm.h (revision 71d09d6e1da31c7024293452978a24f0987dfd58) @@ -0,0 +1,48 @@ +/* + * Copyright (c) 2012 Jan Vesely + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * - Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * - Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * - The name of the author may not be used to endorse or promote products + * derived from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR + * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES + * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. + * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT + * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF + * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ +/** @addtogroup arm32beagleboardxm beagleboardxm + * @brief BeagleBoard-xM platform. + * @ingroup arm32 + * @{ + */ +/** @file + * @brief BeagleBoard platform driver. + */ + +#ifndef KERN_arm32_beagleboardxm_H_ +#define KERN_arm32_beagleboardxm_H_ + +#include + +extern struct arm_machine_ops bbxm_machine_ops; + +#endif + +/** @} + */ + Index: kernel/arch/arm32/include/machine_func.h =================================================================== --- kernel/arch/arm32/include/machine_func.h (revision c4c2406caea2227486ba46e0c0ca00fff2b1fe13) +++ kernel/arch/arm32/include/machine_func.h (revision 71d09d6e1da31c7024293452978a24f0987dfd58) @@ -108,4 +108,6 @@ extern size_t machine_get_irq_count(void); +extern const char * machine_get_platform_name(void); + #endif Index: kernel/arch/arm32/include/mm/frame.h =================================================================== --- kernel/arch/arm32/include/mm/frame.h (revision c4c2406caea2227486ba46e0c0ca00fff2b1fe13) +++ kernel/arch/arm32/include/mm/frame.h (revision 71d09d6e1da31c7024293452978a24f0987dfd58) @@ -48,4 +48,6 @@ #ifdef MACHINE_gta02 #define BOOT_PAGE_TABLE_ADDRESS 0x30010000 +#elif defined MACHINE_beagleboardxm +#define BOOT_PAGE_TABLE_ADDRESS 0x80008000 #else #define BOOT_PAGE_TABLE_ADDRESS 0x00008000 @@ -57,4 +59,6 @@ #ifdef MACHINE_gta02 #define PHYSMEM_START_ADDR 0x30008000 +#elif defined MACHINE_beagleboardxm +#define PHYSMEM_START_ADDR 0x80000000 #else #define PHYSMEM_START_ADDR 0x00000000 Index: kernel/arch/arm32/include/mm/page.h =================================================================== --- kernel/arch/arm32/include/mm/page.h (revision c4c2406caea2227486ba46e0c0ca00fff2b1fe13) +++ kernel/arch/arm32/include/mm/page.h (revision 71d09d6e1da31c7024293452978a24f0987dfd58) @@ -46,4 +46,13 @@ #define PAGE_SIZE FRAME_SIZE +#ifdef MACHINE_beagleboardxm +#ifndef __ASM__ +# define KA2PA(x) ((uintptr_t) (x)) +# define PA2KA(x) ((uintptr_t) (x)) +#else +# define KA2PA(x) (x) +# define PA2KA(x) (x) +#endif +#else #ifndef __ASM__ # define KA2PA(x) (((uintptr_t) (x)) - 0x80000000) @@ -53,57 +62,58 @@ # define PA2KA(x) ((x) + 0x80000000) #endif +#endif /* Number of entries in each level. */ -#define PTL0_ENTRIES_ARCH (1 << 12) /* 4096 */ -#define PTL1_ENTRIES_ARCH 0 -#define PTL2_ENTRIES_ARCH 0 +#define PTL0_ENTRIES_ARCH (1 << 12) /* 4096 */ +#define PTL1_ENTRIES_ARCH 0 +#define PTL2_ENTRIES_ARCH 0 /* coarse page tables used (256 * 4 = 1KB per page) */ -#define PTL3_ENTRIES_ARCH (1 << 8) /* 256 */ +#define PTL3_ENTRIES_ARCH (1 << 8) /* 256 */ /* Page table sizes for each level. */ -#define PTL0_SIZE_ARCH FOUR_FRAMES -#define PTL1_SIZE_ARCH 0 -#define PTL2_SIZE_ARCH 0 -#define PTL3_SIZE_ARCH ONE_FRAME +#define PTL0_SIZE_ARCH FOUR_FRAMES +#define PTL1_SIZE_ARCH 0 +#define PTL2_SIZE_ARCH 0 +#define PTL3_SIZE_ARCH ONE_FRAME /* Macros calculating indices into page tables for each level. */ -#define PTL0_INDEX_ARCH(vaddr) (((vaddr) >> 20) & 0xfff) -#define PTL1_INDEX_ARCH(vaddr) 0 -#define PTL2_INDEX_ARCH(vaddr) 0 -#define PTL3_INDEX_ARCH(vaddr) (((vaddr) >> 12) & 0x0ff) +#define PTL0_INDEX_ARCH(vaddr) (((vaddr) >> 20) & 0xfff) +#define PTL1_INDEX_ARCH(vaddr) 0 +#define PTL2_INDEX_ARCH(vaddr) 0 +#define PTL3_INDEX_ARCH(vaddr) (((vaddr) >> 12) & 0x0ff) /* Get PTE address accessors for each level. */ #define GET_PTL1_ADDRESS_ARCH(ptl0, i) \ - ((pte_t *) ((((pte_t *)(ptl0))[(i)].l0).coarse_table_addr << 10)) + ((pte_t *) ((((pte_t *)(ptl0))[(i)].l0).coarse_table_addr << 10)) #define GET_PTL2_ADDRESS_ARCH(ptl1, i) \ - (ptl1) + (ptl1) #define GET_PTL3_ADDRESS_ARCH(ptl2, i) \ - (ptl2) + (ptl2) #define GET_FRAME_ADDRESS_ARCH(ptl3, i) \ - ((uintptr_t) ((((pte_t *)(ptl3))[(i)].l1).frame_base_addr << 12)) + ((uintptr_t) ((((pte_t *)(ptl3))[(i)].l1).frame_base_addr << 12)) /* Set PTE address accessors for each level. */ #define SET_PTL0_ADDRESS_ARCH(ptl0) \ - (set_ptl0_addr((pte_t *) (ptl0))) + (set_ptl0_addr((pte_t *) (ptl0))) #define SET_PTL1_ADDRESS_ARCH(ptl0, i, a) \ - (((pte_t *) (ptl0))[(i)].l0.coarse_table_addr = (a) >> 10) + (((pte_t *) (ptl0))[(i)].l0.coarse_table_addr = (a) >> 10) #define SET_PTL2_ADDRESS_ARCH(ptl1, i, a) #define SET_PTL3_ADDRESS_ARCH(ptl2, i, a) #define SET_FRAME_ADDRESS_ARCH(ptl3, i, a) \ - (((pte_t *) (ptl3))[(i)].l1.frame_base_addr = (a) >> 12) + (((pte_t *) (ptl3))[(i)].l1.frame_base_addr = (a) >> 12) /* Get PTE flags accessors for each level. */ #define GET_PTL1_FLAGS_ARCH(ptl0, i) \ - get_pt_level0_flags((pte_t *) (ptl0), (size_t) (i)) + get_pt_level0_flags((pte_t *) (ptl0), (size_t) (i)) #define GET_PTL2_FLAGS_ARCH(ptl1, i) \ - PAGE_PRESENT + PAGE_PRESENT #define GET_PTL3_FLAGS_ARCH(ptl2, i) \ - PAGE_PRESENT + PAGE_PRESENT #define GET_FRAME_FLAGS_ARCH(ptl3, i) \ - get_pt_level1_flags((pte_t *) (ptl3), (size_t) (i)) + get_pt_level1_flags((pte_t *) (ptl3), (size_t) (i)) /* Set PTE flags accessors for each level. */ #define SET_PTL1_FLAGS_ARCH(ptl0, i, x) \ - set_pt_level0_flags((pte_t *) (ptl0), (size_t) (i), (x)) + set_pt_level0_flags((pte_t *) (ptl0), (size_t) (i), (x)) #define SET_PTL2_FLAGS_ARCH(ptl1, i, x) #define SET_PTL3_FLAGS_ARCH(ptl2, i, x) @@ -119,221 +129,11 @@ set_pt_level1_present((pte_t *) (ptl3), (size_t) (i)) -/* Macros for querying the last-level PTE entries. */ -#define PTE_VALID_ARCH(pte) \ - (*((uint32_t *) (pte)) != 0) -#define PTE_PRESENT_ARCH(pte) \ - (((pte_t *) (pte))->l0.descriptor_type != 0) -#define PTE_GET_FRAME_ARCH(pte) \ - (((pte_t *) (pte))->l1.frame_base_addr << FRAME_WIDTH) -#define PTE_WRITABLE_ARCH(pte) \ - (((pte_t *) (pte))->l1.access_permission_0 == PTE_AP_USER_RW_KERNEL_RW) -#define PTE_EXECUTABLE_ARCH(pte) \ - 1 - -#ifndef __ASM__ - -/** Level 0 page table entry. */ -typedef struct { - /* 0b01 for coarse tables, see below for details */ - unsigned descriptor_type : 2; - unsigned impl_specific : 3; - unsigned domain : 4; - unsigned should_be_zero : 1; - - /* Pointer to the coarse 2nd level page table (holding entries for small - * (4KB) or large (64KB) pages. ARM also supports fine 2nd level page - * tables that may hold even tiny pages (1KB) but they are bigger (4KB - * per table in comparison with 1KB per the coarse table) - */ - unsigned coarse_table_addr : 22; -} ATTRIBUTE_PACKED pte_level0_t; - -/** Level 1 page table entry (small (4KB) pages used). */ -typedef struct { - - /* 0b10 for small pages */ - unsigned descriptor_type : 2; - unsigned bufferable : 1; - unsigned cacheable : 1; - - /* access permissions for each of 4 subparts of a page - * (for each 1KB when small pages used */ - unsigned access_permission_0 : 2; - unsigned access_permission_1 : 2; - unsigned access_permission_2 : 2; - unsigned access_permission_3 : 2; - unsigned frame_base_addr : 20; -} ATTRIBUTE_PACKED pte_level1_t; - -typedef union { - pte_level0_t l0; - pte_level1_t l1; -} pte_t; - -/* Level 1 page tables access permissions */ - -/** User mode: no access, privileged mode: no access. */ -#define PTE_AP_USER_NO_KERNEL_NO 0 - -/** User mode: no access, privileged mode: read/write. */ -#define PTE_AP_USER_NO_KERNEL_RW 1 - -/** User mode: read only, privileged mode: read/write. */ -#define PTE_AP_USER_RO_KERNEL_RW 2 - -/** User mode: read/write, privileged mode: read/write. */ -#define PTE_AP_USER_RW_KERNEL_RW 3 - - -/* pte_level0_t and pte_level1_t descriptor_type flags */ - -/** pte_level0_t and pte_level1_t "not present" flag (used in descriptor_type). */ -#define PTE_DESCRIPTOR_NOT_PRESENT 0 - -/** pte_level0_t coarse page table flag (used in descriptor_type). */ -#define PTE_DESCRIPTOR_COARSE_TABLE 1 - -/** pte_level1_t small page table flag (used in descriptor type). */ -#define PTE_DESCRIPTOR_SMALL_PAGE 2 - - -/** Sets the address of level 0 page table. - * - * @param pt Pointer to the page table to set. - * - */ -NO_TRACE static inline void set_ptl0_addr(pte_t *pt) -{ - asm volatile ( - "mcr p15, 0, %[pt], c2, c0, 0\n" - :: [pt] "r" (pt) - ); -} - - -/** Returns level 0 page table entry flags. - * - * @param pt Level 0 page table. - * @param i Index of the entry to return. - * - */ -NO_TRACE static inline int get_pt_level0_flags(pte_t *pt, size_t i) -{ - pte_level0_t *p = &pt[i].l0; - int np = (p->descriptor_type == PTE_DESCRIPTOR_NOT_PRESENT); - - return (np << PAGE_PRESENT_SHIFT) | (1 << PAGE_USER_SHIFT) | - (1 << PAGE_READ_SHIFT) | (1 << PAGE_WRITE_SHIFT) | - (1 << PAGE_EXEC_SHIFT) | (1 << PAGE_CACHEABLE_SHIFT); -} - -/** Returns level 1 page table entry flags. - * - * @param pt Level 1 page table. - * @param i Index of the entry to return. - * - */ -NO_TRACE static inline int get_pt_level1_flags(pte_t *pt, size_t i) -{ - pte_level1_t *p = &pt[i].l1; - - int dt = p->descriptor_type; - int ap = p->access_permission_0; - - return ((dt == PTE_DESCRIPTOR_NOT_PRESENT) << PAGE_PRESENT_SHIFT) | - ((ap == PTE_AP_USER_RO_KERNEL_RW) << PAGE_READ_SHIFT) | - ((ap == PTE_AP_USER_RW_KERNEL_RW) << PAGE_READ_SHIFT) | - ((ap == PTE_AP_USER_RW_KERNEL_RW) << PAGE_WRITE_SHIFT) | - ((ap != PTE_AP_USER_NO_KERNEL_RW) << PAGE_USER_SHIFT) | - ((ap == PTE_AP_USER_NO_KERNEL_RW) << PAGE_READ_SHIFT) | - ((ap == PTE_AP_USER_NO_KERNEL_RW) << PAGE_WRITE_SHIFT) | - (1 << PAGE_EXEC_SHIFT) | - (p->bufferable << PAGE_CACHEABLE); -} - -/** Sets flags of level 0 page table entry. - * - * @param pt level 0 page table - * @param i index of the entry to be changed - * @param flags new flags - * - */ -NO_TRACE static inline void set_pt_level0_flags(pte_t *pt, size_t i, int flags) -{ - pte_level0_t *p = &pt[i].l0; - - if (flags & PAGE_NOT_PRESENT) { - p->descriptor_type = PTE_DESCRIPTOR_NOT_PRESENT; - /* - * Ensures that the entry will be recognized as valid when - * PTE_VALID_ARCH applied. - */ - p->should_be_zero = 1; - } else { - p->descriptor_type = PTE_DESCRIPTOR_COARSE_TABLE; - p->should_be_zero = 0; - } -} - -NO_TRACE static inline void set_pt_level0_present(pte_t *pt, size_t i) -{ - pte_level0_t *p = &pt[i].l0; - - p->should_be_zero = 0; - write_barrier(); - p->descriptor_type = PTE_DESCRIPTOR_COARSE_TABLE; -} - -/** Sets flags of level 1 page table entry. - * - * We use same access rights for the whole page. When page - * is not preset we store 1 in acess_rigts_3 so that at least - * one bit is 1 (to mark correct page entry, see #PAGE_VALID_ARCH). - * - * @param pt Level 1 page table. - * @param i Index of the entry to be changed. - * @param flags New flags. - * - */ -NO_TRACE static inline void set_pt_level1_flags(pte_t *pt, size_t i, int flags) -{ - pte_level1_t *p = &pt[i].l1; - - if (flags & PAGE_NOT_PRESENT) - p->descriptor_type = PTE_DESCRIPTOR_NOT_PRESENT; - else - p->descriptor_type = PTE_DESCRIPTOR_SMALL_PAGE; - - p->cacheable = p->bufferable = (flags & PAGE_CACHEABLE) != 0; - - /* default access permission */ - p->access_permission_0 = p->access_permission_1 = - p->access_permission_2 = p->access_permission_3 = - PTE_AP_USER_NO_KERNEL_RW; - - if (flags & PAGE_USER) { - if (flags & PAGE_READ) { - p->access_permission_0 = p->access_permission_1 = - p->access_permission_2 = p->access_permission_3 = - PTE_AP_USER_RO_KERNEL_RW; - } - if (flags & PAGE_WRITE) { - p->access_permission_0 = p->access_permission_1 = - p->access_permission_2 = p->access_permission_3 = - PTE_AP_USER_RW_KERNEL_RW; - } - } -} - -NO_TRACE static inline void set_pt_level1_present(pte_t *pt, size_t i) -{ - pte_level1_t *p = &pt[i].l1; - - p->descriptor_type = PTE_DESCRIPTOR_SMALL_PAGE; -} - -extern void page_arch_init(void); - -#endif /* __ASM__ */ +#if defined(PROCESSOR_armv6) | defined(PROCESSOR_armv7_a) +#include "page_armv6.h" +#elif defined(PROCESSOR_armv4) | defined(PROCESSOR_armv5) +#include "page_armv4.h" +#else +#error "Unsupported architecture" +#endif #endif Index: kernel/arch/arm32/include/mm/page_armv4.h =================================================================== --- kernel/arch/arm32/include/mm/page_armv4.h (revision 71d09d6e1da31c7024293452978a24f0987dfd58) +++ kernel/arch/arm32/include/mm/page_armv4.h (revision 71d09d6e1da31c7024293452978a24f0987dfd58) @@ -0,0 +1,269 @@ +/* + * Copyright (c) 2007 Pavel Jancik, Michal Kebrt + * Copyright (c) 2012 Jan Vesely + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * - Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * - Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * - The name of the author may not be used to endorse or promote products + * derived from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR + * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES + * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. + * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT + * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF + * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +/** @addtogroup arm32mm + * @{ + */ +/** @file + * @brief Paging related declarations. + */ + +#ifndef KERN_arm32_PAGE_armv4_H_ +#define KERN_arm32_PAGE_armv4_H_ + +#ifndef KERN_arm32_PAGE_H_ +#error "Do not include arch specific page.h directly use generic page.h instead" +#endif + +/* Macros for querying the last-level PTE entries. */ +#define PTE_VALID_ARCH(pte) \ + (*((uint32_t *) (pte)) != 0) +#define PTE_PRESENT_ARCH(pte) \ + (((pte_t *) (pte))->l0.descriptor_type != 0) +#define PTE_GET_FRAME_ARCH(pte) \ + (((pte_t *) (pte))->l1.frame_base_addr << FRAME_WIDTH) +#define PTE_WRITABLE_ARCH(pte) \ + (((pte_t *) (pte))->l1.access_permission_0 == PTE_AP_USER_RW_KERNEL_RW) +#define PTE_EXECUTABLE_ARCH(pte) \ + 1 + +#ifndef __ASM__ + +/** Level 0 page table entry. */ +typedef struct { + /* 0b01 for coarse tables, see below for details */ + unsigned descriptor_type : 2; + unsigned impl_specific : 3; + unsigned domain : 4; + unsigned should_be_zero : 1; + + /* Pointer to the coarse 2nd level page table (holding entries for small + * (4KB) or large (64KB) pages. ARM also supports fine 2nd level page + * tables that may hold even tiny pages (1KB) but they are bigger (4KB + * per table in comparison with 1KB per the coarse table) + */ + unsigned coarse_table_addr : 22; +} ATTRIBUTE_PACKED pte_level0_t; + +/** Level 1 page table entry (small (4KB) pages used). */ +typedef struct { + + /* 0b10 for small pages */ + unsigned descriptor_type : 2; + unsigned bufferable : 1; + unsigned cacheable : 1; + + /* access permissions for each of 4 subparts of a page + * (for each 1KB when small pages used */ + unsigned access_permission_0 : 2; + unsigned access_permission_1 : 2; + unsigned access_permission_2 : 2; + unsigned access_permission_3 : 2; + unsigned frame_base_addr : 20; +} ATTRIBUTE_PACKED pte_level1_t; + +typedef union { + pte_level0_t l0; + pte_level1_t l1; +} pte_t; + +/* Level 1 page tables access permissions */ + +/** User mode: no access, privileged mode: no access. */ +#define PTE_AP_USER_NO_KERNEL_NO 0 + +/** User mode: no access, privileged mode: read/write. */ +#define PTE_AP_USER_NO_KERNEL_RW 1 + +/** User mode: read only, privileged mode: read/write. */ +#define PTE_AP_USER_RO_KERNEL_RW 2 + +/** User mode: read/write, privileged mode: read/write. */ +#define PTE_AP_USER_RW_KERNEL_RW 3 + + +/* pte_level0_t and pte_level1_t descriptor_type flags */ + +/** pte_level0_t and pte_level1_t "not present" flag (used in descriptor_type). */ +#define PTE_DESCRIPTOR_NOT_PRESENT 0 + +/** pte_level0_t coarse page table flag (used in descriptor_type). */ +#define PTE_DESCRIPTOR_COARSE_TABLE 1 + +/** pte_level1_t small page table flag (used in descriptor type). */ +#define PTE_DESCRIPTOR_SMALL_PAGE 2 + + +/** Sets the address of level 0 page table. + * + * @param pt Pointer to the page table to set. + * + */ +NO_TRACE static inline void set_ptl0_addr(pte_t *pt) +{ + asm volatile ( + "mcr p15, 0, %[pt], c2, c0, 0\n" + :: [pt] "r" (pt) + ); +} + + +/** Returns level 0 page table entry flags. + * + * @param pt Level 0 page table. + * @param i Index of the entry to return. + * + */ +NO_TRACE static inline int get_pt_level0_flags(pte_t *pt, size_t i) +{ + pte_level0_t *p = &pt[i].l0; + int np = (p->descriptor_type == PTE_DESCRIPTOR_NOT_PRESENT); + + return (np << PAGE_PRESENT_SHIFT) | (1 << PAGE_USER_SHIFT) | + (1 << PAGE_READ_SHIFT) | (1 << PAGE_WRITE_SHIFT) | + (1 << PAGE_EXEC_SHIFT) | (1 << PAGE_CACHEABLE_SHIFT); +} + +/** Returns level 1 page table entry flags. + * + * @param pt Level 1 page table. + * @param i Index of the entry to return. + * + */ +NO_TRACE static inline int get_pt_level1_flags(pte_t *pt, size_t i) +{ + pte_level1_t *p = &pt[i].l1; + + int dt = p->descriptor_type; + int ap = p->access_permission_0; + + return ((dt == PTE_DESCRIPTOR_NOT_PRESENT) << PAGE_PRESENT_SHIFT) | + ((ap == PTE_AP_USER_RO_KERNEL_RW) << PAGE_READ_SHIFT) | + ((ap == PTE_AP_USER_RW_KERNEL_RW) << PAGE_READ_SHIFT) | + ((ap == PTE_AP_USER_RW_KERNEL_RW) << PAGE_WRITE_SHIFT) | + ((ap != PTE_AP_USER_NO_KERNEL_RW) << PAGE_USER_SHIFT) | + ((ap == PTE_AP_USER_NO_KERNEL_RW) << PAGE_READ_SHIFT) | + ((ap == PTE_AP_USER_NO_KERNEL_RW) << PAGE_WRITE_SHIFT) | + (1 << PAGE_EXEC_SHIFT) | + (p->bufferable << PAGE_CACHEABLE); +} + +/** Sets flags of level 0 page table entry. + * + * @param pt level 0 page table + * @param i index of the entry to be changed + * @param flags new flags + * + */ +NO_TRACE static inline void set_pt_level0_flags(pte_t *pt, size_t i, int flags) +{ + pte_level0_t *p = &pt[i].l0; + + if (flags & PAGE_NOT_PRESENT) { + p->descriptor_type = PTE_DESCRIPTOR_NOT_PRESENT; + /* + * Ensures that the entry will be recognized as valid when + * PTE_VALID_ARCH applied. + */ + p->should_be_zero = 1; + } else { + p->descriptor_type = PTE_DESCRIPTOR_COARSE_TABLE; + p->should_be_zero = 0; + } +} + + +/** Sets flags of level 1 page table entry. + * + * We use same access rights for the whole page. When page + * is not preset we store 1 in acess_rigts_3 so that at least + * one bit is 1 (to mark correct page entry, see #PAGE_VALID_ARCH). + * + * @param pt Level 1 page table. + * @param i Index of the entry to be changed. + * @param flags New flags. + * + */ +NO_TRACE static inline void set_pt_level1_flags(pte_t *pt, size_t i, int flags) +{ + pte_level1_t *p = &pt[i].l1; + + if (flags & PAGE_NOT_PRESENT) + p->descriptor_type = PTE_DESCRIPTOR_NOT_PRESENT; + else + p->descriptor_type = PTE_DESCRIPTOR_SMALL_PAGE; + + p->cacheable = p->bufferable = (flags & PAGE_CACHEABLE) != 0; + + /* default access permission */ + p->access_permission_0 = p->access_permission_1 = + p->access_permission_2 = p->access_permission_3 = + PTE_AP_USER_NO_KERNEL_RW; + + if (flags & PAGE_USER) { + if (flags & PAGE_READ) { + p->access_permission_0 = p->access_permission_1 = + p->access_permission_2 = p->access_permission_3 = + PTE_AP_USER_RO_KERNEL_RW; + } + if (flags & PAGE_WRITE) { + p->access_permission_0 = p->access_permission_1 = + p->access_permission_2 = p->access_permission_3 = + PTE_AP_USER_RW_KERNEL_RW; + } + } +} + +NO_TRACE static inline void set_pt_level0_present(pte_t *pt, size_t i) +{ + pte_level0_t *p = &pt[i].l0; + + p->should_be_zero = 0; + write_barrier(); + p->descriptor_type = PTE_DESCRIPTOR_COARSE_TABLE; +} + + +NO_TRACE static inline void set_pt_level1_present(pte_t *pt, size_t i) +{ + pte_level1_t *p = &pt[i].l1; + + p->descriptor_type = PTE_DESCRIPTOR_SMALL_PAGE; +} + + +extern void page_arch_init(void); + + +#endif /* __ASM__ */ + +#endif + +/** @} + */ Index: kernel/arch/arm32/include/mm/page_armv6.h =================================================================== --- kernel/arch/arm32/include/mm/page_armv6.h (revision 71d09d6e1da31c7024293452978a24f0987dfd58) +++ kernel/arch/arm32/include/mm/page_armv6.h (revision 71d09d6e1da31c7024293452978a24f0987dfd58) @@ -0,0 +1,285 @@ +/* + * Copyright (c) 2012 Jan Vesely + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * - Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * - Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * - The name of the author may not be used to endorse or promote products + * derived from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR + * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES + * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. + * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT + * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF + * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +/** @addtogroup arm32mm + * @{ + */ +/** @file + * @brief Paging related declarations. + */ + +#ifndef KERN_arm32_PAGE_armv7_H_ +#define KERN_arm32_PAGE_armv7_H_ + +#ifndef KERN_arm32_PAGE_H_ +#error "Do not include arch specific page.h directly use generic page.h instead" +#endif + +/* Macros for querying the last-level PTE entries. */ +#define PTE_VALID_ARCH(pte) \ + (*((uint32_t *) (pte)) != 0) +#define PTE_PRESENT_ARCH(pte) \ + (((pte_t *) (pte))->l0.descriptor_type != 0) +#define PTE_GET_FRAME_ARCH(pte) \ + (((pte_t *) (pte))->l1.frame_base_addr << FRAME_WIDTH) +#define PTE_WRITABLE_ARCH(pte) \ + (((pte_t *) (pte))->l1.access_permission_1 != PTE_AP1_RO) +#define PTE_EXECUTABLE_ARCH(pte) \ + (((pte_t *) (pte))->l1.descriptor_type != PTE_DESCRIPTOR_SMALL_PAGE_NX) + +#ifndef __ASM__ + +/** Level 0 page table entry. */ +typedef struct { + /* 0b01 for coarse tables, see below for details */ + unsigned descriptor_type : 2; + unsigned pxn : 1; + unsigned ns : 1; + unsigned should_be_zero_0 : 1; + unsigned domain : 4; + unsigned should_be_zero_1 : 1; + + /* Pointer to the coarse 2nd level page table (holding entries for small + * (4KB) or large (64KB) pages. ARM also supports fine 2nd level page + * tables that may hold even tiny pages (1KB) but they are bigger (4KB + * per table in comparison with 1KB per the coarse table) + */ + unsigned coarse_table_addr : 22; +} ATTRIBUTE_PACKED pte_level0_t; + +/** Level 1 page table entry (small (4KB) pages used). */ +typedef struct { + + /* 0b10 for small pages, 0b11 for NX small pages */ + unsigned descriptor_type : 2; + unsigned bufferable : 1; + unsigned cacheable : 1; + unsigned access_permission_0 : 2; + unsigned tex : 3; + unsigned access_permission_1 : 1; + unsigned shareable : 1; + unsigned non_global : 1; + unsigned frame_base_addr : 20; +} ATTRIBUTE_PACKED pte_level1_t; + +typedef union { + pte_level0_t l0; + pte_level1_t l1; +} pte_t; + +/* Level 1 page tables access permissions */ + +/** User mode: no access, privileged mode: no access. */ +#define PTE_AP0_USER_NO_KERNEL_NO 0 + +/** User mode: no access, privileged mode: read/write. */ +#define PTE_AP0_USER_NO_KERNEL_FULL 1 + +/** User mode: read only, privileged mode: read/write. */ +#define PTE_AP0_USER_LIMITED_KERNEL_FULL 2 + +/** User mode: read/write, privileged mode: read/write. */ +#define PTE_AP0_USER_FULL_KERNEL_FULL 3 + +/** Allow writes */ +#define PTE_AP1_RO 1 + + +/* pte_level0_t and pte_level1_t descriptor_type flags */ + +/** pte_level0_t and pte_level1_t "not present" flag (used in descriptor_type). */ +#define PTE_DESCRIPTOR_NOT_PRESENT 0 + +/** pte_level0_t coarse page table flag (used in descriptor_type). */ +#define PTE_DESCRIPTOR_COARSE_TABLE 1 + +/** pte_level1_t small page table flag (used in descriptor type). */ +#define PTE_DESCRIPTOR_SMALL_PAGE 2 + +/** pte_level1_t small page table flag with NX (used in descriptor type). */ +#define PTE_DESCRIPTOR_SMALL_PAGE_NX 3 + +/** Sets the address of level 0 page table. + * + * @param pt Pointer to the page table to set. + * + */ +NO_TRACE static inline void set_ptl0_addr(pte_t *pt) +{ + asm volatile ( + "mcr p15, 0, %[pt], c2, c0, 0\n" + :: [pt] "r" (pt) + ); +} + + +/** Returns level 0 page table entry flags. + * + * @param pt Level 0 page table. + * @param i Index of the entry to return. + * + */ +NO_TRACE static inline int get_pt_level0_flags(pte_t *pt, size_t i) +{ + const pte_level0_t *p = &pt[i].l0; + const unsigned np = (p->descriptor_type == PTE_DESCRIPTOR_NOT_PRESENT); + + return (np << PAGE_PRESENT_SHIFT) | (1 << PAGE_USER_SHIFT) | + (1 << PAGE_READ_SHIFT) | (1 << PAGE_WRITE_SHIFT) | + (1 << PAGE_EXEC_SHIFT) | (1 << PAGE_CACHEABLE_SHIFT); +} + +/** Returns level 1 page table entry flags. + * + * @param pt Level 1 page table. + * @param i Index of the entry to return. + * + */ +NO_TRACE static inline int get_pt_level1_flags(pte_t *pt, size_t i) +{ + const pte_level1_t *p = &pt[i].l1; + + const unsigned dt = p->descriptor_type; + const unsigned ap0 = p->access_permission_0; + const unsigned ap1 = p->access_permission_1; + + return ((dt == PTE_DESCRIPTOR_NOT_PRESENT) << PAGE_PRESENT_SHIFT) | + ((dt != PTE_DESCRIPTOR_SMALL_PAGE_NX) << PAGE_EXEC_SHIFT) | + ((ap0 == PTE_AP0_USER_LIMITED_KERNEL_FULL) << PAGE_READ_SHIFT) | + ((ap0 == PTE_AP0_USER_FULL_KERNEL_FULL) << PAGE_READ_SHIFT) | + ((ap0 == PTE_AP0_USER_NO_KERNEL_FULL) << PAGE_READ_SHIFT) | + ((ap0 != PTE_AP0_USER_NO_KERNEL_FULL) << PAGE_USER_SHIFT) | + (((ap1 != PTE_AP1_RO) && (ap0 == PTE_AP0_USER_FULL_KERNEL_FULL)) << PAGE_WRITE_SHIFT) | + (((ap1 != PTE_AP1_RO) && (ap0 == PTE_AP0_USER_NO_KERNEL_FULL)) << PAGE_WRITE_SHIFT) | + (p->bufferable << PAGE_CACHEABLE); +} + +/** Sets flags of level 0 page table entry. + * + * @param pt level 0 page table + * @param i index of the entry to be changed + * @param flags new flags + * + */ +NO_TRACE static inline void set_pt_level0_flags(pte_t *pt, size_t i, int flags) +{ + pte_level0_t *p = &pt[i].l0; + + if (flags & PAGE_NOT_PRESENT) { + p->descriptor_type = PTE_DESCRIPTOR_NOT_PRESENT; + /* + * Ensures that the entry will be recognized as valid when + * PTE_VALID_ARCH applied. + */ + p->should_be_zero_0 = 1; + p->should_be_zero_1 = 1; + } else { + p->descriptor_type = PTE_DESCRIPTOR_COARSE_TABLE; + p->should_be_zero_0 = 0; + p->should_be_zero_1 = 0; + p->domain = 0; + p->ns = 0; + } +} + + +/** Sets flags of level 1 page table entry. + * + * We use same access rights for the whole page. When page + * is not preset we store 1 in acess_rigts_3 so that at least + * one bit is 1 (to mark correct page entry, see #PAGE_VALID_ARCH). + * + * @param pt Level 1 page table. + * @param i Index of the entry to be changed. + * @param flags New flags. + * + */ +NO_TRACE static inline void set_pt_level1_flags(pte_t *pt, size_t i, int flags) +{ + pte_level1_t *p = &pt[i].l1; + + if (flags & PAGE_NOT_PRESENT) { + p->descriptor_type = PTE_DESCRIPTOR_NOT_PRESENT; + } else { + if (flags & PAGE_EXEC) + p->descriptor_type = PTE_DESCRIPTOR_SMALL_PAGE; + else + p->descriptor_type = PTE_DESCRIPTOR_SMALL_PAGE_NX; + } + + /* tex=0 buf=1 and cache=1 => normal memory + * tex=0 buf=1 and cache=0 => shareable device mmio + */ + p->cacheable = (flags & PAGE_CACHEABLE); + p->bufferable = 1; + p->tex = 0; + + /* Shareable is ignored for devices (non-cacheable), + * turn it on for normal memory. */ + p->shareable = 1; + + p->non_global = !(flags & PAGE_GLOBAL); + + /* default access permission: kernel only*/ + p->access_permission_0 = PTE_AP0_USER_NO_KERNEL_FULL; + + if (flags & PAGE_USER) { + p->access_permission_0 = PTE_AP0_USER_FULL_KERNEL_FULL; + // TODO Fix kernel to use PAGE_WRITE flag properly and + // apply this for kernel pages as well. + if (!(flags & PAGE_WRITE)) + p->access_permission_1 = PTE_AP1_RO; + } +} + +NO_TRACE static inline void set_pt_level0_present(pte_t *pt, size_t i) +{ + pte_level0_t *p = &pt[i].l0; + + p->should_be_zero_0 = 0; + p->should_be_zero_1 = 0; + write_barrier(); + p->descriptor_type = PTE_DESCRIPTOR_COARSE_TABLE; +} + +NO_TRACE static inline void set_pt_level1_present(pte_t *pt, size_t i) +{ + pte_level1_t *p = &pt[i].l1; + + p->descriptor_type = PTE_DESCRIPTOR_SMALL_PAGE; +} + + +extern void page_arch_init(void); + +#endif /* __ASM__ */ + +#endif + +/** @} + */ Index: kernel/arch/arm32/include/mm/page_fault.h =================================================================== --- kernel/arch/arm32/include/mm/page_fault.h (revision c4c2406caea2227486ba46e0c0ca00fff2b1fe13) +++ kernel/arch/arm32/include/mm/page_fault.h (revision 71d09d6e1da31c7024293452978a24f0987dfd58) @@ -40,18 +40,28 @@ -/** Decribes CP15 "fault status register" (FSR). */ -typedef struct { - unsigned status : 3; - unsigned domain : 4; - unsigned zero : 1; - unsigned should_be_zero : 24; -} ATTRIBUTE_PACKED fault_status_t; - - -/** Help union used for casting integer value into #fault_status_t. */ +/** Decribes CP15 "fault status register" (FSR). + * + * See ARM Architecture Reference Manual ch. B4.9.6 (pdf p.743). + */ typedef union { - fault_status_t fs; - uint32_t dummy; -} fault_status_union_t; + struct { + unsigned status : 4; + unsigned domain : 4; + unsigned zero : 1; + unsigned lpae : 1; /**< Needs LPAE support implemented */ + unsigned fs : 1; /**< armv6+ mandated, earlier IPLM. DEFINED */ + unsigned wr : 1; /**< armv6+ only */ + unsigned ext : 1 ; /**< external abort */ + unsigned cm : 1; /**< Cache maintenance, needs LPAE support */ + unsigned should_be_zero : 18; + } data; + struct { + unsigned status : 4; + unsigned sbz0 : 6; + unsigned fs : 1; + unsigned should_be_zero : 21; + } inst; + uint32_t raw; +} fault_status_t; Index: kernel/arch/arm32/include/regutils.h =================================================================== --- kernel/arch/arm32/include/regutils.h (revision c4c2406caea2227486ba46e0c0ca00fff2b1fe13) +++ kernel/arch/arm32/include/regutils.h (revision 71d09d6e1da31c7024293452978a24f0987dfd58) @@ -41,5 +41,27 @@ #define STATUS_REG_MODE_MASK 0x1f -#define CP15_R1_HIGH_VECTORS_BIT (1 << 13) +/* COntrol register bit values see ch. B4.1.130 of ARM Architecture Reference + * Manual ARMv7-A and ARMv7-R edition, page 1687 */ +#define CP15_R1_MMU_EN (1 << 0) +#define CP15_R1_ALIGN_CHECK_EN (1 << 1) /* Allow alignemnt check */ +#define CP15_R1_CACHE_EN (1 << 2) +#define CP15_R1_CP15_BARRIER_EN (1 << 5) +#define CP15_R1_B_EN (1 << 7) /* ARMv6- only big endian switch */ +#define CP15_R1_SWAP_EN (1 << 10) +#define CP15_R1_BRANCH_PREDICT_EN (1 << 11) +#define CP15_R1_INST_CACHE_EN (1 << 12) +#define CP15_R1_HIGH_VECTORS_EN (1 << 13) +#define CP15_R1_ROUND_ROBIN_EN (1 << 14) +#define CP15_R1_HW_ACCESS_FLAG_EN (1 << 17) +#define CP15_R1_WRITE_XN_EN (1 << 19) /* Only if virt. supported */ +#define CP15_R1_USPCE_WRITE_XN_EN (1 << 20) /* Only if virt. supported */ +#define CP15_R1_FAST_IRQ_EN (1 << 21) /* Disbale impl.specific features */ +#define CP15_R1_UNALIGNED_EN (1 << 22) /* Must be 1 on armv7 */ +#define CP15_R1_IRQ_VECTORS_EN (1 << 24) +#define CP15_R1_BIG_ENDIAN_EXC (1 << 25) +#define CP15_R1_NMFI_EN (1 << 27) +#define CP15_R1_TEX_REMAP_EN (1 << 28) +#define CP15_R1_ACCESS_FLAG_EN (1 << 29) +#define CP15_R1_THUMB_EXC_EN (1 << 30) /* ARM Processor Operation Modes */ Index: kernel/arch/arm32/src/arm32.c =================================================================== --- kernel/arch/arm32/src/arm32.c (revision c4c2406caea2227486ba46e0c0ca00fff2b1fe13) +++ kernel/arch/arm32/src/arm32.c (revision 71d09d6e1da31c7024293452978a24f0987dfd58) @@ -49,4 +49,5 @@ #include #include +#include /** Performs arm32-specific initialization before main_bsp() is called. */ @@ -116,4 +117,8 @@ { machine_input_init(); + const char *platform = machine_get_platform_name(); + + sysinfo_set_item_data("platform", NULL, (void *) platform, + str_size(platform)); } Index: kernel/arch/arm32/src/cpu/cpu.c =================================================================== --- kernel/arch/arm32/src/cpu/cpu.c (revision c4c2406caea2227486ba46e0c0ca00fff2b1fe13) +++ kernel/arch/arm32/src/cpu/cpu.c (revision 71d09d6e1da31c7024293452978a24f0987dfd58) @@ -44,14 +44,17 @@ /** Implementators (vendor) names */ static const char *imp_data[] = { - "?", /* IMP_DATA_START_OFFSET */ - "ARM Ltd", /* 0x41 */ - "", /* 0x42 */ - "", /* 0x43 */ - "Digital Equipment Corporation", /* 0x44 */ - "", "", "", "", "", "", "", "", "", "", /* 0x45 - 0x4e */ - "", "", "", "", "", "", "", "", "", "", /* 0x4f - 0x58 */ - "", "", "", "", "", "", "", "", "", "", /* 0x59 - 0x62 */ - "", "", "", "", "", "", /* 0x63 - 0x68 */ - "Intel Corporation" /* 0x69 */ + "?", /* IMP_DATA_START_OFFSET */ + "ARM Limited", /* 0x41 */ + "", "", /* 0x42 - 0x43 */ + "Digital Equipment Corporation", /* 0x44 */ + "", "", "", "", "", "", "", "", /* 0x45 - 0x4c */ + "Motorola, Freescale Semicondutor Inc.", /* 0x4d */ + "", "", "", /* 0x4e - 0x50 */ + "Qualcomm Inc.", /* 0x51 */ + "", "", "", "", /* 0x52 - 0x55 */ + "Marvell Semiconductor", /* 0x56 */ + "", "", "", "", "", "", "", "", "", "", /* 0x57 - 0x60 */ + "", "", "", "", "", "", "", "", /* 0x61 - 0x68 */ + "Intel Corporation" /* 0x69 */ }; @@ -94,11 +97,47 @@ } -/** Does nothing on ARM. */ +/** Enables unaligned access and caching for armv6+ */ void cpu_arch_init(void) { +#if defined(PROCESSOR_armv7_a) | defined(PROCESSOR_armv6) + uint32_t control_reg = 0; + asm volatile ( + "mrc p15, 0, %[control_reg], c1, c0" + : [control_reg] "=r" (control_reg) + ); + + /* Turn off tex remap, RAZ ignores writes prior to armv7 */ + control_reg &= ~CP15_R1_TEX_REMAP_EN; + /* Turn off accessed flag, RAZ ignores writes prior to armv7 */ + control_reg &= ~(CP15_R1_ACCESS_FLAG_EN | CP15_R1_HW_ACCESS_FLAG_EN); + /* Enable unaligned access, RAZ ignores writes prior to armv6 + * switchable on armv6, RAO ignores writes on armv7, + * see ARM Architecture Reference Manual ARMv7-A and ARMv7-R edition + * L.3.1 (p. 2456) */ + control_reg |= CP15_R1_UNALIGNED_EN; + /* Disable alignment checks, this turns unaligned access to undefined, + * unless U bit is set. */ + control_reg &= ~CP15_R1_ALIGN_CHECK_EN; + /* Enable caching, On arm prior to armv7 there is only one level + * of caches. Data cache is coherent. + * "This means that the behavior of accesses from the same observer to + * different VAs, that are translated to the same PA + * with the same memory attributes, is fully coherent." + * ARM Architecture Reference Manual ARMv7-A and ARMv7-R Edition + * B3.11.1 (p. 1383) + * ICache coherency is elaborate on in barrier.h. + * We are safe to turn these on. + */ + control_reg |= CP15_R1_CACHE_EN | CP15_R1_INST_CACHE_EN; + + asm volatile ( + "mcr p15, 0, %[control_reg], c1, c0" + :: [control_reg] "r" (control_reg) + ); +#endif } /** Retrieves processor identification and stores it to #CPU.arch */ -void cpu_identify(void) +void cpu_identify(void) { arch_cpu_identify(&CPU->arch); @@ -112,11 +151,12 @@ cpu_arch_t * cpu_arch = &m->arch; - if ((cpu_arch->imp_num) > 0 && - (cpu_arch->imp_num < (imp_data_length + IMP_DATA_START_OFFSET))) { + const unsigned imp_offset = cpu_arch->imp_num - IMP_DATA_START_OFFSET; + + if (imp_offset < imp_data_length) { vendor = imp_data[cpu_arch->imp_num - IMP_DATA_START_OFFSET]; } - if ((cpu_arch->arch_num) > 0 && - (cpu_arch->arch_num < arch_data_length)) { + // TODO CPUs with arch_num == 0xf use CPUID scheme for identification + if (cpu_arch->arch_num < arch_data_length) { architecture = arch_data[cpu_arch->arch_num]; } Index: kernel/arch/arm32/src/exception.c =================================================================== --- kernel/arch/arm32/src/exception.c (revision c4c2406caea2227486ba46e0c0ca00fff2b1fe13) +++ kernel/arch/arm32/src/exception.c (revision 71d09d6e1da31c7024293452978a24f0987dfd58) @@ -117,9 +117,24 @@ #ifdef HIGH_EXCEPTION_VECTORS -/** Activates use of high exception vectors addresses. */ +/** Activates use of high exception vectors addresses. + * + * "High vectors were introduced into some implementations of ARMv4 and are + * required in ARMv6 implementations. High vectors allow the exception vector + * locations to be moved from their normal address range 0x00000000-0x0000001C + * at the bottom of the 32-bit address space, to an alternative address range + * 0xFFFF0000-0xFFFF001C near the top of the address space. These alternative + * locations are known as the high vectors. + * + * Prior to ARMv6, it is IMPLEMENTATION DEFINED whether the high vectors are + * supported. When they are, a hardware configuration input selects whether + * the normal vectors or the high vectors are to be used from + * reset." ARM Architecture Reference Manual A2.6.11 (p. 64 in the PDF). + * + * ARM920T (gta02) TRM A2.3.5 (PDF p. 36) and ARM926EJ-S (icp) 2.3.2 (PDF p. 42) + * say that armv4 an armv5 chips that we support implement this. + */ static void high_vectors(void) { - uint32_t control_reg; - + uint32_t control_reg = 0; asm volatile ( "mrc p15, 0, %[control_reg], c1, c0" @@ -128,5 +143,5 @@ /* switch on the high vectors bit */ - control_reg |= CP15_R1_HIGH_VECTORS_BIT; + control_reg |= CP15_R1_HIGH_VECTORS_EN; asm volatile ( @@ -153,4 +168,5 @@ void exception_init(void) { + // TODO check for availability of high vectors for <= armv5 #ifdef HIGH_EXCEPTION_VECTORS high_vectors(); Index: kernel/arch/arm32/src/mach/beagleboardxm/beagleboardxm.c =================================================================== --- kernel/arch/arm32/src/mach/beagleboardxm/beagleboardxm.c (revision 71d09d6e1da31c7024293452978a24f0987dfd58) +++ kernel/arch/arm32/src/mach/beagleboardxm/beagleboardxm.c (revision 71d09d6e1da31c7024293452978a24f0987dfd58) @@ -0,0 +1,261 @@ +/* + * Copyright (c) 2012 Jan Vesely + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * - Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * - Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * - The name of the author may not be used to endorse or promote products + * derived from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR + * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES + * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. + * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT + * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF + * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ +/** @addtogroup arm32beagleboardxm + * @{ + */ +/** @file + * @brief BeagleBoard-xM platform driver. + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +static void bbxm_init(void); +static void bbxm_timer_irq_start(void); +static void bbxm_cpu_halt(void); +static void bbxm_get_memory_extents(uintptr_t *start, size_t *size); +static void bbxm_irq_exception(unsigned int exc_no, istate_t *istate); +static void bbxm_frame_init(void); +static void bbxm_output_init(void); +static void bbxm_input_init(void); +static size_t bbxm_get_irq_count(void); +static const char *bbxm_get_platform_name(void); + +#define BBXM_MEMORY_START 0x80000000 /* physical */ +#define BBXM_MEMORY_SIZE 0x20000000 /* 512 MB */ + +static struct beagleboard { + amdm37x_dispc_regs_t *dispc; + amdm37x_irc_regs_t *irc_addr; + amdm37x_uart_t uart; + amdm37x_gpt_t timer; +} beagleboard; + +struct arm_machine_ops bbxm_machine_ops = { + .machine_init = bbxm_init, + .machine_timer_irq_start = bbxm_timer_irq_start, + .machine_cpu_halt = bbxm_cpu_halt, + .machine_get_memory_extents = bbxm_get_memory_extents, + .machine_irq_exception = bbxm_irq_exception, + .machine_frame_init = bbxm_frame_init, + .machine_output_init = bbxm_output_init, + .machine_input_init = bbxm_input_init, + .machine_get_irq_count = bbxm_get_irq_count, + .machine_get_platform_name = bbxm_get_platform_name +}; + +static irq_ownership_t bb_timer_irq_claim(irq_t *irq) +{ + return IRQ_ACCEPT; +} + +static void bbxm_setup_fb(unsigned width, unsigned height, unsigned bpp) +{ + const unsigned pixel_bytes = (bpp / 8); + const size_t size = ALIGN_UP(width * height * pixel_bytes, FRAME_SIZE); + const unsigned frames = size / FRAME_SIZE; + unsigned order = 0; + unsigned frame = 1; + while (frame < frames) { + frame *= 2; + ++order; + } + /* prefer highmem as we don't care about virtual mapping. */ + void *buffer = frame_alloc(order, FRAME_LOWMEM); + if (!buffer) { + printf("Failed to allocate framebuffer.\n"); + return; + } + + amdm37x_dispc_setup_fb(beagleboard.dispc, width, height, bpp, + (uintptr_t) buffer); + + fb_properties_t prop = { + .addr = (uintptr_t)buffer, + .offset = 0, + .x = width, + .y = height, + .scan = width * pixel_bytes, + .visual = VISUAL_RGB_5_6_5_LE + }; + switch (bpp) + { + case 8: + prop.visual = VISUAL_INDIRECT_8; break; + case 16: + prop.visual = VISUAL_RGB_5_6_5_LE; break; + case 24: + prop.visual = VISUAL_BGR_8_8_8; break; + case 32: + prop.visual = VISUAL_RGB_8_8_8_0; break; + default: + printf("Invalid framebuffer bit depth: bailing out.\n"); + return; + } + outdev_t *fb_dev = fb_init(&prop); + if (fb_dev) + stdout_wire(fb_dev); + +} + +static void bb_timer_irq_handler(irq_t *irq) +{ + /* + * We are holding a lock which prevents preemption. + * Release the lock, call clock() and reacquire the lock again. + */ + amdm37x_gpt_irq_ack(&beagleboard.timer); + spinlock_unlock(&irq->lock); + clock(); + spinlock_lock(&irq->lock); +} + +static void bbxm_init(void) +{ + /* Initialize interrupt controller */ + beagleboard.irc_addr = + (void *) km_map(AMDM37x_IRC_BASE_ADDRESS, AMDM37x_IRC_SIZE, + PAGE_NOT_CACHEABLE); + ASSERT(beagleboard.irc_addr); + amdm37x_irc_init(beagleboard.irc_addr); + + /* Map display controller */ + beagleboard.dispc = (void*) km_map(AMDM37x_DISPC_BASE_ADDRESS, + AMDM37x_DISPC_SIZE, PAGE_NOT_CACHEABLE); + ASSERT(beagleboard.dispc); + + /* Initialize timer. Use timer1, because it is in WKUP power domain + * (always on) and has special capabilities for precise 1ms ticks */ + amdm37x_gpt_timer_ticks_init(&beagleboard.timer, + AMDM37x_GPT1_BASE_ADDRESS, AMDM37x_GPT1_SIZE, HZ); +} + +static void bbxm_timer_irq_start(void) +{ + /* Initialize timer IRQ */ + static irq_t timer_irq; + irq_initialize(&timer_irq); + timer_irq.devno = device_assign_devno(); + timer_irq.inr = AMDM37x_GPT1_IRQ; + timer_irq.claim = bb_timer_irq_claim; + timer_irq.handler = bb_timer_irq_handler; + irq_register(&timer_irq); + + /* Enable timer interrupt */ + amdm37x_irc_enable(beagleboard.irc_addr, AMDM37x_GPT1_IRQ); + + /* Start timer here */ + amdm37x_gpt_timer_ticks_start(&beagleboard.timer); +} + +static void bbxm_cpu_halt(void) +{ + while (1); +} + +/** Get extents of available memory. + * + * @param start Place to store memory start address (physical). + * @param size Place to store memory size. + */ +static void bbxm_get_memory_extents(uintptr_t *start, size_t *size) +{ + *start = BBXM_MEMORY_START; + *size = BBXM_MEMORY_SIZE; +} + +static void bbxm_irq_exception(unsigned int exc_no, istate_t *istate) +{ + const unsigned inum = amdm37x_irc_inum_get(beagleboard.irc_addr); + amdm37x_irc_irq_ack(beagleboard.irc_addr); + + irq_t *irq = irq_dispatch_and_lock(inum); + if (irq) { + /* The IRQ handler was found. */ + irq->handler(irq); + spinlock_unlock(&irq->lock); + } else { + /* Spurious interrupt.*/ + printf("cpu%d: spurious interrupt (inum=%d)\n", + CPU->id, inum); + } +} + +static void bbxm_frame_init(void) +{ +} + +static void bbxm_output_init(void) +{ +#ifdef CONFIG_FB + bbxm_setup_fb(CONFIG_BFB_WIDTH, CONFIG_BFB_HEIGHT, CONFIG_BFB_BPP); +#else + (void)bbxm_setup_fb; +#endif + /* UART3 is wired to external RS232 connector */ + const bool ok = amdm37x_uart_init(&beagleboard.uart, + AMDM37x_UART3_IRQ, AMDM37x_UART3_BASE_ADDRESS, AMDM37x_UART3_SIZE); + if (ok) { + stdout_wire(&beagleboard.uart.outdev); + } +} + +static void bbxm_input_init(void) +{ + srln_instance_t *srln_instance = srln_init(); + if (srln_instance) { + indev_t *sink = stdin_wire(); + indev_t *srln = srln_wire(srln_instance, sink); + amdm37x_uart_input_wire(&beagleboard.uart, srln); + amdm37x_irc_enable(beagleboard.irc_addr, AMDM37x_UART3_IRQ); + } +} + +size_t bbxm_get_irq_count(void) +{ + return AMDM37x_IRC_IRQ_COUNT; +} + +const char *bbxm_get_platform_name(void) +{ + return "beagleboardxm"; +} + +/** + * @} + */ Index: kernel/arch/arm32/src/machine_func.c =================================================================== --- kernel/arch/arm32/src/machine_func.c (revision c4c2406caea2227486ba46e0c0ca00fff2b1fe13) +++ kernel/arch/arm32/src/machine_func.c (revision 71d09d6e1da31c7024293452978a24f0987dfd58) @@ -42,4 +42,5 @@ #include #include +#include /** Pointer to machine_ops structure being used. */ @@ -55,4 +56,6 @@ #elif defined(MACHINE_integratorcp) machine_ops = &icp_machine_ops; +#elif defined(MACHINE_beagleboardxm) + machine_ops = &bbxm_machine_ops; #else #error Machine type not defined. @@ -131,4 +134,10 @@ } +const char * machine_get_platform_name(void) +{ + if (machine_ops->machine_get_platform_name) + return machine_ops->machine_get_platform_name(); + return NULL; +} /** @} */ Index: kernel/arch/arm32/src/mm/page.c =================================================================== --- kernel/arch/arm32/src/mm/page.c (revision c4c2406caea2227486ba46e0c0ca00fff2b1fe13) +++ kernel/arch/arm32/src/mm/page.c (revision 71d09d6e1da31c7024293452978a24f0987dfd58) @@ -52,14 +52,16 @@ void page_arch_init(void) { - int flags = PAGE_CACHEABLE; + int flags = PAGE_CACHEABLE | PAGE_EXEC; page_mapping_operations = &pt_mapping_operations; page_table_lock(AS_KERNEL, true); - uintptr_t cur; - /* Kernel identity mapping */ - for (cur = PHYSMEM_START_ADDR; - cur < min(config.identity_size, config.physmem_end); + //FIXME: We need to consider the possibility that + //identity_base > identity_size and physmem_end. + //This might lead to overflow if identity_size is too big. + for (uintptr_t cur = PHYSMEM_START_ADDR; + cur < min(KA2PA(config.identity_base) + + config.identity_size, config.physmem_end); cur += FRAME_SIZE) page_mapping_insert(AS_KERNEL, PA2KA(cur), cur, flags); Index: kernel/arch/arm32/src/mm/page_fault.c =================================================================== --- kernel/arch/arm32/src/mm/page_fault.c (revision c4c2406caea2227486ba46e0c0ca00fff2b1fe13) +++ kernel/arch/arm32/src/mm/page_fault.c (revision 71d09d6e1da31c7024293452978a24f0987dfd58) @@ -42,27 +42,124 @@ #include -/** Returns value stored in fault status register. + +/** + * FSR encoding ARM Architecture Reference Manual ARMv7-A and ARMv7-R edition. + * + * B3.13.3 page B3-1406 (PDF page 1406) + */ +typedef enum { + DFSR_SOURCE_ALIGN = 0x0001, + DFSR_SOURCE_CACHE_MAINTENANCE = 0x0004, + DFSR_SOURCE_SYNC_EXTERNAL_TRANSLATION_L1 = 0x000c, + DFSR_SOURCE_SYNC_EXTERNAL_TRANSLATION_L2 = 0x000e, + DFSR_SOURCE_SYNC_PARITY_TRANSLATION_L1 = 0x040c, + DFSR_SOURCE_SYNC_PARITY_TRANSLATION_L2 = 0x040e, + DFSR_SOURCE_TRANSLATION_L1 = 0x0005, + DFSR_SOURCE_TRANSLATION_L2 = 0x0007, + DFSR_SOURCE_ACCESS_FLAG_L1 = 0x0003, /**< @note: This used to be alignment enc. */ + DFSR_SOURCE_ACCESS_FLAG_L2 = 0x0006, + DFSR_SOURCE_DOMAIN_L1 = 0x0009, + DFSR_SOURCE_DOMAIN_L2 = 0x000b, + DFSR_SOURCE_PERMISSION_L1 = 0x000d, + DFSR_SOURCE_PERMISSION_L2 = 0x000f, + DFSR_SOURCE_DEBUG = 0x0002, + DFSR_SOURCE_SYNC_EXTERNAL = 0x0008, + DFSR_SOURCE_TLB_CONFLICT = 0x0400, + DFSR_SOURCE_LOCKDOWN = 0x0404, /**< @note: Implementation defined */ + DFSR_SOURCE_COPROCESSOR = 0x040a, /**< @note Implementation defined */ + DFSR_SOURCE_SYNC_PARITY = 0x0409, + DFSR_SOURCE_ASYNC_EXTERNAL = 0x0406, + DFSR_SOURCE_ASYNC_PARITY = 0x0408, + DFSR_SOURCE_MASK = 0x0000040f, +} dfsr_source_t; + +static inline const char * dfsr_source_to_str(dfsr_source_t source) +{ + switch (source) { + case DFSR_SOURCE_TRANSLATION_L1: + return "Translation fault L1"; + case DFSR_SOURCE_TRANSLATION_L2: + return "Translation fault L2"; + case DFSR_SOURCE_PERMISSION_L1: + return "Permission fault L1"; + case DFSR_SOURCE_PERMISSION_L2: + return "Permission fault L2"; + case DFSR_SOURCE_ALIGN: + return "Alignment fault"; + case DFSR_SOURCE_CACHE_MAINTENANCE: + return "Instruction cache maintenance fault"; + case DFSR_SOURCE_SYNC_EXTERNAL_TRANSLATION_L1: + return "Synchronous external abort on translation table walk level 1"; + case DFSR_SOURCE_SYNC_EXTERNAL_TRANSLATION_L2: + return "Synchronous external abort on translation table walk level 2"; + case DFSR_SOURCE_SYNC_PARITY_TRANSLATION_L1: + return "Synchronous parity error on translation table walk level 1"; + case DFSR_SOURCE_SYNC_PARITY_TRANSLATION_L2: + return "Synchronous parity error on translation table walk level 2"; + case DFSR_SOURCE_ACCESS_FLAG_L1: + return "Access flag fault L1"; + case DFSR_SOURCE_ACCESS_FLAG_L2: + return "Access flag fault L2"; + case DFSR_SOURCE_DOMAIN_L1: + return "Domain fault L1"; + case DFSR_SOURCE_DOMAIN_L2: + return "Domain flault L2"; + case DFSR_SOURCE_DEBUG: + return "Debug event"; + case DFSR_SOURCE_SYNC_EXTERNAL: + return "Synchronous external abort"; + case DFSR_SOURCE_TLB_CONFLICT: + return "TLB conflict abort"; + case DFSR_SOURCE_LOCKDOWN: + return "Lockdown (Implementation defined)"; + case DFSR_SOURCE_COPROCESSOR: + return "Coprocessor abort (Implementation defined)"; + case DFSR_SOURCE_SYNC_PARITY: + return "Synchronous parity error on memory access"; + case DFSR_SOURCE_ASYNC_EXTERNAL: + return "Asynchronous external abort"; + case DFSR_SOURCE_ASYNC_PARITY: + return "Asynchronous parity error on memory access"; + case DFSR_SOURCE_MASK: + break; + } + return "Unknown data abort"; +} + + +/** Returns value stored in comnbined/data fault status register. * * @return Value stored in CP15 fault status register (FSR). - */ -static inline fault_status_t read_fault_status_register(void) -{ - fault_status_union_t fsu; + * + * "VMSAv6 added a fifth fault status bit (bit[10]) to both the IFSR and DFSR. + * It is IMPLEMENTATION DEFINED how this bit is encoded in earlier versions of + * the architecture. A write flag (bit[11] of the DFSR) has also been + * introduced." + * ARM Architecture Reference Manual version i ch. B4.6 (PDF p. 719) + * + * See ch. B4.9.6 for location of data/instruction FSR. + * + */ +static inline fault_status_t read_data_fault_status_register(void) +{ + fault_status_t fsu; - /* fault status is stored in CP15 register 5 */ + /* Combined/Data fault status is stored in CP15 register 5, c0. */ asm volatile ( "mrc p15, 0, %[dummy], c5, c0, 0" - : [dummy] "=r" (fsu.dummy) + : [dummy] "=r" (fsu.raw) ); - return fsu.fs; -} - -/** Returns FAR (fault address register) content. - * - * @return FAR (fault address register) content (address that caused a page + return fsu; +} + +/** Returns DFAR (fault address register) content. + * + * This register is equivalent to FAR on pre armv6 machines. + * + * @return DFAR (fault address register) content (address that caused a page * fault) */ -static inline uintptr_t read_fault_address_register(void) +static inline uintptr_t read_data_fault_address_register(void) { uintptr_t ret; @@ -77,4 +174,5 @@ } +#if defined(PROCESSOR_armv4) | defined(PROCESSOR_armv5) /** Decides whether read or write into memory is requested. * @@ -97,5 +195,5 @@ panic("page_fault - instruction does not access memory " "(instr_code: %#0" PRIx32 ", badvaddr:%p).", - instr_union.pc, (void *) badvaddr); + *(uint32_t*)instr_union.instr, (void *) badvaddr); return PF_ACCESS_EXEC; } @@ -136,4 +234,5 @@ inst, (void *) badvaddr); } +#endif /** Handles "data abort" exception (load or store at invalid address). @@ -145,11 +244,50 @@ void data_abort(unsigned int exc_no, istate_t *istate) { - fault_status_t fsr __attribute__ ((unused)) = - read_fault_status_register(); - uintptr_t badvaddr = read_fault_address_register(); - - pf_access_t access = get_memory_access_type(istate->pc, badvaddr); - - int ret = as_page_fault(badvaddr, access, istate); + const uintptr_t badvaddr = read_data_fault_address_register(); + const fault_status_t fsr = read_data_fault_status_register(); + const dfsr_source_t source = fsr.raw & DFSR_SOURCE_MASK; + + switch (source) { + case DFSR_SOURCE_TRANSLATION_L1: + case DFSR_SOURCE_TRANSLATION_L2: + case DFSR_SOURCE_PERMISSION_L1: + case DFSR_SOURCE_PERMISSION_L2: + /* Page fault is handled further down */ + break; + case DFSR_SOURCE_ALIGN: + case DFSR_SOURCE_CACHE_MAINTENANCE: + case DFSR_SOURCE_SYNC_EXTERNAL_TRANSLATION_L1: + case DFSR_SOURCE_SYNC_EXTERNAL_TRANSLATION_L2: + case DFSR_SOURCE_SYNC_PARITY_TRANSLATION_L1: + case DFSR_SOURCE_SYNC_PARITY_TRANSLATION_L2: + case DFSR_SOURCE_ACCESS_FLAG_L1: + case DFSR_SOURCE_ACCESS_FLAG_L2: + case DFSR_SOURCE_DOMAIN_L1: + case DFSR_SOURCE_DOMAIN_L2: + case DFSR_SOURCE_DEBUG: + case DFSR_SOURCE_SYNC_EXTERNAL: + case DFSR_SOURCE_TLB_CONFLICT: + case DFSR_SOURCE_LOCKDOWN: + case DFSR_SOURCE_COPROCESSOR: + case DFSR_SOURCE_SYNC_PARITY: + case DFSR_SOURCE_ASYNC_EXTERNAL: + case DFSR_SOURCE_ASYNC_PARITY: + case DFSR_SOURCE_MASK: + /* Weird abort stuff */ + fault_if_from_uspace(istate, "Unhandled abort %s at address: " + "%#x.", dfsr_source_to_str(source), badvaddr); + panic("Unhandled abort %s at address: %#x.", + dfsr_source_to_str(source), badvaddr); + } + +#if defined(PROCESSOR_armv6) | defined(PROCESSOR_armv7_a) + const pf_access_t access = + fsr.data.wr ? PF_ACCESS_WRITE : PF_ACCESS_READ; +#elif defined(PROCESSOR_armv4) | defined(PROCESSOR_armv5) + const pf_access_t access = get_memory_access_type(istate->pc, badvaddr); +#else +#error "Unsupported architecture" +#endif + const int ret = as_page_fault(badvaddr, access, istate); if (ret == AS_PF_FAULT) { @@ -167,4 +305,5 @@ void prefetch_abort(unsigned int exc_no, istate_t *istate) { + /* NOTE: We should use IFAR and IFSR here. */ int ret = as_page_fault(istate->pc, PF_ACCESS_EXEC, istate); Index: kernel/genarch/Makefile.inc =================================================================== --- kernel/genarch/Makefile.inc (revision c4c2406caea2227486ba46e0c0ca00fff2b1fe13) +++ kernel/genarch/Makefile.inc (revision 71d09d6e1da31c7024293452978a24f0987dfd58) @@ -106,4 +106,9 @@ endif +ifeq ($(CONFIG_AMDM37X_UART),y) + GENARCH_SOURCES += \ + genarch/src/drivers/amdm37x_uart/amdm37x_uart.c +endif + ifeq ($(CONFIG_VIA_CUDA),y) GENARCH_SOURCES += \ Index: kernel/genarch/include/drivers/amdm37x_dispc/amdm37x_dispc.h =================================================================== --- kernel/genarch/include/drivers/amdm37x_dispc/amdm37x_dispc.h (revision 71d09d6e1da31c7024293452978a24f0987dfd58) +++ kernel/genarch/include/drivers/amdm37x_dispc/amdm37x_dispc.h (revision 71d09d6e1da31c7024293452978a24f0987dfd58) @@ -0,0 +1,394 @@ +/* + * Copyright (c) 2012 Jan Vesely + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * - Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * - Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * - The name of the author may not be used to endorse or promote products + * derived from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR + * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES + * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. + * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT + * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF + * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ +/** @addtogroup genarch + * @{ + */ +/** + * @file + * @brief Texas Instruments AM/DM37x SDRAM Memory Scheduler. + */ + +#ifndef KERN_AMDM37x_DISPC_H_ +#define KERN_AMDM37x_DISPC_H_ + +/* AMDM37x TRM p. 1813 */ +#define AMDM37x_DISPC_BASE_ADDRESS 0x48050400 +#define AMDM37x_DISPC_SIZE 1024 + +#define __paddname(line) PADD32_ ## line +#define _paddname(line) __paddname(line) +#define PADD32(count) uint32_t _paddname(__LINE__)[count] + +#include + +typedef struct { + const ioport32_t revision; +#define AMDM37X_DISPC_REVISION_MASK 0xff + + PADD32(3); + ioport32_t sysconfig; +#define AMDM37X_DISPC_SYSCONFIG_AUTOIDLE_FLAG (1 << 0) +#define AMDM37X_DISPC_SYSCONFIG_SOFTRESET_FLAG (1 << 1) +#define AMDM37X_DISPC_SYSCONFIG_ENWAKEUP_FLAG (1 << 2) +#define AMDM37X_DISPC_SYSCONFIG_SIDLEMODE_MASK 0x3 +#define AMDM37X_DISPC_SYSCONFIG_SIDLEMODE_SHIFT 3 +#define AMDM37X_DISPC_SYSCONFIG_CLOCKACTIVITY_MASK 0x3 +#define AMDM37X_DISPC_SYSCONFIG_CLOCKACTIVITY_SHIFT 8 +#define AMDM37X_DISPC_SYSCONFIG_MIDLEMODE_MASK 0x3 +#define AMDM37X_DISPC_SYSCONFIG_MIDLEMODE_SHIFT 12 + + const ioport32_t sysstatus; +#define AMDM37X_DISPC_SYSSTATUS_RESETDONE_FLAG (1 << 0) + + ioport32_t irqstatus; + ioport32_t irqenable; +#define AMDM37X_DISPC_IRQ_FRAMEDONE_FLAG (1 << 0) +#define AMDM37X_DISPC_IRQ_VSYNC_FLAG (1 << 1) +#define AMDM37X_DISPC_IRQ_EVSYNCEVEN_FLAG (1 << 2) +#define AMDM37X_DISPC_IRQ_EVSYNCODD_FLAG (1 << 3) +#define AMDM37X_DISPC_IRQ_ACBIASCOUNTSTATUS_FLAG (1 << 4) +#define AMDM37X_DISPC_IRQ_PROGRAMMEDLINENUMBER_FLAG (1 << 5) +#define AMDM37X_DISPC_IRQ_GFXFIFOUNDERFLOW_FLAG (1 << 6) +#define AMDM37X_DISPC_IRQ_GFXENDWINDOW_FLAG (1 << 7) +#define AMDM37X_DISPC_IRQ_PALETTEGAMMALOADING_FLAG (1 << 8) +#define AMDM37X_DISPC_IRQ_OPCERROR_FLAG (1 << 9) +#define AMDM37X_DISPC_IRQ_VID1FIFOUNDERFLOW_FLAG (1 << 10) +#define AMDM37X_DISPC_IRQ_VID1ENDWINDOW_FLAG (1 << 11) +#define AMDM37X_DISPC_IRQ_VID2FIFOUNDERFLOW_FLAG (1 << 12) +#define AMDM37X_DISPC_IRQ_VID2ENDWINDOW_FLAG (1 << 13) +#define AMDM37X_DISPC_IRQ_SYNCLOST_FLAG (1 << 14) +#define AMDM37X_DISPC_IRQ_SYNCLOSTDIGITAL_FLAG (1 << 15) +#define AMDM37X_DISPC_IRQ_WAKEUP_FLAG (1 << 16) + + PADD32(8); + ioport32_t control; +#define AMDM37X_DISPC_CONTROL_LCD_ENABLE_FLAG (1 << 0) +#define AMDM37X_DISPC_CONTROL_DIGITAL_ENABLE_FLAG (1 << 1) +#define AMDM37X_DISPC_CONTROL_MONOCOLOR_FLAG (1 << 2) +#define AMDM37X_DISPC_CONTROL_STNTFT_FLAG (1 << 3) +#define AMDM37X_DISPC_CONTROL_M8B_FLAG (1 << 4) +#define AMDM37X_DISPC_CONTROL_GOLCD_FLAG (1 << 5) +#define AMDM37X_DISPC_CONTROL_GODIGITAL_FLAG (1 << 6) +#define AMDM37X_DISPC_CONTROL_STDITHERENABLE_FLAG (1 << 7) +#define AMDM37X_DISPC_CONTROL_TFTDATALINES_MASK 0x3 +#define AMDM37X_DISPC_CONTROL_TFTDATALINES_SHIFT 8 +#define AMDM37X_DISPC_CONTROL_TFTDATALINES_12B 0 +#define AMDM37X_DISPC_CONTROL_TFTDATALINES_16B 1 +#define AMDM37X_DISPC_CONTROL_TFTDATALINES_18B 2 +#define AMDM37X_DISPC_CONTROL_TFTDATALINES_24B 3 +#define AMDM37X_DISPC_CONTROL_STALLMODE_FLAG (1 << 11) +#define AMDM37X_DISPC_CONTROL_OVERLAYOPTIMIZATION_FLAG (1 << 12) +#define AMDM37X_DISPC_CONTROL_GPIN0_FLAG (1 << 13) +#define AMDM37X_DISPC_CONTROL_GPIN1_FLAG (1 << 14) +#define AMDM37X_DISPC_CONTROL_GPOUT0_FLAG (1 << 15) +#define AMDM37X_DISPC_CONTROL_GPOUT1_FLAG (1 << 16) +#define AMDM37X_DISPC_CONTROL_HT_MASK 0x7 +#define AMDM37X_DISPC_CONTROL_HT_SHIFT 17 +#define AMDM37X_DISPC_CONTROL_TDMENABLE_FLAG (1 << 20) +#define AMDM37X_DISPC_CONTROL_TDMPARALLELMODE_MASK 0x3 +#define AMDM37X_DISPC_CONTROL_TDMPARELLELMODE_SHIFT 21 +#define AMDM37X_DISPC_CONTROL_TDMCYCLEFORMAT_MASK 0x3 +#define AMDM37X_DISPC_CONTROL_TDMCYCLEFORMAT_SHIFT 23 +#define AMDM37X_DISPC_CONTROL_TDMUNUSEDBITS_MASK 0x3 +#define AMDM37X_DISPC_CONTROL_TDMUNUSEDBITS_SHIFT 25 +#define AMDM37X_DISPC_CONTROL_PCKFREEENABLE_FLAG (1 << 27) +#define AMDM37X_DISPC_CONTROL_LCDENABLESIGNAL_FLAG (1 << 28) +#define AMDM37X_DISPC_CONTROL_KCDENABLEPOL_FLAG (1 << 29) +#define AMDM37X_DISPC_CONTROL_SPATIALTEMPORALDITHERINGFRAMES_MASK 0x3 +#define AMDM37X_DISPC_CONTROL_SPATIALTEMPORALDITHERINGFRAMES_SHIFT 30 + + ioport32_t config; +#define AMDM37X_DISPC_CONFIG_PIXELGATED_FLAG (1 << 0) +#define AMDM37X_DISPC_CONFIG_LOADMODE_MASK 0x3 +#define AMDM37X_DISPC_CONFIG_LOADMODE_SHIFT 1 +#define AMDM37X_DISPC_CONFIG_LOADMODE_PGDATAEVERYFRAME 0x0 +#define AMDM37X_DISPC_CONFIG_LOADMODE_PGUSER 0x1 +#define AMDM37X_DISPC_CONFIG_LOADMODE_DATAEVERYFRAME 0x2 +#define AMDM37X_DISPC_CONFIG_LOADMODE_PGDFIRSTFRAME 0x3 +#define AMDM37X_DISPC_CONFIG_PALETTEGAMMATABLE_FLAG (1 << 3) +#define AMDM37X_DISPC_CONFIG_PIXELDATAGATED_FLAG (1 << 4) +#define AMDM37X_DISPC_CONFIG_PIXELCLOCKGATED_FLAG (1 << 5) +#define AMDM37X_DISPC_CONFIG_HSYNCGATED_FLAG (1 << 6) +#define AMDM37X_DISPC_CONFIG_VSYNCGATED_FLAG (1 << 7) +#define AMDM37X_DISPC_CONFIG_ACBIASGATED_FLAG (1 << 8) +#define AMDM37X_DISPC_CONFIG_FUNCGATED_FLAG (1 << 9) +#define AMDM37X_DISPC_CONFIG_TCKLCDENABLE_FLAG (1 << 10) +#define AMDM37X_DISPC_CONFIG_TCKLCDSELECTION_FLAG (1 << 11) +#define AMDM37X_DISPC_CONFIG_TCKDIGENABLE_FLAG (1 << 12) +#define AMDM37X_DISPC_CONFIG_TCKDIGSELECTION_FLAG (1 << 13) +#define AMDM37X_DISPC_CONFIG_FIFOMERGE_FLAG (1 << 14) +#define AMDM37X_DISPC_CONFIG_CPR_FLAG (1 << 15) +#define AMDM37X_DISPC_CONFIG_FIFOHANDCHECK_FLAG (1 << 16) +#define AMDM37X_DISPC_CONFIG_FIFOFILLING_FLAG (1 << 17) +#define AMDM37X_DISPC_CONFIG_LCDPALPHABLENDERENABLDE_FLAG (1 << 18) +#define AMDM37X_DISPC_CONFIG_TVALPHABLENDERENABLE_FLAG (1 << 19) + + PADD32(1); + ioport32_t default_color[2]; + ioport32_t trans_color[2]; +#define AMDM37X_DISPC_COLOR_MASK 0xffffff + + const ioport32_t line_status; + ioport32_t line_number; +#define AMDM37X_DISPC_LINE_NUMBER_MASK 0x3ff + + ioport32_t timing_h; +#define AMDM37X_DISPC_TIMING_H_HSW_MASK 0xff +#define AMDM37X_DISPC_TIMING_H_HSW_SHIFT 0 +#define AMDM37X_DISPC_TIMING_H_HFP_MASK 0xfff +#define AMDM37X_DISPC_TIMING_H_HFP_SHIFT 8 +#define AMDM37X_DISPC_TIMING_H_HBP_MASK 0xfff +#define AMDM37X_DISPC_TIMING_H_HBP_SHIFT 20 + + ioport32_t timing_v; +#define AMDM37X_DISPC_TIMING_V_VSW_MASK 0xff +#define AMDM37X_DISPC_TIMING_V_VSW_SHIFT 0 +#define AMDM37X_DISPC_TIMING_V_VFP_MASK 0xfff +#define AMDM37X_DISPC_TIMING_V_VFP_SHIFT 8 +#define AMDM37X_DISPC_TIMING_V_VBP_MASK 0xfff +#define AMDM37X_DISPC_TIMING_V_VBP_SHIFT 20 + + ioport32_t pol_freq; +#define AMDM37X_DISPC_POL_FREQ_ACB_MASK 0xff +#define AMDM37X_DISPC_POL_FREQ_ACB_SHIFT 0 +#define AMDM37X_DISPC_POL_FREQ_ACBI_MASK 0xf +#define AMDM37X_DISPC_POL_FREQ_ACBI_SHIFT 8 +#define AMDM37X_DISPC_POL_FREQ_IVS_FLAG (1 << 12) +#define AMDM37X_DISPC_POL_FREQ_IHS_FLAG (1 << 13) +#define AMDM37X_DISPC_POL_FREQ_IPC_FLAG (1 << 14) +#define AMDM37X_DISPC_POL_FREQ_IEO_FLAG (1 << 15) +#define AMDM37X_DISPC_POL_FREQ_RF_FLAG (1 << 16) +#define AMDM37X_DISPC_POL_FREQ_ONOFF_FLAG (1 << 17) + + ioport32_t divisor; +#define AMDM37X_DISPC_DIVISOR_PCD_MASK 0xff +#define AMDM37X_DISPC_DIVISOR_PCD_SHIFT 0 +#define AMDM37X_DISPC_DIVISOR_LCD_MASK 0xff +#define AMDM37X_DISPC_DIVISOR_LCD_SHIFT 16 + + ioport32_t global_alpha; +#define AMDM37X_DISPC_GLOBAL_ALPHA_GFXGLOBALALPHA_MASK 0xff +#define AMDM37X_DISPC_GLOBAL_ALPHA_GFXGLOBALALPHA_SHIFT 0 +#define AMDM37X_DISPC_GLOBAL_ALPHA_VID2GLOBALALPHA_MASK 0xff +#define AMDM37X_DISPC_GLOBAL_ALPHA_VID2GLOBALALPHA_SHIFT 16 + + ioport32_t size_dig; + ioport32_t size_lcd; + + struct { + ioport32_t ba[2]; + ioport32_t position; +#define AMDM37X_DISPC_GFX_POSITION_GFXPOSX_MASK 0x7ff +#define AMDM37X_DISPC_GFX_POSITION_GFXPOSX_SHIFT 0 +#define AMDM37X_DISPC_GFX_POSITION_GFXPOSY_MASK 0x7ff +#define AMDM37X_DISPC_GFX_POSITION_GFXPOSY_SHIFT 16 + + ioport32_t size; +#define AMDM37X_DISPC_SIZE_WIDTH_MASK 0x7ff +#define AMDM37X_DISPC_SIZE_WIDTH_SHIFT 0 +#define AMDM37X_DISPC_SIZE_HEIGHT_MASK 0x7ff +#define AMDM37X_DISPC_SIZE_HEIGHT_SHIFT 16 + + PADD32(4); + ioport32_t attributes; +#define AMDM37X_DISPC_GFX_ATTRIBUTES_ENABLE_FLAG (1 << 0) +#define AMDM37X_DISPC_GFX_ATTRIBUTES_FORMAT_MASK 0xf +#define AMDM37X_DISPC_GFX_ATTRIBUTES_FORMAT_SHIFT 1 +#define AMDM37X_DISPC_GFX_ATTRIBUTES_FORMAT_ARGB16 0x5 +#define AMDM37X_DISPC_GFX_ATTRIBUTES_FORMAT_RGB16 0x6 +#define AMDM37X_DISPC_GFX_ATTRIBUTES_FORMAT_RGB24_32 0x8 +#define AMDM37X_DISPC_GFX_ATTRIBUTES_FORMAT_RGB24 0x9 +#define AMDM37X_DISPC_GFX_ATTRIBUTES_FORMAT_ARGB 0xc +#define AMDM37X_DISPC_GFX_ATTRIBUTES_FORMAT_RGBA 0xd +#define AMDM37X_DISPC_GFX_ATTRIBUTES_FORMAT_RGBX 0xe +#define AMDM37X_DISPC_GFX_ATTRIBUTES_REPLICATIONENABLE_FLAG (1 << 5) +#define AMDM37X_DISPC_GFX_ATTRIBUTES_GFXBURSTSIZE_MASK 0x3 +#define AMDM37X_DISPC_GFX_ATTRIBUTES_GFXBURSTSIZE_SHIFT 6 +#define AMDM37X_DISPC_GFX_ATTRIBUTES_GFXCHANNELOUT_FLAG (1 << 8) +#define AMDM37X_DISPC_GFX_ATTRIBUTES_GFXNIBBLEMODE_FLAG (1 << 9) +#define AMDM37X_DISPC_GFX_ATTRIBUTES_GFXENDIANNES_FLAG (1 << 10) +#define AMDM37X_DISPC_GFX_ATTRIBUTES_GFXFIFOPRELOAD_FLAG (1 << 11) +#define AMDM37X_DISPC_GFX_ATTRIBUTES_GFXROTATION_MASK 0x3 +#define AMDM37X_DISPC_GFX_ATTRIBUTES_GFXROTATION_SHIFT 12 +#define AMDM37X_DISPC_GFX_ATTRIBUTES_GFXARBITRATION_FLAG (1 << 14) +#define AMDM37X_DISPC_GFX_ATTRIBUTES_GFXSELFREFRESH_FLAG (1 << 15) +#define AMDM37X_DISPC_GFX_ATTRIBUTES_PREMULTIALPHA_FLAG (1 << 28) + + + ioport32_t fifo_threshold; + const ioport32_t fifo_size_status; + ioport32_t row_inc; + ioport32_t pixel_inc; + ioport32_t window_skip; + ioport32_t table_ba; + } gfx; + + struct { + ioport32_t ba[2]; + ioport32_t position; + ioport32_t size; + ioport32_t attributes; + ioport32_t fifo_threshold; + const ioport32_t fifo_size_status; + ioport32_t row_inc; + ioport32_t pixel_inc; + ioport32_t fir; + ioport32_t picture_size; + ioport32_t accui[2]; + struct { + ioport32_t hi; + ioport32_t hvi; + } fir_coef[8]; + ioport32_t conv_coef[5]; + PADD32(2); + } vid[2]; + /* 0x1d4 */ + ioport32_t data_cycle[3]; + /* 0x1e0 */ + ioport32_t vid_fir_coef_v[8]; + /* 0x200 */ + PADD32(8); + /* 0x220 */ + ioport32_t cpr_coef_r; + ioport32_t cpr_coef_g; + ioport32_t cpr_coef_b; + ioport32_t gfx_preload; + + /* 0x230 */ + ioport32_t vid_preload[2]; + +} __attribute__((packed)) amdm37x_dispc_regs_t; + + +static inline void amdm37x_dispc_setup_fb(amdm37x_dispc_regs_t *regs, + unsigned x, unsigned y, unsigned bpp, uintptr_t pa) +{ + ASSERT(regs); + /* Init sequence for dispc is in chapter 7.6.5.1.4 p. 1810, + * no idea what parts of that work. */ + + /* Disable all interrupts */ + regs->irqenable = 0; + + /* Pixel format specifics*/ + uint32_t attrib_pixel_format = 0; + uint32_t control_data_lanes = 0; + switch (bpp) + { + case 32: + attrib_pixel_format = AMDM37X_DISPC_GFX_ATTRIBUTES_FORMAT_RGBX; + control_data_lanes = AMDM37X_DISPC_CONTROL_TFTDATALINES_24B; + break; + case 24: + attrib_pixel_format = AMDM37X_DISPC_GFX_ATTRIBUTES_FORMAT_RGB24; + control_data_lanes = AMDM37X_DISPC_CONTROL_TFTDATALINES_24B; + break; + case 16: + attrib_pixel_format = AMDM37X_DISPC_GFX_ATTRIBUTES_FORMAT_RGB16; + control_data_lanes = AMDM37X_DISPC_CONTROL_TFTDATALINES_16B; + break; + default: + ASSERT(false); + } + + /* Prepare sizes */ + const uint32_t size_reg = + (((x - 1) & AMDM37X_DISPC_SIZE_WIDTH_MASK) + << AMDM37X_DISPC_SIZE_WIDTH_SHIFT) | + (((y - 1) & AMDM37X_DISPC_SIZE_HEIGHT_MASK) + << AMDM37X_DISPC_SIZE_HEIGHT_SHIFT); + + /* modes taken from u-boot, for 1024x768 */ + // TODO replace magic values with actual correct values +// regs->timing_h = 0x1a4024c9; +// regs->timing_v = 0x02c00509; +// regs->pol_freq = 0x00007028; +// regs->divisor = 0x00010001; + + /* setup output */ + regs->size_lcd = size_reg; + regs->size_dig = size_reg; + + /* Nice blue default color */ + regs->default_color[0] = 0x0000ff; + regs->default_color[1] = 0x0000ff; + + /* Setup control register */ + uint32_t control = 0 | + AMDM37X_DISPC_CONTROL_PCKFREEENABLE_FLAG | + (control_data_lanes << AMDM37X_DISPC_CONTROL_TFTDATALINES_SHIFT) | + AMDM37X_DISPC_CONTROL_GPOUT0_FLAG | + AMDM37X_DISPC_CONTROL_GPOUT1_FLAG; + regs->control = control; + + /* No gamma stuff only data */ + uint32_t config = (AMDM37X_DISPC_CONFIG_LOADMODE_DATAEVERYFRAME + << AMDM37X_DISPC_CONFIG_LOADMODE_SHIFT); + regs->config = config; + + + /* Set framebuffer base address */ + regs->gfx.ba[0] = pa; + regs->gfx.ba[1] = pa; + regs->gfx.position = 0; + + /* Setup fb size */ + regs->gfx.size = size_reg; + + /* Set pixel format */ + uint32_t attribs = 0 | + (attrib_pixel_format << AMDM37X_DISPC_GFX_ATTRIBUTES_FORMAT_SHIFT); + regs->gfx.attributes = attribs; + + /* 0x03ff03c0 is the default */ + regs->gfx.fifo_threshold = 0x03ff03c0; + /* This value should be stride - width, 1 means next pixel i.e. + * stride == width */ + regs->gfx.row_inc = 1; + /* number of bytes to next pixel in BPP multiples */ + regs->gfx.pixel_inc = 1; + /* only used if video is played over fb */ + regs->gfx.window_skip = 0; + /* Gamma and palette table */ + regs->gfx.table_ba = 0; + + /* enable frame buffer graphics */ + regs->gfx.attributes |= AMDM37X_DISPC_GFX_ATTRIBUTES_ENABLE_FLAG; + /* Update register values */ + regs->control |= AMDM37X_DISPC_CONTROL_GOLCD_FLAG; + regs->control |= AMDM37X_DISPC_CONTROL_GODIGITAL_FLAG; + /* Enable output */ + regs->control |= AMDM37X_DISPC_CONTROL_LCD_ENABLE_FLAG; + regs->control |= AMDM37X_DISPC_CONTROL_DIGITAL_ENABLE_FLAG; +} + + +#endif +/** + * @} + */ Index: kernel/genarch/include/drivers/amdm37x_gpt/amdm37x_gpt.h =================================================================== --- kernel/genarch/include/drivers/amdm37x_gpt/amdm37x_gpt.h (revision 71d09d6e1da31c7024293452978a24f0987dfd58) +++ kernel/genarch/include/drivers/amdm37x_gpt/amdm37x_gpt.h (revision 71d09d6e1da31c7024293452978a24f0987dfd58) @@ -0,0 +1,255 @@ +/* + * Copyright (c) 2012 Jan Vesely + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * - Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * - Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * - The name of the author may not be used to endorse or promote products + * derived from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR + * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES + * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. + * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT + * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF + * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ +/** @addtogroup genarch + * @{ + */ +/** + * @file + * @brief Texas Instruments AM/DM37x MPU general purpose timer driver. + */ + +#ifndef KERN_AMDM37x_GPT_H_ +#define KERN_AMDM37x_GPT_H_ + +#include +#include + +/* AMDM37x TRM p. 2740 */ +#define AMDM37x_GPT1_BASE_ADDRESS 0x48318000 +#define AMDM37x_GPT1_SIZE 4096 +#define AMDM37x_GPT1_IRQ 37 +#define AMDM37x_GPT2_BASE_ADDRESS 0x49032000 +#define AMDM37x_GPT2_SIZE 4096 +#define AMDM37x_GPT2_IRQ 38 +#define AMDM37x_GPT3_BASE_ADDRESS 0x49034000 +#define AMDM37x_GPT3_SIZE 4096 +#define AMDM37x_GPT3_IRQ 39 +#define AMDM37x_GPT4_BASE_ADDRESS 0x49036000 +#define AMDM37x_GPT4_SIZE 4096 +#define AMDM37x_GPT4_IRQ 40 +#define AMDM37x_GPT5_BASE_ADDRESS 0x49038000 +#define AMDM37x_GPT5_SIZE 4096 +#define AMDM37x_GPT5_IRQ 41 +#define AMDM37x_GPT6_BASE_ADDRESS 0x4903a000 +#define AMDM37x_GPT6_SIZE 4096 +#define AMDM37x_GPT6_IRQ 42 +#define AMDM37x_GPT7_BASE_ADDRESS 0x4903c000 +#define AMDM37x_GPT7_SIZE 4096 +#define AMDM37x_GPT7_IRQ 43 +#define AMDM37x_GPT8_BASE_ADDRESS 0x4903e000 +#define AMDM37x_GPT8_SIZE 4096 +#define AMDM37x_GPT8_IRQ 44 +#define AMDM37x_GPT9_BASE_ADDRESS 0x49040000 +#define AMDM37x_GPT9_SIZE 4096 +#define AMDM37x_GPT9_IRQ 45 +#define AMDM37x_GPT10_BASE_ADDRESS 0x48086000 +#define AMDM37x_GPT10_SIZE 4096 +#define AMDM37x_GPT10_IRQ 46 +#define AMDM37x_GPT11_BASE_ADDRESS 0x48088000 +#define AMDM37x_GPT11_SIZE 4096 +#define AMDM37x_GPT11_IRQ 47 + + +/** GPT register map AMDM37x TRM p. 2740 */ +typedef struct { + /** IP revision */ + const ioport32_t tidr; +#define AMDM37x_GPT_TIDR_MINOR_MASK (0xf) +#define AMDM37x_GPT_TIDR_MINOR_SHIFT (0) +#define AMDM37x_GPT_TIDR_MAJOR_MASK (0xf) +#define AMDM37x_GPT_TIDR_MAJOR_SHIFT (4) + uint32_t padd0_[3]; + + /** L4 Interface parameters */ + ioport32_t tiocp_cfg; +#define AMDM37x_GPT_TIOCP_CFG_AUTOIDLE_FLAG (1 << 0) +#define AMDM37x_GPT_TIOCP_CFG_SOFTRESET_FLAG (1 << 1) +#define AMDM37x_GPT_TIOCP_CFG_ENWAKEUP_FLAG (1 << 2) +#define AMDM37x_GPT_TIOCP_CFG_IDLEMODE_MASK (0x3) +#define AMDM37x_GPT_TIOCP_CFG_IDLEMODE_SHIFT (3) +#define AMDM37x_GPT_TIOCP_CFG_EMUFREE_FlAG (1 << 5) +#define AMDM37x_GPT_TIOCP_CFG_CLOCKACTIVITY_MASK (0x3) +#define AMDM37x_GPT_TIOCP_CFG_CLOCKACTIVITY_SHIFT (8) + + /** Module status information, excluding irq */ + const ioport32_t tistat; +#define AMDM37x_GPT_TISTAT_RESET_DONE_FLAG (1 << 0) + + /** Interrupt status register */ + ioport32_t tisr; +#define AMDM37x_GPT_TISR_MAT_IRQ_FLAG (1 << 0) +#define AMDM37x_GPT_TISR_OVF_IRQ_FLAG (1 << 1) +#define AMDM37x_GPT_TISR_TCAR_IRQ_FLAG (1 << 2) + + /* Interrupt enable register */ + ioport32_t tier; +#define AMDM37x_GPT_TIER_MAT_IRQ_FLAG (1 << 0) +#define AMDM37x_GPT_TIER_OVF_IRQ_FLAG (1 << 1) +#define AMDM37x_GPT_TIER_TCAR_IRQ_FLAG (1 << 2) + + /** Wakeup enable register */ + ioport32_t twer; +#define AMDM37x_GPT_TWER_MAT_IRQ_FLAG (1 << 0) +#define AMDM37x_GPT_TWER_OVF_IRQ_FLAG (1 << 1) +#define AMDM37x_GPT_TWER_TCAR_IRQ_FLAG (1 << 2) + + /** Optional features control register */ + ioport32_t tclr; +#define AMDM37x_GPT_TCLR_ST_FLAG (1 << 0) +#define AMDM37x_GPT_TCLR_AR_FLAG (1 << 1) +#define AMDM37x_GPT_TCLR_PTV_MASK (0x7) +#define AMDM37x_GPT_TCLR_PTV_SHIFT (2) +#define AMDM37x_GPT_TCLR_PRE_FLAG (1 << 5) +#define AMDM37x_GPT_TCLR_CE_FLAG (1 << 6) +#define AMDM37x_GPT_TCLR_SCPWM (1 << 7) +#define AMDM37x_GPT_TCLR_TCM_MASK (0x3) +#define AMDM37x_GPT_TCLR_TCM_SHIFT (8) +#define AMDM37x_GPT_TCLR_TRG_MASK (0x3) +#define AMDM37x_GPT_TCLR_TRG_SHIFT (10) +#define AMDM37x_GPT_TCLR_PT_FLAG (1 << 12) +#define AMDM37x_GPT_TCLR_CAPT_MODE_FLAG (1 << 13) +#define AMDM37x_GPT_TCLR_GPO_CFG_FLAG (1 << 14) + + /** Value of timer counter */ + ioport32_t tccr; + + /** Timer load register */ + ioport32_t tldr; + + /** Timer trigger register */ + ioport32_t ttgr; + + /** Write-posted pending register */ + const ioport32_t twps; +#define AMDM37x_GPT_TWPS_TCLR_FLAG (1 << 0) +#define AMDM37x_GPT_TWPS_TCRR_FLAG (1 << 1) +#define AMDM37x_GPT_TWPS_TLDR_FLAG (1 << 2) +#define AMDM37x_GPT_TWPS_TTGR_FLAG (1 << 3) +#define AMDM37x_GPT_TWPS_TMAR_FLAG (1 << 4) +#define AMDM37x_GPT_TWPS_TPIR_FLAG (1 << 5) +#define AMDM37x_GPT_TWPS_TNIR_FLAG (1 << 6) +#define AMDM37x_GPT_TWPS_TCVR_FLAG (1 << 7) +#define AMDM37x_GPT_TWPS_TOCR_FLAG (1 << 8) +#define AMDM37x_GPT_TWPS_TOWR_FLAG (1 << 9) + + /** Timer match register */ + ioport32_t tmar; + + /** Capture value 1 register */ + const ioport32_t tcar1; + + /** Software interface control register */ + ioport32_t tsicr; +#define AMDM37x_GPT_TSICR_SFT_FLAG (1 << 1) +#define AMDM37x_GPT_TSICR_POSTED_FLAG (1 << 2) + + /** Capture value 2 register */ + const ioport32_t tcar2; + + /* GPT1,2,10 only (used for 1ms time period generation)*/ + + /** Positive increment register */ + ioport32_t tpir; + + /** Negative increment register */ + ioport32_t tnir; + + /** Counter value register */ + ioport32_t tcvr; + + /** Mask the tick interrupt for selected number of ticks */ + ioport32_t tocr; + + /** Number of masked overflow interrupts */ + ioport32_t towr; +} amdm37x_gpt_regs_t; + +typedef struct { + amdm37x_gpt_regs_t *regs; + bool special_available; +} amdm37x_gpt_t; + +static inline void amdm37x_gpt_timer_ticks_init( + amdm37x_gpt_t* timer, uintptr_t ioregs, size_t iosize, unsigned hz) +{ + /* Set 32768 Hz clock as source */ + // TODO find a nicer way to setup 32kHz clock source for timer1 + // reg 0x48004C40 is CM_CLKSEL_WKUP see page 485 of the manual + ioport32_t *clksel = (void*) km_map(0x48004C40, 4, PAGE_NOT_CACHEABLE); + *clksel &= ~1; + km_unmap((uintptr_t)clksel, 4); + + ASSERT(timer); + /* Map control register */ + timer->regs = (void*) km_map(ioregs, iosize, PAGE_NOT_CACHEABLE); + + /* Set autoreload */ + timer->regs->tclr = AMDM37x_GPT_TCLR_AR_FLAG; + + timer->special_available = ( + (ioregs == AMDM37x_GPT1_BASE_ADDRESS) || + (ioregs == AMDM37x_GPT2_BASE_ADDRESS) || + (ioregs == AMDM37x_GPT10_BASE_ADDRESS)); + timer->regs->tldr = 0xffffffff - (32768 / hz) + 1; + timer->regs->tccr = 0xffffffff - (32768 / hz) + 1; + if (timer->special_available) { + /* Set values for according to formula (manual p. 2733) */ + /* Use temporary variables for easier debugging */ + const uint32_t tpir = + ((32768 / hz + 1) * 1000000) - (32768000L * (1000 / hz)); + const uint32_t tnir = + ((32768 / hz) * 1000000) - (32768000 * (1000 / hz)); + timer->regs->tpir = tpir; + timer->regs->tnir = tnir; + } + +} + +static inline void amdm37x_gpt_timer_ticks_start(amdm37x_gpt_t* timer) +{ + ASSERT(timer); + ASSERT(timer->regs); + /* Enable overflow interrupt */ + timer->regs->tier |= AMDM37x_GPT_TIER_OVF_IRQ_FLAG; + /* Start timer */ + timer->regs->tclr |= AMDM37x_GPT_TCLR_ST_FLAG; +} + +static inline void amdm37x_gpt_irq_ack(amdm37x_gpt_t* timer) +{ + ASSERT(timer); + ASSERT(timer->regs); + /* Clear all pending interrupts */ + timer->regs->tisr = timer->regs->tisr; +} + +#endif + +/** + * @} + */ Index: kernel/genarch/include/drivers/amdm37x_irc/amdm37x_irc.h =================================================================== --- kernel/genarch/include/drivers/amdm37x_irc/amdm37x_irc.h (revision 71d09d6e1da31c7024293452978a24f0987dfd58) +++ kernel/genarch/include/drivers/amdm37x_irc/amdm37x_irc.h (revision 71d09d6e1da31c7024293452978a24f0987dfd58) @@ -0,0 +1,206 @@ +/* + * Copyright (c) 2012 Jan Vesely + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * - Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * - Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * - The name of the author may not be used to endorse or promote products + * derived from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR + * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES + * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. + * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT + * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF + * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ +/** @addtogroup genarch + * @{ + */ +/** + * @file + * @brief Texas Instruments AM/DM37x MPU on-chip interrupt controller driver. + */ + +#ifndef KERN_AMDM37x_IRQC_H_ +#define KERN_AMDM37x_IRQC_H_ + +/* AMDM37x TRM p. 1079 */ +#define AMDM37x_IRC_BASE_ADDRESS 0x48200000 +#define AMDM37x_IRC_SIZE 4096 + +#define AMDM37x_IRC_IRQ_COUNT 96 + +#include + +typedef struct { + const ioport32_t revision; /**< Revision */ +#define AMDM37x_IRC_REV_MASK (0xff) + + uint8_t padd0_[12]; + + ioport32_t sysconfig; /**< SYS config */ +#define AMDM37x_IRC_SYSCONFIG_AUTOIDLE_FLAG (1 << 0) +#define AMDM37x_IRC_SYSCONFIG_SOFTRESET_FLAG (1 << 1) + + const ioport32_t sysstatus; /**< SYS status */ +#define AMDM37x_IRC_SYSSTATUS_RESET_DONE_FLAG (1 << 0) + + uint8_t padd1_[40]; + + const ioport32_t sir_irq; /**< Currently active irq number */ +#define AMDM37x_IRC_SIR_IRQ_ACTIVEIRQ_MASK (0x7f) +#define AMDM37x_IRC_SIR_IRQ_SPURIOUSIRQFLAG_MASK (0xfffffff8) + + const ioport32_t sir_fiq; +#define AMDM37x_IRC_SIR_FIQ_ACTIVEIRQ_MASK (0x7f) +#define AMDM37x_IRC_SIR_FIQ_SPURIOUSIRQFLAG_MASK (0xfffffff8) + + ioport32_t control; /**< New interrupt agreement. */ +#define AMDM37x_IRC_CONTROL_NEWIRQAGR_FLAG (1 << 0) +#define AMDM37x_IRC_CONTROL_NEWFIQAGR_FLAG (1 << 1) + + ioport32_t protection; /**< Protect other registers. */ +#define AMDM37x_IRC_PROTECTION_PROETCTION_FLAG (1 << 0) + + ioport32_t idle; /**< Idle and autogating */ +#define AMDM37x_IRC_IDLE_FUNCIDLE_FLAG (1 << 0) +#define AMDM37x_IRC_IDLE_TURBO_FLAG (1 << 1) + + uint8_t padd2_[12]; + + ioport32_t irq_priority; /**< Active IRQ priority */ +#define AMDM37x_IRC_IRQ_PRIORITY_IRQPRIORITY_MASK (0x7f) +#define AMDM37x_IRC_IRQ_PRIORITY_SPURIOUSIRQFLAG_MASK (0xfffffff8) + + ioport32_t fiq_priority; /**< Active FIQ priority */ +#define AMDM37x_IRC_FIQ_PRIORITY_FIQPRIORITY_MASK (0x7f) +#define AMDM37x_IRC_FIQ_PRIORITY_SPURIOUSFIQFLAG_MASK (0xfffffff8) + + ioport32_t threshold; /**< Priority threshold */ +#define AMDM37x_IRC_THRESHOLD_PRIORITYTHRESHOLD_MASK (0xff) +#define AMDM37x_IRC_THRESHOLD_PRIORITYTHRESHOLD_ENABLED (0x00) +#define AMDM37x_IRC_THRESHOLD_PRIORITYTHRESHOLD_DISABLED (0xff) + + uint8_t padd3__[20]; + + struct { + const ioport32_t itr; /**< Interrupt input status before masking */ + ioport32_t mir; /**< Interrupt mask */ + ioport32_t mir_clear; /**< Clear mir mask bits */ + ioport32_t mir_set; /**< Set mir mask bits */ + ioport32_t isr_set; /**< Set software interrupt bits */ + ioport32_t isr_clear; /**< Clear software interrupt bits */ + const ioport32_t pending_irq; /**< IRQ status after masking */ + const ioport32_t pending_fiq; /**< FIQ status after masking */ + } interrupts[3]; + + uint8_t padd4_[32]; + + ioport32_t ilr[96]; /**< FIQ/IRQ steering */ +#define AMDM37x_IRC_ILR_FIQNIRQ (1 << 0) +#define AMDM37x_IRC_ILR_PRIORITY_MASK (0x3f) +#define AMDM37x_IRC_ILR_PRIORITY_SHIFT (2) + +} amdm37x_irc_regs_t; + +static inline void amdm37x_irc_dump(amdm37x_irc_regs_t *regs) +{ +#define DUMP_REG(name) \ + printf("%s %p(%x).\n", #name, ®s->name, regs->name); + + DUMP_REG(revision); + DUMP_REG(sysconfig); + DUMP_REG(sysstatus); + DUMP_REG(sir_irq); + DUMP_REG(sir_fiq); + DUMP_REG(control); + DUMP_REG(protection); + DUMP_REG(idle); + DUMP_REG(irq_priority); + DUMP_REG(fiq_priority); + DUMP_REG(threshold); + + for (int i = 0; i < 3; ++i) { + DUMP_REG(interrupts[i].itr); + DUMP_REG(interrupts[i].mir); + DUMP_REG(interrupts[i].isr_set); + DUMP_REG(interrupts[i].pending_irq); + DUMP_REG(interrupts[i].pending_fiq); + } + for (int i = 0; i < AMDM37x_IRC_IRQ_COUNT; ++i) { + DUMP_REG(ilr[i]); + } + +#undef DUMP_REG +} + +static inline void amdm37x_irc_init(amdm37x_irc_regs_t *regs) +{ + /* AMDM37x TRM sec 12.5.1 p. 2425 */ + /* Program system config register */ + //TODO enable this when you know the meaning + //regs->sysconfig |= AMDM37x_IRC_SYSCONFIG_AUTOIDLE_FLAG; + + /* Program idle register */ + //TODO enable this when you know the meaning + //regs->sysconfig |= AMDM37x_IRC_IDLE_TURBO_FLAG; + + /* Program ilr[m] assign priority, decide fiq */ + for (unsigned i = 0; i < AMDM37x_IRC_IRQ_COUNT; ++i) { + regs->ilr[i] = 0; /* highest prio(default) route to irq */ + } + + /* Disable all interrupts */ + regs->interrupts[0].mir_set = 0xffffffff; + regs->interrupts[1].mir_set = 0xffffffff; + regs->interrupts[2].mir_set = 0xffffffff; +} + +static inline unsigned amdm37x_irc_inum_get(amdm37x_irc_regs_t *regs) +{ + return regs->sir_irq & AMDM37x_IRC_SIR_IRQ_ACTIVEIRQ_MASK; +} + +static inline void amdm37x_irc_irq_ack(amdm37x_irc_regs_t *regs) +{ + regs->control = AMDM37x_IRC_CONTROL_NEWIRQAGR_FLAG; +} + +static inline void amdm37x_irc_fiq_ack(amdm37x_irc_regs_t *regs) +{ + regs->control = AMDM37x_IRC_CONTROL_NEWFIQAGR_FLAG; +} + +static inline void amdm37x_irc_enable(amdm37x_irc_regs_t *regs, unsigned inum) +{ + ASSERT(inum < AMDM37x_IRC_IRQ_COUNT); + const unsigned set = inum / 32; + const unsigned pos = inum % 32; + regs->interrupts[set].mir_clear = (1 << pos); +} + +static inline void amdm37x_irc_disable(amdm37x_irc_regs_t *regs, unsigned inum) +{ + ASSERT(inum < AMDM37x_IRC_IRQ_COUNT); + const unsigned set = inum / 32; + const unsigned pos = inum % 32; + regs->interrupts[set].mir_set = (1 << pos); +} + +#endif + +/** + * @} + */ Index: kernel/genarch/include/drivers/amdm37x_uart/amdm37x_uart.h =================================================================== --- kernel/genarch/include/drivers/amdm37x_uart/amdm37x_uart.h (revision 71d09d6e1da31c7024293452978a24f0987dfd58) +++ kernel/genarch/include/drivers/amdm37x_uart/amdm37x_uart.h (revision 71d09d6e1da31c7024293452978a24f0987dfd58) @@ -0,0 +1,459 @@ +/* + * Copyright (c) 2012 Jan Vesely + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * - Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * - Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * - The name of the author may not be used to endorse or promote products + * derived from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR + * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES + * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. + * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT + * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF + * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ +/** @addtogroup genarch + * @{ + */ +/** + * @file + * @brief Texas Instruments AMDM37x on-chip interrupt controller driver. + */ + +#ifndef KERN_AMDM37x_UART_H_ +#define KERN_AMDM37x_UART_H_ + +#include +#include +#include + +/* AMDM37x TRM p. 2950 */ +#define AMDM37x_UART1_BASE_ADDRESS 0x4806a000 +#define AMDM37x_UART1_SIZE 1024 +#define AMDM37x_UART1_IRQ 72 /* AMDM37x TRM p. 2418 */ + +#define AMDM37x_UART2_BASE_ADDRESS 0x4806b000 +#define AMDM37x_UART2_SIZE 1024 +#define AMDM37x_UART2_IRQ 73 /* AMDM37x TRM p. 2418 */ + +#define AMDM37x_UART3_BASE_ADDRESS 0x49020000 +#define AMDM37x_UART3_SIZE 1024 +#define AMDM37x_UART3_IRQ 74 /* AMDM37x TRM p. 2418 */ + +#define AMDM37x_UART4_BASE_ADDRESS 0x49042000 +#define AMDM37x_UART4_SIZE 1024 +#define AMDM37x_UART4_IRQ 80 /* AMDM37x TRM p. 2418 */ + +typedef struct { + union { + /** Stores lower part of the 14-bit baud divisor */ + ioport32_t dll; +#define AMDM37x_UART_DLL_MASK (0xff) + + /** Receive holding register */ + const ioport32_t rhr; +#define AMDM37x_UART_RHR_MASK (0xff) + + /** Transmit holding register */ + ioport32_t thr; +#define AMDM37x_UART_THR_MASK (0xff) + }; + + union { + /** Stores higher part of the 14-bit baud divisor */ + ioport32_t dlh; +#define AMDM37x_UART_DLH_MASK (0x1f) + + /** Interrupt enable registers */ + ioport32_t ier; +#define AMDM37x_UART_IER_RHR_IRQ_FLAG (1 << 0) +#define AMDM37x_UART_IER_THR_IRQ_FLAG (1 << 1) +#define AMDM37x_UART_IER_LINE_STS_IRQ_FLAG (1 << 2) +#define AMDM37x_UART_IER_MODEM_STS_IRQ_FLAG (1 << 3) +#define AMDM37x_UART_IER_SLEEP_MODE_FLAG (1 << 4) +#define AMDM37x_UART_IER_XOFF_IRQ_FLAG (1 << 5) +#define AMDM37x_UART_IER_RTS_IRQ_FLAG (1 << 6) +#define AMDM37x_UART_IER_CTS_IRQ_FLAG (1 << 7) + +#define AMDM37x_CIR_IER_RHR_IRQ_FLAG (1 << 0) +#define AMDM37x_CIR_IER_THR_IRQ_FLAG (1 << 1) +#define AMDM37x_CIR_IER_RX_STOP_IRQ_FLAG (1 << 2) +#define AMDM37x_CIR_IER_RX_OVERRUN_IRQ_FLAG (1 << 3) +#define AMDM37x_CIR_IER_TX_STS_IRQ_FLAG (1 << 5) + +#define AMDM37x_IRDA_IER_RHR_IRQ_FLAG (1 << 0) +#define AMDM37x_IRDA_IER_THR_IRQ_FLAG (1 << 1) +#define AMDM37x_IRDA_IER_LAST_RX_BYTE_IRQ_FLAG (1 << 2) +#define AMDM37x_IRDA_IER_RX_OVERRUN_IRQ_FLAG (1 << 3) +#define AMDM37x_IRDA_IER_STS_FIFO_TRIG_IRQ_FLAG (1 << 4) +#define AMDM37x_IRDA_IER_TX_STS_IRQ_FLAG (1 << 5) +#define AMDM37x_IRDA_IER_LINE_STS_IRQ_FLAG (1 << 6) +#define AMDM37x_IRDA_IER_EOF_IRQ_FLAG (1 << 7) + }; + + union { + /** Interrupt identification register */ + const ioport32_t iir; +#define AMDM37x_UART_IIR_IRQ_PENDING_FLAG (1 << 0) +#define AMDM37x_UART_IIR_TYPE_MASK (0x1f) +#define AMDM37x_UART_IIR_TYPE_SHIFT (1) +#define AMDM37x_UART_IIR_FCR_MASK (0x3) +#define AMDM37x_UART_IIR_FCR_SHIFT (6) + +#define AMDM37x_CIR_IIR_RHR_IRQ_FLAG (1 << 0) +#define AMDM37x_CIR_IIR_THR_IRQ_FLAG (1 << 1) +#define AMDM37x_CIR_IIR_RX_STOP_IRQ_FLAG (1 << 2) +#define AMDM37x_CIR_IIR_RX_OE_IRQ_FLAG (1 << 3) +#define AMDM37x_CIR_IIR_TX_STS_IRQ_FLAG (1 << 5) + +#define AMDM37x_IRDA_IIR_RHR_IRQ_FLAG (1 << 0) +#define AMDM37x_IRDA_IIR_THR_IRQ_FLAG (1 << 1) +#define AMDM37x_IRDA_IIR_RX_FIFO_LB_IRQ_FLAG (1 << 2) +#define AMDM37x_IRDA_IIR_RX_OE_IRQ_FLAG (1 << 3) +#define AMDM37x_IRDA_IIR_STS_FIFO_IRQ_FLAG (1 << 4) +#define AMDM37x_IRDA_IIR_TX_STS_IRQ_FLAG (1 << 5) +#define AMDM37x_IRDA_IIR_LINE_STS_IRQ_FLAG (1 << 6) +#define AMDM37x_IRDA_IIR_EOF_IRQ_FLAG (1 << 7) + + /** FIFO control register */ + ioport32_t fcr; +#define AMDM37x_UART_FCR_FIFO_EN_FLAG (1 << 0) +#define AMDM37x_UART_FCR_RX_FIFO_CLR_FLAG (1 << 1) +#define AMDM37x_UART_FCR_TX_FIFO_CLR_FLAG (1 << 3) +#define AMDM37x_UART_FCR_DMA_MODE_FLAG (1 << 4) + +#define AMDM37x_UART_FCR_TX_FIFO_TRIG_MASK (0x3) +#define AMDM37x_UART_FCR_TX_FIFO_TRIG_SHIFT (4) + +#define AMDM37x_UART_FCR_RX_FIFO_TRIG_MASK (0x3) +#define AMDM37x_UART_FCR_RX_FIFO_TRIG_SHIFT (6) + + /** Enhanced feature register */ + ioport32_t efr; +#define AMDM37x_UART_EFR_SW_FLOW_CTRL_RX_MASK (0x3) +#define AMDM37x_UART_EFR_SW_FLOW_CTRL_RX_SHIFT (0) +#define AMDM37x_UART_EFR_SW_FLOW_CTRL_TX_MASK (0x3) +#define AMDM37x_UART_EFR_SW_FLOW_CTRL_TX_SHIFT (2) + +#define AMDM37x_UART_EFR_SW_FLOW_CTRL_NONE (0x0) +#define AMDM37x_UART_EFR_SW_FLOW_CTRL_X2 (0x1) +#define AMDM37x_UART_EFR_SW_FLOW_CTRL_X1 (0x2) +#define AMDM37x_UART_EFR_SW_FLOW_CTRL_XBOTH (0x3) + +#define AMDM37x_UART_EFR_ENH_FLAG (1 << 4) +#define AMDM37x_UART_EFR_SPEC_CHAR_FLAG (1 << 5) +#define AMDM37x_UART_EFR_AUTO_RTS_EN_FLAG (1 << 6) +#define AMDM37x_UART_EFR_AUTO_CTS_EN_FLAG (1 << 7) + }; + + /** Line control register */ + ioport32_t lcr; +#define AMDM37x_UART_LCR_CHAR_LENGTH_MASK (0x3) +#define AMDM37x_UART_LCR_CHAR_LENGTH_SHIFT (0) +#define AMDM37x_UART_LCR_CHAR_LENGTH_5BITS (0x0) +#define AMDM37x_UART_LCR_CHAR_LENGTH_6BITS (0x1) +#define AMDM37x_UART_LCR_CHAR_LENGTH_7BITS (0x2) +#define AMDM37x_UART_LCR_CHAR_LENGTH_8BITS (0x3) +#define AMDM37x_UART_LCR_NB_STOP_FLAG (1 << 2) +#define AMDM37x_UART_LCR_PARITY_EN_FLAG (1 << 3) +#define AMDM37x_UART_LCR_PARITY_TYPE1_FLAG (1 << 4) +#define AMDM37x_UART_LCR_PARITY_TYPE2_FLAG (1 << 5) +#define AMDM37x_UART_LCR_BREAK_EN_FLAG (1 << 6) +#define AMDM37x_UART_LCR_DIV_EN_FLAG (1 << 7) + + + union { + /** Modem control register */ + ioport32_t mcr; +#define AMDM37x_UART_MCR_DTR_FLAG (1 << 0) +#define AMDM37x_UART_MCR_RTS_FLAG (1 << 1) +#define AMDM37x_UART_MCR_RI_STS_CH_FLAG (1 << 2) +#define AMDM37x_UART_MCR_CD_STS_CH_FLAG (1 << 3) +#define AMDM37x_UART_MCR_LOOPBACK_EN_FLAG (1 << 4) +#define AMDM37x_UART_MCR_XON_EN_FLAG (1 << 5) +#define AMDM37x_UART_MCR_TCR_TLR_FLAG (1 << 6) + + /** UART: XON1 char, IRDA: ADDR1 address */ + ioport32_t xon1_addr1; +#define AMDM37x_UART_XON1_ADDR1_MASK (0xff) + }; + + union { + /** Line status register */ + const ioport32_t lsr; +#define AMDM37x_UART_LSR_RX_FIFO_E_FLAG (1 << 0) +#define AMDM37x_UART_LSR_RX_OE_FLAG (1 << 1) +#define AMDM37x_UART_LSR_RX_PE_FLAG (1 << 2) +#define AMDM37x_UART_LSR_RX_FE_FLAG (1 << 3) +#define AMDM37x_UART_LSR_RX_BI_FLAG (1 << 4) +#define AMDM37x_UART_LSR_TX_FIFO_E_FLAG (1 << 5) +#define AMDM37x_UART_LSR_TX_SR_E_FLAG (1 << 6) +#define AMDM37x_UART_LSR_RX_FIFO_STS_FLAG (1 << 7) + +#define AMDM37x_CIR_LSR_RX_FIFO_E_FLAG (1 << 0) +#define AMDM37x_CIR_LSR_RX_STOP_FLAG (1 << 5) +#define AMDM37x_CIR_LSR_THR_EMPTY_FLAG (1 << 7) + +#define AMDM37x_IRDA_LSR_RX_FIFO_E_FLAG (1 << 0) +#define AMDM37x_IRDA_LSR_STS_FIFO_E_FLAG (1 << 1) +#define AMDM37x_IRDA_LSR_CRC_FLAG (1 << 2) +#define AMDM37x_IRDA_LSR_ABORT_FLAG (1 << 3) +#define AMDM37x_IRDA_LSR_FTL_FLAG (1 << 4) +#define AMDM37x_IRDA_LSR_RX_LAST_FLAG (1 << 5) +#define AMDM37x_IRDA_LSR_STS_FIFO_FULL_FLAG (1 << 6) +#define AMDM37x_IRDA_LSR_THR_EMPTY_FLAG (1 << 7) + + /** UART: XON2 char, IRDA: ADDR2 address */ + ioport32_t xon2_addr2; + }; + + union { + /** Modem status register */ + const ioport32_t msr; +#define AMDM37x_UART_MSR_CTS_STS_FLAG (1 << 0) +#define AMDM37x_UART_MSR_DSR_STS_FLAG (1 << 1) +#define AMDM37x_UART_MSR_RI_STS_FLAG (1 << 2) +#define AMDM37x_UART_MSR_DCD_STS_FLAG (1 << 3) +#define AMDM37x_UART_MSR_NCTS_STS_FLAG (1 << 4) +#define AMDM37x_UART_MSR_NDSR_STS_FLAG (1 << 5) +#define AMDM37x_UART_MSR_NRI_STS_FLAG (1 << 6) +#define AMDM37x_UART_MSR_NCD_STS_FLAG (1 << 7) + + /** Transmission control register */ + ioport32_t tcr; +#define AMDM37x_UART_TCR_FIFO_TRIG_MASK (0xf) +#define AMDM37x_UART_TCR_FIFO_TRIG_HALT_SHIFT (0) +#define AMDM37x_UART_TCR_FIFO_TRIG_START_SHIFT (4) + + /** UART: XOFF1 char */ + ioport32_t xoff1; +#define AMDM37x_UART_XOFF1_MASK (0xff) + }; + + union { + /* Scratchpad register, does nothing */ + ioport32_t spr; +#define AMDM37x_UART_SPR_MASK (0xff) + + /* Trigger level register */ + ioport32_t tlr; +#define AMDM37x_UART_TLR_LEVEL_MASK (0xf) +#define AMDM37x_UART_TLR_TX_FIFO_TRIG_SHIFT (0) +#define AMDM37x_UART_TLR_RX_FIFO_TRIG_SHIFT (4) + + /** UART: XOFF2 char */ + ioport32_t xoff2; +#define AMDM37x_UART_XOFF2_MASK (0xff) + }; + + /** Mode definition register. */ + ioport32_t mdr1; +#define AMDM37x_UART_MDR_MS_MASK (0x7) +#define AMDM37x_UART_MDR_MS_SHIFT (0) +#define AMDM37x_UART_MDR_MS_UART16 (0x0) +#define AMDM37x_UART_MDR_MS_SIR (0x1) +#define AMDM37x_UART_MDR_MS_UART16_AUTO (0x2) +#define AMDM37x_UART_MDR_MS_UART13 (0x3) +#define AMDM37x_UART_MDR_MS_MIR (0x4) +#define AMDM37x_UART_MDR_MS_FIR (0x5) +#define AMDM37x_UART_MDR_MS_CIR (0x6) +#define AMDM37x_UART_MDR_MS_DISABLE (0x7) + +#define AMDM37x_UART_MDR_IR_SLEEP_FLAG (1 << 3) +#define AMDM37x_UART_MDR_SET_TXIR_FLAG (1 << 4) +#define AMDM37x_UART_MDR_SCT_FLAG (1 << 5) +#define AMDM37x_UART_MDR_SIP_FLAG (1 << 6) +#define AMDM37x_UART_MDR_FRAME_END_MODE_FLAG (1 << 7) + + /** Mode definition register */ + ioport32_t mdr2; +#define AMDM37x_UART_MDR_IRTX_UNDERRUN_FLAG (1 << 0) +#define AMDM37x_UART_MDR_STS_FIFO_TRIG_MASK (0x3) +#define AMDM37x_UART_MDR_STS_FIFO_TRIG_SHIFT (1) +#define AMDM37x_UART_MDR_PULSE_SHAPING_FLAG (1 << 3) +#define AMDM37x_UART_MDR_CIR_PULSE_MODE_MASK (0x3) +#define AMDM37x_UART_MDR_CIR_PULSE_MODE_SHIFT (4) +#define AMDM37x_UART_MDR_IRRXINVERT_FLAG (1 << 6) + + + /* UART3 specific */ + union { + /** Status FIFO line status register (IrDA only) */ + const ioport32_t sflsr; +#define AMDM37x_IRDA_SFLSR_CRC_ERROR_FLAG (1 << 1) +#define AMDM37x_IRDA_SFLSR_ABORT_FLAG (1 << 2) +#define AMDM37x_IRDA_SFLSR_FTL_FLAG (1 << 3) +#define AMDM37x_IRDA_SFLSR_OE_FLAG (1 << 4) + + /** Transmit frame length low (IrDA only) */ + ioport32_t txfll; +#define AMDM37x_UART_TXFLL_MASK (0xff) + }; + + /* UART3 specific */ + union { + /** Dummy register to restart TX or RX (IrDA only) */ + const ioport32_t resume; + /** Transmit frame length high (IrDA only) */ + ioport32_t txflh; +#define AMDM37x_UART_TXFLH_MASK (0xff) + }; + + /* UART3 specific */ + union { + /** Status FIFO register low (IrDA only) */ + const ioport32_t sfregl; +#define AMDM37x_UART_SFREGL_MASK (0xff) + /** Received frame length low (IrDA only) */ + ioport32_t rxfll; +#define AMDM37x_UART_RXFLL_MASK (0xff) + }; + + /* UART3 specific */ + union { + /** Status FIFO register high (IrDA only) */ + const ioport32_t sfregh; +#define AMDM37x_UART_SFREGH_MASK (0xf) + /** Received frame length high (IrDA only) */ + ioport32_t rxflh; +#define AMDM37x_UART_RXFLH_MASK (0xf) + }; + + union { + /** UART autobauding status register */ + const ioport32_t uasr; +#define AMDM37x_UART_UASR_SPEED_MASK (0x1f) +#define AMDM37x_UART_UASR_SPEED_SHIFT (0) +#define AMDM37x_UART_UASR_8BIT_CHAR_FLAG (1 << 5) +#define AMDM37x_UART_UASR_PARITY_MASK (0x3) +#define AMDM37x_UART_UASR_PARITY_SHIFT (6) + + /** BOF control register (IrDA only) */ + ioport32_t blr; /* UART3 sepcific */ +#define AMDM37x_IRDA_BLR_XBOF_TYPE_FLAG (1 << 6) +#define AMDM37x_IRDA_BLR_STS_FIFO_RESET (1 << 7) + }; + + /** Auxiliary control register (IrDA only) */ + ioport32_t acreg; /* UART3 specific */ +#define AMDM37x_IRDA_ACREG_EOT_EN_FLAG (1 << 0) +#define AMDM37x_IRDA_ACREG_ABORT_EN_FLAG (1 << 1) +#define AMDM37x_IRDA_ACREG_SCTX_EN_FLAG (1 << 2) +#define AMDM37x_IRDA_ACREG_SEND_SIP_FLAG (1 << 3) +#define AMDM37x_IRDA_ACREG_DIS_TX_UNDERRUN_FLAG (1 << 4) +#define AMDM37x_IRDA_ACREG_DIS_IR_RX_FLAG (1 << 5) +#define AMDM37x_IRDA_ACREG_SD_MOD_FLAG (1 << 6) +#define AMDM37x_IRDA_ACREG_PULSE_TYPE_FLAG (1 << 7) + + /** Supplementary control register */ + ioport32_t scr; +#define AMDM37x_UART_SCR_DMA_MODE_CTL_FLAG (1 << 0) +#define AMDM37x_UART_SCR_DMA_MODE_MASK (0x3) +#define AMDM37x_UART_SCR_DMA_MODE_SHIFT (1) +#define AMDM37x_UART_SCR_TX_EMPTY_CTL_IRQ_FLAG (1 << 3) +#define AMDM37x_UART_SCR_RX_CTS_WU_EN_FLAG (1 << 4) +#define AMDM37x_UART_SCR_TX_TRIG_GRANU1_FLAG (1 << 6) +#define AMDM37x_UART_SCR_RX_TRIG_GRANU1_FLAG (1 << 7) + + /** Supplementary status register */ + const ioport32_t ssr; +#define AMDM37x_UART_SSR_TX_FIFO_FULL_FLAG (1 << 0) +#define AMDM37x_UART_SSR_RX_CTS_WU_STS_FLAG (1 << 1) +#define AMDM37x_UART_SSR_DMA_COUNTER_RESET_FLAG (1 << 2) + + /** BOF Length register (IrDA only)*/ + ioport32_t eblr; /* UART3 specific */ +#define AMDM37x_IRDA_EBLR_DISABLED (0x00) +#define AMDM37x_IRDA_EBLR_RX_STOP_BITS(bits) (bits & 0xff) + + uint32_t padd0_; + + /** Module version register */ + const ioport32_t mvr; +#define AMDM37x_UART_MVR_MINOR_MASK (0xf) +#define AMDM37x_UART_MVR_MINOR_SHIFT (0) +#define AMDM37x_UART_MVR_MAJOR_MASK (0xf) +#define AMDM37x_UART_MVR_MAJOR_SHIFT (4) + + /** System configuration register */ + ioport32_t sysc; +#define AMDM37x_UART_SYSC_AUTOIDLE_FLAG (1 << 0) +#define AMDM37x_UART_SYSC_SOFTRESET_FLAG (1 << 1) +#define AMDM37x_UART_SYSC_ENWAKEUP_FLAG (1 << 2) +#define AMDM37x_UART_SYSC_IDLE_MODE_MASK (0x3) +#define AMDM37x_UART_SYSC_IDLE_MODE_SHIFT (3) +#define AMDM37x_UART_SYSC_IDLE_MODE_FORCE (0x0) +#define AMDM37x_UART_SYSC_IDLE_MODE_NO (0x1) +#define AMDM37x_UART_SYSC_IDLE_MODE_SMART (0x2) + + /** System status register */ + const ioport32_t syss; +#define AMDM37x_UART_SYSS_RESETDONE_FLAG (1 << 0) + + /** Wake-up enable register */ + ioport32_t wer; +#define AMDM37x_UART_WER_CTS_ACTIVITY_FLAG (1 << 0) +#define AMDM37x_UART_WER_RI_ACTIVITY_FLAG (1 << 2) +#define AMDM37x_UART_WER_RX_ACTIVITY_FLAG (1 << 4) +#define AMDM37x_UART_WER_RHR_IRQ_FLAG (1 << 5) +#define AMDM37x_UART_WER_RLS_IRQ_FLAG (1 << 6) +#define AMDM37x_UART_WER_TX_WAKEUP_EN_FLAG (1 << 7) + + /** Carrier frequency prescaler */ + ioport32_t cfps; /* UART3 specific */ +#define AMDM37x_UART_CFPS_MASK (0xff) + + /** Number of bytes in RX fifo */ + const ioport32_t rx_fifo_lvl; +#define AMDM37x_UART_RX_FIFO_LVL_MASK (0xff) + + /** Number of bytes in TX fifo */ + const ioport32_t tx_fifo_lvl; +#define AMDM37x_UART_TX_FIFO_LVL_MASK (0xff) + + /** RX/TX empty interrupts */ + ioport32_t ier2; +#define AMDM37x_UART_IER2_RX_FIFO_EMPTY_IRQ_EN_FLAG (1 << 0) +#define AMDM37x_UART_IER2_TX_FIFO_EMPTY_IRQ_EN_FLAG (1 << 1) + + /** RX/TX empty status */ + ioport32_t isr2; +#define AMDM37x_UART_ISR2_RX_FIFO_EMPTY_FLAG (1 << 0) +#define AMDM37x_UART_ISR2_TX_FIFO_EMPTY_FLAG (1 << 1) + + uint32_t padd2_[3]; + + /** Mode definition register 3 */ + ioport32_t mdr3; +#define AMDM37x_UART_MDR3_DIS_CIR_RX_DEMOD_FLAG (1 << 0) +} amdm37x_uart_regs_t; + +typedef struct { + amdm37x_uart_regs_t *regs; + indev_t *indev; + outdev_t outdev; + irq_t irq; +} amdm37x_uart_t; + + +bool amdm37x_uart_init(amdm37x_uart_t *, inr_t, uintptr_t, size_t); +void amdm37x_uart_input_wire(amdm37x_uart_t *, indev_t *); + +#endif + +/** + * @} + */ Index: kernel/genarch/src/drivers/amdm37x_uart/amdm37x_uart.c =================================================================== --- kernel/genarch/src/drivers/amdm37x_uart/amdm37x_uart.c (revision 71d09d6e1da31c7024293452978a24f0987dfd58) +++ kernel/genarch/src/drivers/amdm37x_uart/amdm37x_uart.c (revision 71d09d6e1da31c7024293452978a24f0987dfd58) @@ -0,0 +1,163 @@ +/* + * Copyright (c) 2012 Jan Vesely + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * - Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * - Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * - The name of the author may not be used to endorse or promote products + * derived from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR + * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES + * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. + * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT + * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF + * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ +/** @addtogroup genarch + * @{ + */ +/** + * @file + * @brief Texas Instruments AMDM37x on-chip uart serial line driver. + */ + +#include +#include +#include +#include + +static void amdm37x_uart_txb(amdm37x_uart_t *uart, uint8_t b) +{ + /* Wait for buffer */ + while (uart->regs->ssr & AMDM37x_UART_SSR_TX_FIFO_FULL_FLAG); + /* Write to the outgoing fifo */ + uart->regs->thr = b; +} + +static void amdm37x_uart_putchar(outdev_t *dev, wchar_t ch) +{ + amdm37x_uart_t *uart = dev->data; + if (!ascii_check(ch)) { + amdm37x_uart_txb(uart, U_SPECIAL); + } else { + if (ch == '\n') + amdm37x_uart_txb(uart, '\r'); + amdm37x_uart_txb(uart, ch); + } +} + +static outdev_operations_t amdm37x_uart_ops = { + .redraw = NULL, + .write = amdm37x_uart_putchar, +}; + +static irq_ownership_t amdm37x_uart_claim(irq_t *irq) +{ + return IRQ_ACCEPT; +} + +static void amdm37x_uart_handler(irq_t *irq) +{ + amdm37x_uart_t *uart = irq->instance; + while ((uart->regs->rx_fifo_lvl)) { + const uint8_t val = uart->regs->rhr; + if (uart->indev && val) { + indev_push_character(uart->indev, val); + } + } +} + +bool amdm37x_uart_init( + amdm37x_uart_t *uart, inr_t interrupt, uintptr_t addr, size_t size) +{ + ASSERT(uart); + uart->regs = (void *)km_map(addr, size, PAGE_NOT_CACHEABLE); + + ASSERT(uart->regs); + + /* See TI OMAP35X TRM ch 17.5.1.1 p. 2732 for startup routine */ +#if 0 + /* Soft reset the port */ + uart->regs->sysc = AMDM37x_UART_SYSC_SOFTRESET_FLAG; + while (!(uart->regs->syss & AMDM37x_UART_SYSS_RESETDONE_FLAG)) ; +#endif + + /* Enable access to EFR register */ + const uint8_t lcr = uart->regs->lcr; /* Save old value */ + uart->regs->lcr = 0xbf; /* Sets config mode B */ + + /* Enable access to TCL_TLR register */ + const bool enhanced = uart->regs->efr & AMDM37x_UART_EFR_ENH_FLAG; + uart->regs->efr |= AMDM37x_UART_EFR_ENH_FLAG; /* Turn on enh. */ + uart->regs->lcr = 0x80; /* Config mode A */ + + /* Set default (val 0) triggers, disable DMA enable FIFOs */ + const bool tcl_tlr = uart->regs->mcr & AMDM37x_UART_MCR_TCR_TLR_FLAG; + /* Enable access to tcr and tlr registers */ + uart->regs->mcr |= AMDM37x_UART_MCR_TCR_TLR_FLAG; + + /* Enable FIFOs */ + uart->regs->fcr = AMDM37x_UART_FCR_FIFO_EN_FLAG; + + /* Eneble fine granularity for RX FIFO and set trigger level to 1, + * TX FIFO, trigger level is irelevant*/ + uart->regs->lcr = 0xbf; /* Sets config mode B */ + uart->regs->scr = AMDM37x_UART_SCR_RX_TRIG_GRANU1_FLAG; + uart->regs->tlr = 1 << AMDM37x_UART_TLR_RX_FIFO_TRIG_SHIFT; + + /* Restore enhanced */ + if (!enhanced) + uart->regs->efr &= ~AMDM37x_UART_EFR_ENH_FLAG; + + uart->regs->lcr = 0x80; /* Config mode A */ + /* Restore tcl_lcr access flag*/ + if (!tcl_tlr) + uart->regs->mcr &= ~AMDM37x_UART_MCR_TCR_TLR_FLAG; + + /* Restore lcr */ + uart->regs->lcr = lcr; + + /* Disable interrupts */ + uart->regs->ier = 0; + + /* Setup outdev */ + outdev_initialize("amdm37x_uart_dev", &uart->outdev, &amdm37x_uart_ops); + uart->outdev.data = uart; + + /* Initialize IRQ */ + irq_initialize(&uart->irq); + uart->irq.devno = device_assign_devno(); + uart->irq.inr = interrupt; + uart->irq.claim = amdm37x_uart_claim; + uart->irq.handler = amdm37x_uart_handler; + uart->irq.instance = uart; + + return true; +} + +void amdm37x_uart_input_wire(amdm37x_uart_t *uart, indev_t *indev) +{ + ASSERT(uart); + /* Set indev */ + uart->indev = indev; + /* Register interrupt. */ + irq_register(&uart->irq); + /* Enable interrupt on receive */ + uart->regs->ier |= AMDM37x_UART_IER_RHR_IRQ_FLAG; +} + +/** + * @} + */