Index: kernel/arch/sparc64/Makefile.inc =================================================================== --- kernel/arch/sparc64/Makefile.inc (revision 69b68d1f55687ef031fcf0c68306d1a9162c79ab) +++ kernel/arch/sparc64/Makefile.inc (revision 70a1c5973a6eaac7ac446329ee243b13fb827f5d) @@ -80,5 +80,5 @@ arch/$(KARCH)/src/proc/scheduler.c \ arch/$(KARCH)/src/proc/thread.c \ - arch/$(KARCH)/src/trap/mmu.S \ + arch/$(KARCH)/src/trap/$(USARCH)/mmu.S \ arch/$(KARCH)/src/trap/$(USARCH)/trap_table.S \ arch/$(KARCH)/src/trap/trap.c \ Index: kernel/arch/sparc64/include/trap/sun4v/mmu.h =================================================================== --- kernel/arch/sparc64/include/trap/sun4v/mmu.h (revision 69b68d1f55687ef031fcf0c68306d1a9162c79ab) +++ kernel/arch/sparc64/include/trap/sun4v/mmu.h (revision 70a1c5973a6eaac7ac446329ee243b13fb827f5d) @@ -1,4 +1,5 @@ /* * Copyright (c) 2006 Jakub Jermar + * Copyright (c) 2008 Pavel Rimsky * All rights reserved. * @@ -40,4 +41,8 @@ #include #include +#include +#include +#include +#include #include #include @@ -52,4 +57,5 @@ #define TT_FAST_DATA_ACCESS_MMU_MISS 0x68 #define TT_FAST_DATA_ACCESS_PROTECTION 0x6c +#define TT_CPU_MONDO 0x7c #define FAST_MMU_HANDLER_SIZE 128 @@ -57,86 +63,61 @@ #ifdef __ASM__ +/* MMU fault status area data fault offset */ +#define FSA_DFA_OFFSET 0x48 + +/* MMU fault status area data context */ +#define FSA_DFC_OFFSET 0x50 + +/* offset of the target address within the TTE Data entry */ +#define TTE_DATA_TADDR_OFFSET 13 + .macro FAST_INSTRUCTION_ACCESS_MMU_MISS_HANDLER - /* - * First, try to refill TLB from TSB. - */ -#ifdef CONFIG_TSB - ldxa [%g0] ASI_IMMU, %g1 ! read TSB Tag Target Register - ldxa [%g0] ASI_IMMU_TSB_8KB_PTR_REG, %g2 ! read TSB 8K Pointer - ldda [%g2] ASI_NUCLEUS_QUAD_LDD, %g4 ! 16-byte atomic load into %g4 and %g5 - cmp %g1, %g4 ! is this the entry we are looking for? - bne,pn %xcc, 0f - nop - stxa %g5, [%g0] ASI_ITLB_DATA_IN_REG ! copy mapping from ITSB to ITLB - retry -#endif - -0: - wrpr %g0, PSTATE_PRIV_BIT | PSTATE_AG_BIT, %pstate PREEMPTIBLE_HANDLER fast_instruction_access_mmu_miss .endm +/* + * Handler of the Fast Data Access MMU Miss trap. If the trap occurred in the kernel + * (context 0), an identity mapping (with displacement) is installed. Otherwise + * a higher level service routine is called. + */ .macro FAST_DATA_ACCESS_MMU_MISS_HANDLER tl -//MH - save %sp, -STACK_WINDOW_SAVE_AREA_SIZE, %sp - set 0x8000, %o0 - set 0x0, %o1 - setx 0x80000000804087c3, %g1, %o2 - set 0x3, %o3 - ta 0x83 - restore %g0, 0, %g0 - retry -#if 0 - /* - * First, try to refill TLB from TSB. - */ + mov SCRATCHPAD_MMU_FSA, %g1 + ldxa [%g1] ASI_SCRATCHPAD, %g1 ! g1 <= RA of MMU fault status area -#ifdef CONFIG_TSB - ldxa [%g0] ASI_DMMU, %g1 ! read TSB Tag Target Register - srlx %g1, TSB_TAG_TARGET_CONTEXT_SHIFT, %g2 ! is this a kernel miss? - brz,pn %g2, 0f - ldxa [%g0] ASI_DMMU_TSB_8KB_PTR_REG, %g3 ! read TSB 8K Pointer - ldda [%g3] ASI_NUCLEUS_QUAD_LDD, %g4 ! 16-byte atomic load into %g4 and %g5 - cmp %g1, %g4 ! is this the entry we are looking for? - bne,pn %xcc, 0f + /* read faulting context */ + add %g1, FSA_DFC_OFFSET, %g2 ! g2 <= RA of data fault context + ldxa [%g2] ASI_REAL, %g3 ! read the fault context + + /* read the faulting address */ + add %g1, FSA_DFA_OFFSET, %g2 ! g2 <= RA of data fault address + ldxa [%g2] ASI_REAL, %g1 ! read the fault address + srlx %g1, TTE_DATA_TADDR_OFFSET, %g1 ! truncate it to page boundary + sllx %g1, TTE_DATA_TADDR_OFFSET, %g1 + + /* service by higher-level routine when context != 0 */ + brnz %g3, 0f nop - stxa %g5, [%g0] ASI_DTLB_DATA_IN_REG ! copy mapping from DTSB to DTLB - retry -#endif + /* exclude page number 0 from installing the identity mapping */ + brz %g1, 0f + nop /* - * Second, test if it is the portion of the kernel address space - * which is faulting. If that is the case, immediately create - * identity mapping for that page in DTLB. VPN 0 is excluded from - * this treatment. - * - * Note that branch-delay slots are used in order to save space. + * Installing the identity does not fit into 32 instructions, call + * a separate routine. The routine performs RETRY, hence the call never + * returns. */ -0: -//MH -// sethi %hi(fast_data_access_mmu_miss_data_hi), %g7 - wr %g0, ASI_DMMU, %asi - ldxa [VA_DMMU_TAG_ACCESS] %asi, %g1 ! read the faulting Context and VPN - set TLB_TAG_ACCESS_CONTEXT_MASK, %g2 - andcc %g1, %g2, %g3 ! get Context - bnz %xcc, 0f ! Context is non-zero - andncc %g1, %g2, %g3 ! get page address into %g3 - bz %xcc, 0f ! page address is zero -//MH -// ldx [%g7 + %lo(end_of_identity)], %g4 - cmp %g3, %g4 - bgeu %xcc, 0f + ba install_identity_mapping + nop - ldx [%g7 + %lo(kernel_8k_tlb_data_template)], %g2 - add %g3, %g2, %g2 - stxa %g2, [%g0] ASI_DTLB_DATA_IN_REG ! identity map the kernel page - retry + 0: /* - * Third, catch and handle special cases when the trap is caused by - * the userspace register window spill or fill handler. In case - * one of these two traps caused this trap, we just lower the trap - * level and service the DTLB miss. In the end, we restart - * the offending SAVE or RESTORE. + * One of the scenarios in which this trap can occur is when the + * register window spill/fill handler accesses a memory which is not + * mapped. In such a case, this handler will be called from TL = 1. + * We handle the situation by pretending that the MMU miss occurred + * on TL = 0. Once the MMU miss trap is services, the instruction which + * caused the spill/fill trap is restarted, the spill/fill trap occurs, + * but this time its handler accesse memory which IS mapped. */ 0: @@ -146,48 +127,47 @@ /* - * Switch from the MM globals. + * Save the faulting virtual page and faulting context to the %g2 + * register. The most significant 51 bits of the %g2 register will + * contain the virtual address which caused the fault truncated to the + * page boundary. The least significant 13 bits of the %g2 register + * will contain the number of the context in which the fault occurred. + * The value of the %g2 register will be passed as a parameter to the + * higher level service routine. */ - wrpr %g0, PSTATE_PRIV_BIT | PSTATE_AG_BIT, %pstate + or %g1, %g3, %g2 - /* - * Read the Tag Access register for the higher-level handler. - * This is necessary to survive nested DTLB misses. - */ - ldxa [VA_DMMU_TAG_ACCESS] %asi, %g2 - - /* - * g2 will be passed as an argument to fast_data_access_mmu_miss(). - */ PREEMPTIBLE_HANDLER fast_data_access_mmu_miss -#endif .endm +/* + * Handler of the Fast Data MMU Protection trap. Finds the trapping address + * and context and calls higher level service routine. + */ .macro FAST_DATA_ACCESS_PROTECTION_HANDLER tl /* * The same special case as in FAST_DATA_ACCESS_MMU_MISS_HANDLER. */ + .if (\tl > 0) + wrpr %g0, 1, %tl + .endif -.if (\tl > 0) - wrpr %g0, 1, %tl -.endif + mov SCRATCHPAD_MMU_FSA, %g1 + ldxa [%g1] ASI_SCRATCHPAD, %g1 ! g1 <= RA of MMU fault status area - /* - * Switch from the MM globals. - */ - wrpr %g0, PSTATE_PRIV_BIT | PSTATE_AG_BIT, %pstate + /* read faulting context */ + add %g1, FSA_DFC_OFFSET, %g2 ! g2 <= RA of data fault context + ldxa [%g2] ASI_REAL, %g3 ! read the fault context - /* - * Read the Tag Access register for the higher-level handler. - * This is necessary to survive nested DTLB misses. - */ - mov VA_DMMU_TAG_ACCESS, %g2 - ldxa [%g2] ASI_DMMU, %g2 + /* read the faulting address */ + add %g1, FSA_DFA_OFFSET, %g2 ! g2 <= RA of data fault address + ldxa [%g2] ASI_REAL, %g1 ! read the fault address + srlx %g1, TTE_DATA_TADDR_OFFSET, %g1 ! truncate it to page boundary + sllx %g1, TTE_DATA_TADDR_OFFSET, %g1 - /* - * g2 will be passed as an argument to fast_data_access_mmu_miss(). - */ + /* the same as for FAST_DATA_ACCESS_MMU_MISS_HANDLER */ + or %g1, %g3, %g2 + PREEMPTIBLE_HANDLER fast_data_access_protection .endm - #endif /* __ASM__ */ Index: kernel/arch/sparc64/src/drivers/niagara.c =================================================================== --- kernel/arch/sparc64/src/drivers/niagara.c (revision 69b68d1f55687ef031fcf0c68306d1a9162c79ab) +++ kernel/arch/sparc64/src/drivers/niagara.c (revision 70a1c5973a6eaac7ac446329ee243b13fb827f5d) @@ -66,8 +66,5 @@ static niagara_instance_t *instance = NULL; -/* functions referenced from definitions of I/O operations structures */ static void niagara_putchar(outdev_t *, const wchar_t, bool); -//static void niagara_noop(chardev_t *); -//static char niagara_read(chardev_t *); /** character device operations */ @@ -104,10 +101,4 @@ chardev_t niagara_io; -/** - * Niagara IRQ structure. So far used only for notifying the userspace of the - * key being pressed, not for kernel being informed about keyboard interrupts. - */ -static irq_t niagara_irq; - /** defined in drivers/kbd.c */ extern kbd_type_t kbd_type; @@ -119,19 +110,4 @@ static char read_char; -/** - * The driver works in polled mode, so no interrupt should be handled by it. - */ -static irq_ownership_t niagara_claim(void) -{ - return IRQ_DECLINE; -} - -/** - * The driver works in polled mode, so no interrupt should be handled by it. - */ -static void niagara_irq_handler(irq_t *irq, void *arg, ...) -{ - panic("Not yet implemented, SGCN works in polled mode.\n"); -} #endif @@ -146,5 +122,4 @@ /** Writes a single character to the standard output. */ static void niagara_putchar(outdev_t *dev, const wchar_t ch, bool silent) -//static void niagara_putchar(struct chardev * cd, const char c) { do_putchar(ch); @@ -230,28 +205,4 @@ if (__hypercall_fast_ret1(0, 0, 0, 0, 0, CONS_GETCHAR, &c) == EOK) { indev_push_character(instance->srlnin, c); - #if 0 - ipl_t ipl = interrupts_disable(); - spinlock_lock(&niagara_irq.lock); - - if (niagara_irq.notif_cfg.notify && - niagara_irq.notif_cfg.answerbox) { - /* - * remember the character, uspace will pick it - * up using pseudocode - */ - read_char = (char) c; - ipc_irq_send_notif(&niagara_irq); - spinlock_unlock(&niagara_irq.lock); - interrupts_restore(ipl); - return; - } else { - spinlock_unlock(&niagara_irq.lock); - interrupts_restore(ipl); - - chardev_push_character(&niagara_io, c); - if (c == '\r') - chardev_push_character(&niagara_io, '\n'); - } - #endif } @@ -334,7 +285,4 @@ ddi_parea_register(&outbuf_parea); - chardev_initialize("niagara_io", &niagara_io, &niagara_ops); - stdin = &niagara_io; - stdout = &niagara_io; #endif @@ -351,5 +299,4 @@ niagara_init(); - // TODO - move to console init if (instance) { srln_instance_t *srln_instance = srln_init(); Index: kernel/arch/sparc64/src/sun4v/sparc64.c =================================================================== --- kernel/arch/sparc64/src/sun4v/sparc64.c (revision 69b68d1f55687ef031fcf0c68306d1a9162c79ab) +++ kernel/arch/sparc64/src/sun4v/sparc64.c (revision 70a1c5973a6eaac7ac446329ee243b13fb827f5d) @@ -102,6 +102,4 @@ void arch_post_smp_init(void) { - //MH - //standalone_sparc64_console_init(); niagarain_init(); } Index: rnel/arch/sparc64/src/trap/mmu.S =================================================================== --- kernel/arch/sparc64/src/trap/mmu.S (revision 69b68d1f55687ef031fcf0c68306d1a9162c79ab) +++ (revision ) @@ -1,42 +1,0 @@ -# -# Copyright (c) 2006 Jakub Jermar -# All rights reserved. -# -# Redistribution and use in source and binary forms, with or without -# modification, are permitted provided that the following conditions -# are met: -# -# - Redistributions of source code must retain the above copyright -# notice, this list of conditions and the following disclaimer. -# - Redistributions in binary form must reproduce the above copyright -# notice, this list of conditions and the following disclaimer in the -# documentation and/or other materials provided with the distribution. -# - The name of the author may not be used to endorse or promote products -# derived from this software without specific prior written permission. -# -# THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR -# IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES -# OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. -# IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, -# INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT -# NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, -# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY -# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF -# THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -# - -/** - * @file - * @brief MMU trap handlers that do not fit into the trap table. - */ - -.register %g2, #scratch -.register %g3, #scratch - -.text - -#include -#include -#include -