Index: kernel/arch/arm32/include/arch/barrier.h
===================================================================
--- kernel/arch/arm32/include/arch/barrier.h	(revision 7c3fb9bd77e4d2f6c10517a052e567f176fa91ee)
+++ kernel/arch/arm32/include/arch/barrier.h	(revision 6ff23ff32c8aa9d6ad8d06f1743ca1b0d68c14bc)
@@ -49,5 +49,6 @@
 
 #if defined PROCESSOR_ARCH_armv7_a
-/* ARMv7 uses instructions for memory barriers see ARM Architecture reference
+/*
+ * ARMv7 uses instructions for memory barriers see ARM Architecture reference
  * manual for details:
  * DMB: ch. A8.8.43 page A8-376
@@ -69,5 +70,6 @@
  * ARM Architecture Reference Manual version I ch. B.3.2.1 p. B3-4
  */
-/* ARMv6- use system control coprocessor (CP15) for memory barrier instructions.
+/*
+ * ARMv6- use system control coprocessor (CP15) for memory barrier instructions.
  * Although at least mcr p15, 0, r0, c7, c10, 4 is mentioned in earlier archs,
  * CP15 implementation is mandatory only for armv6+.
@@ -86,5 +88,6 @@
 #endif
 #else
-/* Older manuals mention syscalls as a way to implement cache coherency and
+/*
+ * Older manuals mention syscalls as a way to implement cache coherency and
  * barriers. See for example ARM Architecture Reference Manual Version D
  * chapter 2.7.4 Prefetching and self-modifying code (p. A2-28)
@@ -123,6 +126,8 @@
 	inst_barrier();                /* Wait for Inst refetch */\
 } while (0)
-/* @note: Cache type register is not available in uspace. We would need
- * to export the cache line value, or use syscall for uspace smc_coherence */
+/*
+ * @note: Cache type register is not available in uspace. We would need
+ * to export the cache line value, or use syscall for uspace smc_coherence
+ */
 #define smc_coherence_block(a, l) \
 do { \