Index: uspace/drv/bus/usb/xhci/hw_struct/context.h
===================================================================
--- uspace/drv/bus/usb/xhci/hw_struct/context.h	(revision 834d35438a5482878b497a5e240376f64b8d1022)
+++ uspace/drv/bus/usb/xhci/hw_struct/context.h	(revision 6fa91e4c93068032f387570765baf8ad5ae309d3)
@@ -52,4 +52,31 @@
 	xhci_dword_t reserved[3];
 
+#define XHCI_EP_TYPE_ISOCH_OUT		1
+#define XHCI_EP_TYPE_BULK_OUT		2
+#define XHCI_EP_TYPE_INTERRUPT_OUT	3
+#define XHCI_EP_TYPE_CONTROL		4
+#define XHCI_EP_TYPE_ISOCH_IN		5
+#define XHCI_EP_TYPE_BULK_IN		6
+#define XHCI_EP_TYPE_INTERRUPT_IN	7
+
+#define XHCI_EP_TYPE_SET(ctx, val) \
+    xhci_dword_set_bits(&(ctx).data[1], val, 5, 3)
+#define XHCI_EP_MAX_PACKET_SIZE_SET(ctx, val) \
+    xhci_dword_set_bits(&(ctx).data[1], val, 31, 16)
+#define XHCI_EP_MAX_BURST_SIZE_SET(ctx, val) \
+    xhci_dword_set_bits(&(ctx).data[1], val, 15, 8)
+#define XHCI_EP_TR_DPTR_SET(ctx, val) \
+    xhci_dword_set_bits(&(ctx).data[2], (val >> 4), 63, 4)
+#define XHCI_EP_DCS_SET(ctx, val) \
+    xhci_dword_set_bits(&(ctx).data[2], val, 0, 0)
+#define XHCI_EP_INTERVAL_SET(ctx, val) \
+    xhci_dword_set_bits(&(ctx).data[0], val, 23, 16)
+#define XHCI_EP_MAX_P_STREAMS_SET(ctx, val) \
+    xhci_dword_set_bits(&(ctx).data[0], val, 14, 10)
+#define XHCI_EP_MULT_SET(ctx, val) \
+    xhci_dword_set_bits(&(ctx).data[0], val, 9, 8)
+#define XHCI_EP_ERROR_COUNT_SET(ctx, val) \
+    xhci_dword_set_bits(&(ctx).data[1], val, 2, 1)
+
 #define XHCI_EP_STATE(ctx)              XHCI_DWORD_EXTRACT((ctx).data[0],  2,  0)
 #define XHCI_EP_MULT(ctx)               XHCI_DWORD_EXTRACT((ctx).data[0],  9,  8)
@@ -75,4 +102,9 @@
 	xhci_dword_t data [4];
 	xhci_dword_t reserved [4];
+
+#define XHCI_SLOT_ROOT_HUB_PORT_SET(ctx, val) \
+    xhci_dword_set_bits(&(ctx).data[1], val, 23, 16)
+#define XHCI_SLOT_CTX_ENTRIES_SET(ctx, val) \
+    xhci_dword_set_bits(&(ctx).data[0], val, 31, 27)
 
 #define XHCI_SLOT_ROUTE_STRING(ctx)     XHCI_DWORD_EXTRACT((ctx).data[0], 19,  0)
Index: uspace/drv/bus/usb/xhci/rh.c
===================================================================
--- uspace/drv/bus/usb/xhci/rh.c	(revision 834d35438a5482878b497a5e240376f64b8d1022)
+++ uspace/drv/bus/usb/xhci/rh.c	(revision 6fa91e4c93068032f387570765baf8ad5ae309d3)
@@ -75,13 +75,35 @@
 	XHCI_INPUT_CTRL_CTX_ADD_SET(ictx->ctrl_ctx, 1);
 
-	// TODO: Initialize ictx->slot_ctx according to section 4.3.3
-	//       point 3. This requires setters for XHCI_SLOT_* and figuring
-	//       out how are we supposed to find the root string field, which
-	//       can be found in usb3 spec section 8.9.
-
-	// TODO: Allocated and initialize transfer ring for default
-	//       control endpoint.
-	
-	// TODO: Initialize input default control endpoint 0 context.
+   	/* Initialize slot_ctx according to section 4.3.3 point 3. */
+	/* Attaching to root hub port, root string equals to 0. */
+	// TODO: shouldn't these macros consider endianity?
+	XHCI_SLOT_ROOT_HUB_PORT_SET(ictx->slot_ctx, port);
+	XHCI_SLOT_CTX_ENTRIES_SET(ictx->slot_ctx, 1);
+
+	// TODO: where do we save this? the ring should be associated with device structure somewhere
+	xhci_trb_ring_t* ep_ring = malloc32(sizeof(xhci_trb_ring_t));
+	if (!ep_ring) {
+		err = ENOMEM;
+		goto err_ring;    
+	}
+	err = xhci_trb_ring_init(ep_ring, hc);
+	if (err) {
+		xhci_trb_ring_fini(ep_ring);
+		goto err_ring;
+	}
+
+	xhci_port_regs_t* regs = &hc->op_regs->portrs[port - 1];
+	uint8_t port_speed_id = XHCI_REG_RD(regs, XHCI_PORT_PS);
+
+	XHCI_EP_TYPE_SET(ictx->endpoint_ctx[0], 4);
+	XHCI_EP_MAX_PACKET_SIZE_SET(ictx->endpoint_ctx[0], 
+	    hc->speeds[port_speed_id].tx_bps);
+	XHCI_EP_MAX_BURST_SIZE_SET(ictx->endpoint_ctx[0], 0);
+	XHCI_EP_TR_DPTR_SET(ictx->endpoint_ctx[0], ep_ring->dequeue);
+	XHCI_EP_DCS_SET(ictx->endpoint_ctx[0], 1);
+	XHCI_EP_INTERVAL_SET(ictx->endpoint_ctx[0], 0);
+	XHCI_EP_MAX_P_STREAMS_SET(ictx->endpoint_ctx[0], 0);
+	XHCI_EP_MULT_SET(ictx->endpoint_ctx[0], 0);
+	XHCI_EP_ERROR_COUNT_SET(ictx->endpoint_ctx[0], 3);
 	
 	// TODO: What's the alignment?
@@ -106,10 +128,11 @@
 err_ctx:
 	if (ictx) {
-		// To avoid double free.
+		/* Avoid double free. */
 		if (cmd && cmd->ictx && cmd->ictx == ictx)
 			cmd->ictx = NULL;
-
-		free32(ictx);
-	}
+	}
+err_ring:
+	if (ep_ring) 
+		free32(ep_ring);
 err_command:
 	if (cmd)
@@ -121,6 +144,7 @@
 {
 	uint8_t link_state = XHCI_REG_RD(regs, XHCI_PORT_PLS);
+	// FIXME: do we have a better way to detect if this is usb2 or usb3 device?
 	if (link_state == 0) {
-		// USB3 is automatically advance to enabled   
+		/* USB3 is automatically advanced to enabled. */
 		uint8_t port_speed = XHCI_REG_RD(regs, XHCI_PORT_PS);
 		usb_log_debug2("Detected new device on port %u, port speed id %u.", port_id, port_speed);
@@ -128,5 +152,5 @@
 		alloc_dev(hc, port_id);
 	} else if (link_state == 5) {
-		// USB 3 failed to enable
+		/* USB 3 failed to enable. */
 		usb_log_debug("USB 3 port couldn't be enabled.");
 	} else if (link_state == 7) {
@@ -144,15 +168,15 @@
 	xhci_port_regs_t* regs = &hc->op_regs->portrs[port_id - 1];
 
-	// Port reset change
+	/* Port reset change */
 	if (XHCI_REG_RD(regs, XHCI_PORT_PRC)) {
-		// Clear the flag
+		/* Clear the flag. */
 		XHCI_REG_WR(regs, XHCI_PORT_PRC, 1);
 
 		uint8_t port_speed = XHCI_REG_RD(regs, XHCI_PORT_PS);
 		usb_log_debug2("Detected port reset on port %u, port speed id %u.", port_id, port_speed);
-		// TODO: Assign device slot (specification 4.3.2) 
-	}
-
-	// Connection status change
+		alloc_dev(hc, port_id);
+	}
+
+	/* Connection status change */
 	if (XHCI_REG_RD(regs, XHCI_PORT_CSC)) {
 		XHCI_REG_WR(regs, XHCI_PORT_CSC, 1);
@@ -161,5 +185,5 @@
 			handle_connected_device(hc, regs, port_id);
 		} else {
-			// Device disconnected
+			// TODO: Device disconnected
 		}
 	}