Index: kernel/arch/ia32/include/arch/mm/page.h
===================================================================
--- kernel/arch/ia32/include/arch/mm/page.h	(revision bea6233f6403a8326263792f1a531eb1cb564552)
+++ kernel/arch/ia32/include/arch/mm/page.h	(revision 6e49dabfec8b39f3cfff6b845af4e23c6f1d973c)
@@ -190,5 +190,6 @@
 	    p->writeable << PAGE_WRITE_SHIFT |
 	    1 << PAGE_EXEC_SHIFT |
-	    p->global << PAGE_GLOBAL_SHIFT);
+	    p->global << PAGE_GLOBAL_SHIFT |
+	    p->page_write_through << PAGE_WRITE_COMBINE_SHIFT);
 }
 
@@ -197,9 +198,18 @@
 	pte_t *p = &pt[i];
 
-	p->page_cache_disable = !(flags & PAGE_CACHEABLE);
 	p->present = !(flags & PAGE_NOT_PRESENT);
 	p->uaccessible = (flags & PAGE_USER) != 0;
 	p->writeable = (flags & PAGE_WRITE) != 0;
 	p->global = (flags & PAGE_GLOBAL) != 0;
+
+	if (flags & PAGE_WRITE_COMBINE) {
+		/* We have mapped PCD+PWT bits to write-combine mode via PAT MSR. */
+		/* (If PAT is unsupported, it will default to uncached.) */
+		p->page_cache_disable = 1;
+		p->page_write_through = 1;
+	} else {
+		p->page_cache_disable = !(flags & PAGE_CACHEABLE);
+		p->page_write_through = 0;
+	}
 
 	/*
Index: kernel/arch/ia32/include/arch/mm/pat.h
===================================================================
--- kernel/arch/ia32/include/arch/mm/pat.h	(revision 6e49dabfec8b39f3cfff6b845af4e23c6f1d973c)
+++ kernel/arch/ia32/include/arch/mm/pat.h	(revision 6e49dabfec8b39f3cfff6b845af4e23c6f1d973c)
@@ -0,0 +1,1 @@
+../../../../amd64/include/arch/mm/pat.h