Index: uspace/drv/bus/pci/pciintel/pci.c
===================================================================
--- uspace/drv/bus/pci/pciintel/pci.c	(revision d776329b69ef4b29a8601fe5affe7faa8c58b51d)
+++ uspace/drv/bus/pci/pciintel/pci.c	(revision 6c34be69eef6e892de7663ec0a2bacb932d8c72d)
@@ -63,6 +63,7 @@
 #define NAME "pciintel"
 
+#define CONF_ADDR_ENABLE	(1 << 31)
 #define CONF_ADDR(bus, dev, fn, reg) \
-	((1 << 31) | (bus << 16) | (dev << 11) | (fn << 8) | (reg & ~3))
+	((bus << 16) | (dev << 11) | (fn << 8) | (reg & ~3))
 
 /** Obtain PCI function soft-state from DDF function node */
@@ -232,12 +233,18 @@
 	fibril_mutex_lock(&bus->conf_mutex);
 
-	pio_write_32(bus->conf_addr_reg, host2uint32_t_le(conf_addr));
-
-	/*
-	 * Always read full 32-bits from the PCI conf_data_port register and
-	 * get the desired portion of it afterwards. Some architectures do not
-	 * support shorter PIO reads offset from this register.
- 	 */
-	val = uint32_t_le2host(pio_read_32(bus->conf_data_reg));
+	if (bus->conf_addr_reg) {
+		pio_write_32(bus->conf_addr_reg,
+		    host2uint32_t_le(CONF_ADDR_ENABLE | conf_addr));
+		/*
+		 * Always read full 32-bits from the PCI conf_data_port
+		 * register and get the desired portion of it afterwards. Some
+		 * architectures do not support shorter PIO reads offset from
+		 * this register.
+	 	 */
+		val = uint32_t_le2host(pio_read_32(bus->conf_data_reg));
+	} else {
+		val = uint32_t_le2host(pio_read_32(
+		    &bus->conf_space[conf_addr / sizeof(ioport32_t)]));
+	}
 
 	switch (len) {
@@ -260,5 +267,5 @@
 	const uint32_t conf_addr = CONF_ADDR(fun->bus, fun->dev, fun->fn, reg);
 	pci_bus_t *bus = pci_bus_from_fun(fun);
-	uint32_t val = 0; // Prevent -Werror=maybe-uninitialized
+	uint32_t val;
 	
 	fibril_mutex_lock(&bus->conf_mutex);
@@ -275,6 +282,12 @@
  		 * missing bits first.
  		 */
-		pio_write_32(bus->conf_addr_reg, host2uint32_t_le(conf_addr));
-		val = uint32_t_le2host(pio_read_32(bus->conf_data_reg));
+		if (bus->conf_addr_reg) {
+			pio_write_32(bus->conf_addr_reg,
+			    host2uint32_t_le(CONF_ADDR_ENABLE | conf_addr));
+			val = uint32_t_le2host(pio_read_32(bus->conf_data_reg));
+		} else {
+			val = uint32_t_le2host(pio_read_32(
+			    &bus->conf_space[conf_addr / sizeof(ioport32_t)]));
+		}
 	}
 	
@@ -293,6 +306,12 @@
 	}
 
-	pio_write_32(bus->conf_addr_reg, host2uint32_t_le(conf_addr));
-	pio_write_32(bus->conf_data_reg, host2uint32_t_le(val));
+	if (bus->conf_addr_reg) {
+		pio_write_32(bus->conf_addr_reg,
+		    host2uint32_t_le(CONF_ADDR_ENABLE | conf_addr));
+		pio_write_32(bus->conf_data_reg, host2uint32_t_le(val));
+	} else {
+		pio_write_32(&bus->conf_space[conf_addr / sizeof(ioport32_t)],
+		    host2uint32_t_le(val));
+	}
 	
 	fibril_mutex_unlock(&bus->conf_mutex);
@@ -620,5 +639,5 @@
 			ddf_msg(LVL_DEBUG, "Adding new function %s.",
 			    ddf_fun_get_name(fun->fnode));
-			
+
 			pci_fun_create_match_ids(fun);
 			
@@ -688,27 +707,49 @@
 	
 	
-	assert(hw_resources.count > 1);
-	assert(hw_resources.resources[0].type == IO_RANGE);
-	assert(hw_resources.resources[0].res.io_range.size >= 4);
-	
-	assert(hw_resources.resources[1].type == IO_RANGE);
-	assert(hw_resources.resources[1].res.io_range.size >= 4);
-	
-	ddf_msg(LVL_DEBUG, "conf_addr = %" PRIx64 ".",
-	    hw_resources.resources[0].res.io_range.address);
-	ddf_msg(LVL_DEBUG, "data_addr = %" PRIx64 ".",
-	    hw_resources.resources[1].res.io_range.address);
-	
-	if (pio_enable_resource(&bus->pio_win, &hw_resources.resources[0],
-	    (void **) &bus->conf_addr_reg)) {
-		ddf_msg(LVL_ERROR, "Failed to enable configuration ports.");
-		rc = EADDRNOTAVAIL;
-		goto fail;
-	}
-	if (pio_enable_resource(&bus->pio_win, &hw_resources.resources[1],
-	    (void **) &bus->conf_data_reg)) {
-		ddf_msg(LVL_ERROR, "Failed to enable configuration ports.");
-		rc = EADDRNOTAVAIL;
-		goto fail;
+	assert(hw_resources.count >= 1);
+
+	if (hw_resources.count == 1) {
+		assert(hw_resources.resources[0].type == MEM_RANGE);
+
+		ddf_msg(LVL_DEBUG, "conf_addr_space = %" PRIx64 ".",
+		    hw_resources.resources[0].res.mem_range.address);
+
+		if (pio_enable_resource(&bus->pio_win,
+		    &hw_resources.resources[0],
+		    (void **) &bus->conf_space)) {
+			ddf_msg(LVL_ERROR,
+			    "Failed to map configuration space.");
+			rc = EADDRNOTAVAIL;
+			goto fail;
+		}
+		
+	} else {
+		assert(hw_resources.resources[0].type == IO_RANGE);
+		assert(hw_resources.resources[0].res.io_range.size >= 4);
+	
+		assert(hw_resources.resources[1].type == IO_RANGE);
+		assert(hw_resources.resources[1].res.io_range.size >= 4);
+	
+		ddf_msg(LVL_DEBUG, "conf_addr = %" PRIx64 ".",
+		    hw_resources.resources[0].res.io_range.address);
+		ddf_msg(LVL_DEBUG, "data_addr = %" PRIx64 ".",
+		    hw_resources.resources[1].res.io_range.address);
+	
+		if (pio_enable_resource(&bus->pio_win,
+		    &hw_resources.resources[0],
+		    (void **) &bus->conf_addr_reg)) {
+			ddf_msg(LVL_ERROR,
+			    "Failed to enable configuration ports.");
+			rc = EADDRNOTAVAIL;
+			goto fail;
+		}
+		if (pio_enable_resource(&bus->pio_win,
+		    &hw_resources.resources[1],
+		    (void **) &bus->conf_data_reg)) {
+			ddf_msg(LVL_ERROR,
+			    "Failed to enable configuration ports.");
+			rc = EADDRNOTAVAIL;
+			goto fail;
+		}
 	}
 	
Index: uspace/drv/bus/pci/pciintel/pci.h
===================================================================
--- uspace/drv/bus/pci/pciintel/pci.h	(revision d776329b69ef4b29a8601fe5affe7faa8c58b51d)
+++ uspace/drv/bus/pci/pciintel/pci.h	(revision 6c34be69eef6e892de7663ec0a2bacb932d8c72d)
@@ -47,4 +47,5 @@
 	ioport32_t *conf_addr_reg;
 	ioport32_t *conf_data_reg;
+	ioport32_t *conf_space;
 	pio_window_t pio_win;
 	fibril_mutex_t conf_mutex;