Index: kernel/arch/arm32/include/cp15.h =================================================================== --- kernel/arch/arm32/include/cp15.h (revision 813b024543d23272da72916bebaf274aeba62a0a) +++ kernel/arch/arm32/include/cp15.h (revision 6a6ebde0a0582a1049085936c5cb99cc5189a609) @@ -62,5 +62,31 @@ CONTROL_REG_GEN_READ(REVIDR, c0, 0, c0, 6); +enum { + ID_PFR0_THUMBEE_MASK = 0xf << 12, + ID_PFR0_THUMBEE = 0x1 << 12, + ID_PFR0_JAZELLE_MASK = 0xf << 8, + ID_PFR0_JAZELLE = 0x1 << 8, + ID_PFR0_JAZELLE_CV_CLEAR = 0x2 << 8, + ID_PFR0_THUMB_MASK = 0xf << 4, + ID_PFR0_THUMB = 0x1 << 4, + ID_PFR0_THUMB2 = 0x3 << 4, + ID_PFR0_ARM_MASK = 0xf << 0, + ID_PFR0_ARM = 0x1 << 0, +}; CONTROL_REG_GEN_READ(ID_PFR0, c0, 0, c1, 0); + +enum { + ID_PFR1_GEN_TIMER_EXT_MASK = 0xf << 16, + ID_PFR1_GEN_TIMER_EXT = 0x1 << 16, + ID_PFR1_VIRT_EXT_MASK = 0xf << 12, + ID_PFR1_VIRT_EXT = 0x1 << 12, + ID_PFR1_M_PROF_MASK = 0xf << 8, + ID_PFR1_M_PROF_MODEL = 0x2 << 8, + ID_PFR1_SEC_EXT_MASK = 0xf << 4, + ID_PFR1_SEC_EXT = 0x1 << 4, + ID_PFR1_SEC_EXT_RFR = 0x2 << 4, + ID_PFR1_ARMV4_MODEL_MASK = 0xf << 0, + ID_PFR1_ARMV4_MODEL = 0x1 << 0, +}; CONTROL_REG_GEN_READ(ID_PFR1, c0, 0, c1, 1); CONTROL_REG_GEN_READ(ID_DFR0, c0, 0, c1, 2); @@ -94,12 +120,42 @@ CONTROL_REG_GEN_READ(ACTLR, c1, 0, c0, 1); CONTROL_REG_GEN_WRITE(ACTLR, c1, 0, c0, 1); + +enum { + CPACR_ASEDIS_FLAG = 1 << 31, + CPACR_D32DIS_FLAG = 1 << 30, + CPACR_TRCDIS_FLAG = 1 << 28, +#define CPACR_CP_MASK(cp) (0x3 << (cp * 2)) +#define CPACR_CP_NO_ACCESS(cp) (0x0 << (cp * 2)) +#define CPACR_CP_PL1_ACCESS(cp) (0x1 << (cp * 2)) +#define CPACR_CP_FULL_ACCESS(cp) (0x3 << (cp * 2)) +}; CONTROL_REG_GEN_READ(CPACR, c1, 0, c0, 2); CONTROL_REG_GEN_WRITE(CPACR, c1, 0, c0, 2); /* Implemented as part of Security extensions */ +enum { + SCR_SIF_FLAG = 1 << 9, + SCR_HCE_FLAG = 1 << 8, + SCR_SCD_FLAG = 1 << 7, + SCR_nET_FLAG = 1 << 6, + SCR_AW_FLAG = 1 << 5, + SCR_FW_FLAG = 1 << 4, + SCR_EA_FLAG = 1 << 3, + SCR_FIQ_FLAG = 1 << 2, + SCR_IRQ_FLAG = 1 << 1, + SCR_NS_FLAG = 1 << 0, +}; CONTROL_REG_GEN_READ(SCR, c1, 0, c1, 0); CONTROL_REG_GEN_WRITE(SCR, c1, 0, c1, 0); CONTROL_REG_GEN_READ(SDER, c1, 0, c1, 1); CONTROL_REG_GEN_WRITE(SDER, c1, 0, c1, 1); + +enum { + NSACR_NSTRCDIS_FLAG = 1 << 20, + NSACR_RFR_FLAG = 1 << 19, + NSACR_NSASEDIS = 1 << 15, + NSACR_NSD32DIS = 1 << 14, +#define NSACR_CP_FLAG(cp) (1 << cp) +}; CONTROL_REG_GEN_READ(NSACR, c1, 0, c1, 2); CONTROL_REG_GEN_WRITE(NSACR, c1, 0, c1, 2); Index: kernel/arch/arm32/include/regutils.h =================================================================== --- kernel/arch/arm32/include/regutils.h (revision 813b024543d23272da72916bebaf274aeba62a0a) +++ kernel/arch/arm32/include/regutils.h (revision 6a6ebde0a0582a1049085936c5cb99cc5189a609) @@ -66,12 +66,16 @@ /* ARM Processor Operation Modes */ -#define USER_MODE 0x10 -#define FIQ_MODE 0x11 -#define IRQ_MODE 0x12 -#define SUPERVISOR_MODE 0x13 -#define ABORT_MODE 0x17 -#define UNDEFINED_MODE 0x1b -#define SYSTEM_MODE 0x1f - +enum { + USER_MODE = 0x10, + FIQ_MODE = 0x11, + IRQ_MODE = 0x12, + SUPERVISOR_MODE = 0x13, + MONITOR_MODE = 0x16, + ABORT_MODE = 0x17, + HYPERVISOR_MODE = 0x1a, + UNDEFINED_MODE = 0x1b, + SYSTEM_MODE = 0x1f, + MODE_MASK = 0x1f, +}; /* [CS]PRS manipulation macros */ #define GEN_STATUS_READ(nm, reg) \ Index: kernel/arch/arm32/include/security_ext.h =================================================================== --- kernel/arch/arm32/include/security_ext.h (revision 6a6ebde0a0582a1049085936c5cb99cc5189a609) +++ kernel/arch/arm32/include/security_ext.h (revision 6a6ebde0a0582a1049085936c5cb99cc5189a609) @@ -0,0 +1,62 @@ +/* + * Copyright (c) 2013 Jan Vesely + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * - Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * - Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * - The name of the author may not be used to endorse or promote products + * derived from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR + * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES + * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. + * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT + * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF + * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +/** @addtogroup arm32 + * @{ + */ +/** @file + * @brief Security Extensions Routines + */ + +#ifndef KERN_arm32_SECURITY_EXT_H_ +#define KERN_arm32_SECURITY_EXT_H_ + +#include +#include + +static inline bool sec_ext_is_implemented() +{ +#ifdef PROCESSOR_armv7_a + const uint32_t idpfr = ID_PFR1_read() & ID_PFR1_SEC_EXT_MASK; + return idpfr == ID_PFR1_SEC_EXT || idpfr == ID_PFR1_SEC_EXT_RFR; +#endif + return false; +} + +static inline bool sec_ext_is_secure() +{ + return sec_ext_is_implemented() + && ((current_status_reg_read() & MODE_MASK) == MONITOR_MODE + || !(SCR_read() & SCR_NS_FLAG)); +} + +#endif + +/** @} + */ + Index: kernel/arch/arm32/src/fpu_context.c =================================================================== --- kernel/arch/arm32/src/fpu_context.c (revision 813b024543d23272da72916bebaf274aeba62a0a) +++ kernel/arch/arm32/src/fpu_context.c (revision 6a6ebde0a0582a1049085936c5cb99cc5189a609) @@ -37,4 +37,5 @@ #include #include +#include #include