Index: kernel/arch/amd64/Makefile.inc =================================================================== --- kernel/arch/amd64/Makefile.inc (revision 3714e798ef2924b952664a38e4d79dd5605f73b8) +++ kernel/arch/amd64/Makefile.inc (revision 6a44ee4a35beb95618457c456010a40522d2996a) @@ -41,5 +41,5 @@ # is fixed. # -# If GCC generates a code for tail call, instead of generating .. +# When GCC generates a code for tail call, instead of generating .. # # jmp *fnc @@ -48,4 +48,6 @@ # # jmp *$fnc +# +# See http://gcc.gnu.org/bugzilla/show_bug.cgi?id=48385 for reference. # Index: kernel/arch/arm32/src/mach/gta02/gta02.c =================================================================== --- kernel/arch/arm32/src/mach/gta02/gta02.c (revision 3714e798ef2924b952664a38e4d79dd5605f73b8) +++ kernel/arch/arm32/src/mach/gta02/gta02.c (revision 6a44ee4a35beb95618457c456010a40522d2996a) @@ -158,6 +158,4 @@ { #ifdef CONFIG_FB - parea_t fb_parea; - fb_properties_t prop = { .addr = GTA02_FB_BASE, @@ -170,18 +168,11 @@ outdev_t *fb_dev = fb_init(&prop); - if (fb_dev) { + if (fb_dev) stdout_wire(fb_dev); - fb_parea.pbase = GTA02_FB_BASE; - fb_parea.frames = 150; - fb_parea.unpriv = false; - ddi_parea_register(&fb_parea); - } #endif /* Initialize serial port of the debugging console. */ - s3c24xx_uart_io_t *scons_io; - - scons_io = (void *) hw_map(GTA02_SCONS_BASE, PAGE_SIZE); - gta02_scons_dev = s3c24xx_uart_init(scons_io, S3C24XX_INT_UART2); + gta02_scons_dev = + s3c24xx_uart_init(GTA02_SCONS_BASE, S3C24XX_INT_UART2); if (gta02_scons_dev) { Index: kernel/arch/arm32/src/mach/integratorcp/integratorcp.c =================================================================== --- kernel/arch/arm32/src/mach/integratorcp/integratorcp.c (revision 3714e798ef2924b952664a38e4d79dd5605f73b8) +++ kernel/arch/arm32/src/mach/integratorcp/integratorcp.c (revision 6a44ee4a35beb95618457c456010a40522d2996a) @@ -53,5 +53,4 @@ #define SDRAM_SIZE (sdram[((*(uint32_t *)(ICP_CMCR+ICP_SDRAMCR_OFFSET) & ICP_SDRAM_MASK) >> 2)]) -static parea_t fb_parea; static icp_hw_map_t icp_hw_map; static irq_t icp_timer_irq; @@ -296,11 +295,6 @@ outdev_t *fbdev = fb_init(&prop); - if (fbdev) { + if (fbdev) stdout_wire(fbdev); - fb_parea.pbase = ICP_FB; - fb_parea.frames = 300; - fb_parea.unpriv = false; - ddi_parea_register(&fb_parea); - } #endif } Index: kernel/arch/ia32/src/boot/vesa_real.inc =================================================================== --- kernel/arch/ia32/src/boot/vesa_real.inc (revision 3714e798ef2924b952664a38e4d79dd5605f73b8) +++ kernel/arch/ia32/src/boot/vesa_real.inc (revision 6a44ee4a35beb95618457c456010a40522d2996a) @@ -154,4 +154,14 @@ mov $e_vesa_init - vesa_init, %di push %di + /* Write the "VBE2" signature into the info structure in order + * to get proper mode information. The presence of "VBE2" + * indicates two things: + * + * - VBE controller information structure is expected to be + * 512 bytes long instead of 256 bytes. + * - The BIOS should report VBE 3.0 information (potentially + * including non-standard modes in the mode list). + */ + movl $0x32454256, (%di) int $0x10 Index: kernel/arch/ia64/src/drivers/ski.c =================================================================== --- kernel/arch/ia64/src/drivers/ski.c (revision 3714e798ef2924b952664a38e4d79dd5605f73b8) +++ kernel/arch/ia64/src/drivers/ski.c (revision 6a44ee4a35beb95618457c456010a40522d2996a) @@ -57,5 +57,5 @@ }; -static void ski_putchar(outdev_t *, const wchar_t, bool); +static void ski_putchar(outdev_t *, const wchar_t); static outdev_operations_t skidev_ops = { @@ -99,7 +99,4 @@ static void poll_keyboard(ski_instance_t *instance) { - if (silent) - return; - int count = POLL_LIMIT; @@ -121,5 +118,8 @@ while (true) { - if (!silent) + // TODO FIXME: + // This currently breaks the kernel console + // before we get the override from uspace. + if (console_override) poll_keyboard(instance); @@ -182,10 +182,12 @@ * @param dev Character device. * @param ch Character to be printed. - * @param silent Whether the output should be silenced. - * - */ -static void ski_putchar(outdev_t *dev, const wchar_t ch, bool silent) -{ - if (!silent) { + * + */ +static void ski_putchar(outdev_t *dev, const wchar_t ch) +{ + // TODO FIXME: + // This currently breaks the kernel console + // before we get the override from uspace. + if (console_override) { if (ascii_check(ch)) { if (ch == '\n') @@ -213,5 +215,6 @@ if (!fb_exported) { /* - * This is the necessary evil until the userspace driver is entirely + * This is the necessary evil until + * the userspace driver is entirely * self-sufficient. */ Index: kernel/arch/mips32/Makefile.inc =================================================================== --- kernel/arch/mips32/Makefile.inc (revision 3714e798ef2924b952664a38e4d79dd5605f73b8) +++ kernel/arch/mips32/Makefile.inc (revision 6a44ee4a35beb95618457c456010a40522d2996a) @@ -29,5 +29,5 @@ BFD_ARCH = mips BFD = binary -GCC_CFLAGS += -mno-abicalls -G 0 -fno-zero-initialized-in-bss -mips3 +GCC_CFLAGS += -mno-abicalls -G 0 -fno-zero-initialized-in-bss -mips3 -mabi=32 BITS = 32 Index: kernel/arch/mips32/include/cycle.h =================================================================== --- kernel/arch/mips32/include/cycle.h (revision 3714e798ef2924b952664a38e4d79dd5605f73b8) +++ kernel/arch/mips32/include/cycle.h (revision 6a44ee4a35beb95618457c456010a40522d2996a) @@ -27,5 +27,5 @@ */ -/** @addtogroup mips2 +/** @addtogroup mips32 * @{ */ Index: kernel/arch/mips32/include/debug.h =================================================================== --- kernel/arch/mips32/include/debug.h (revision 3714e798ef2924b952664a38e4d79dd5605f73b8) +++ kernel/arch/mips32/include/debug.h (revision 6a44ee4a35beb95618457c456010a40522d2996a) @@ -34,5 +34,5 @@ #ifndef KERN_mips32_DEBUG_H_ -#define KERN_mips23_DEBUG_H_ +#define KERN_mips32_DEBUG_H_ /** Enter the simulator trace mode */ Index: kernel/arch/mips32/include/mm/frame.h =================================================================== --- kernel/arch/mips32/include/mm/frame.h (revision 3714e798ef2924b952664a38e4d79dd5605f73b8) +++ kernel/arch/mips32/include/mm/frame.h (revision 6a44ee4a35beb95618457c456010a40522d2996a) @@ -42,6 +42,4 @@ #ifndef __ASM__ -#include - extern void frame_arch_init(void); extern void physmem_print(void); Index: kernel/arch/mips32/include/stack.h =================================================================== --- kernel/arch/mips32/include/stack.h (revision 3714e798ef2924b952664a38e4d79dd5605f73b8) +++ kernel/arch/mips32/include/stack.h (revision 6a44ee4a35beb95618457c456010a40522d2996a) @@ -39,12 +39,4 @@ #define STACK_ALIGNMENT 8 -#define STACK_ARG0 0 -#define STACK_ARG1 4 -#define STACK_ARG2 8 -#define STACK_ARG3 12 -#define STACK_ARG4 16 -#define STACK_ARG5 20 -#define STACK_ARG6 24 - #endif Index: kernel/arch/mips32/src/cache.c =================================================================== --- kernel/arch/mips32/src/cache.c (revision 3714e798ef2924b952664a38e4d79dd5605f73b8) +++ kernel/arch/mips32/src/cache.c (revision 6a44ee4a35beb95618457c456010a40522d2996a) @@ -27,5 +27,5 @@ */ -/** @addtogroup mips32 +/** @addtogroup mips32 * @{ */ Index: kernel/arch/mips32/src/cpu/cpu.c =================================================================== --- kernel/arch/mips32/src/cpu/cpu.c (revision 3714e798ef2924b952664a38e4d79dd5605f73b8) +++ kernel/arch/mips32/src/cpu/cpu.c (revision 6a44ee4a35beb95618457c456010a40522d2996a) @@ -37,5 +37,5 @@ #include #include -#include +#include struct data_t { Index: kernel/arch/mips32/src/fpu_context.c =================================================================== --- kernel/arch/mips32/src/fpu_context.c (revision 3714e798ef2924b952664a38e4d79dd5605f73b8) +++ kernel/arch/mips32/src/fpu_context.c (revision 6a44ee4a35beb95618457c456010a40522d2996a) @@ -27,5 +27,5 @@ */ -/** @addtogroup mips32 +/** @addtogroup mips32 * @{ */ @@ -40,5 +40,5 @@ void fpu_disable(void) -{ +{ #ifdef CONFIG_FPU cp0_status_write(cp0_status_read() & ~cp0_status_fpu_bit); Index: kernel/arch/mips32/src/mm/as.c =================================================================== --- kernel/arch/mips32/src/mm/as.c (revision 3714e798ef2924b952664a38e4d79dd5605f73b8) +++ kernel/arch/mips32/src/mm/as.c (revision 6a44ee4a35beb95618457c456010a40522d2996a) @@ -61,9 +61,9 @@ /* * Install ASID. - */ + */ hi.value = cp0_entry_hi_read(); hi.asid = as->asid; - cp0_entry_hi_write(hi.value); + cp0_entry_hi_write(hi.value); } Index: kernel/arch/mips32/src/mm/tlb.c =================================================================== --- kernel/arch/mips32/src/mm/tlb.c (revision 3714e798ef2924b952664a38e4d79dd5605f73b8) +++ kernel/arch/mips32/src/mm/tlb.c (revision 6a44ee4a35beb95618457c456010a40522d2996a) @@ -73,5 +73,5 @@ tlbwi(); } - + /* * The kernel is going to make use of some wired @@ -386,13 +386,10 @@ ASSERT(pte->w || access != PF_ACCESS_WRITE); return pte; - break; case AS_PF_DEFER: *pfrc = AS_PF_DEFER; return NULL; - break; case AS_PF_FAULT: *pfrc = AS_PF_FAULT; return NULL; - break; default: panic("Unexpected rc (%d).", rc); Index: kernel/arch/mips32/src/start.S =================================================================== --- kernel/arch/mips32/src/start.S (revision 3714e798ef2924b952664a38e4d79dd5605f73b8) +++ kernel/arch/mips32/src/start.S (revision 6a44ee4a35beb95618457c456010a40522d2996a) @@ -222,6 +222,5 @@ /* move $k0 pointer to kernel stack */ - lui $k0, %hi(supervisor_sp) - ori $k0, $k0, %lo(supervisor_sp) + la $k0, supervisor_sp /* move $k0 (supervisor_sp) */ Index: kernel/arch/mips64/Makefile.inc =================================================================== --- kernel/arch/mips64/Makefile.inc (revision 6a44ee4a35beb95618457c456010a40522d2996a) +++ kernel/arch/mips64/Makefile.inc (revision 6a44ee4a35beb95618457c456010a40522d2996a) @@ -0,0 +1,64 @@ +# +# Copyright (c) 2005 Martin Decky +# All rights reserved. +# +# Redistribution and use in source and binary forms, with or without +# modification, are permitted provided that the following conditions +# are met: +# +# - Redistributions of source code must retain the above copyright +# notice, this list of conditions and the following disclaimer. +# - Redistributions in binary form must reproduce the above copyright +# notice, this list of conditions and the following disclaimer in the +# documentation and/or other materials provided with the distribution. +# - The name of the author may not be used to endorse or promote products +# derived from this software without specific prior written permission. +# +# THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR +# IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES +# OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. +# IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, +# INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT +# NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF +# THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +# + +BFD_ARCH = mips:4000 +BFD = binary +GCC_CFLAGS += -mno-abicalls -G 0 -fno-zero-initialized-in-bss -mips3 -mabi=64 +AFLAGS = -64 + +BITS = 64 + +## Accepted MACHINEs +# + +ifeq ($(MACHINE),msim) + BFD_NAME = elf64-tradlittlemips + ENDIANESS = LE + GCC_CFLAGS += -mhard-float +endif + +ARCH_SOURCES = \ + arch/$(KARCH)/src/start.S \ + arch/$(KARCH)/src/context.S \ + arch/$(KARCH)/src/mips64.c \ + arch/$(KARCH)/src/asm.S \ + arch/$(KARCH)/src/exception.c \ + arch/$(KARCH)/src/interrupt.c \ + arch/$(KARCH)/src/cache.c \ + arch/$(KARCH)/src/debugger.c \ + arch/$(KARCH)/src/cpu/cpu.c \ + arch/$(KARCH)/src/debug/stacktrace.c \ + arch/$(KARCH)/src/debug/stacktrace_asm.S \ + arch/$(KARCH)/src/mm/frame.c \ + arch/$(KARCH)/src/mm/page.c \ + arch/$(KARCH)/src/mm/tlb.c \ + arch/$(KARCH)/src/mm/as.c \ + arch/$(KARCH)/src/fpu_context.c \ + arch/$(KARCH)/src/ddi/ddi.c \ + arch/$(KARCH)/src/smp/dorder.c \ + arch/$(KARCH)/src/smp/smp.c Index: kernel/arch/mips64/_link.ld.in =================================================================== --- kernel/arch/mips64/_link.ld.in (revision 6a44ee4a35beb95618457c456010a40522d2996a) +++ kernel/arch/mips64/_link.ld.in (revision 6a44ee4a35beb95618457c456010a40522d2996a) @@ -0,0 +1,57 @@ +/* + * MIPS64 linker script + * + * kernel text + * kernel data + * + */ + +#undef mips +#define mips mips + +#define KERNEL_LOAD_ADDRESS 0xffffffff80100000 + +OUTPUT_ARCH(mips) +OUTPUT_FORMAT(elf64-tradlittlemips) +ENTRY(kernel_image_start) + +SECTIONS { + . = KERNEL_LOAD_ADDRESS; + .text : { + ktext_start = .; + *(.text); + ktext_end = .; + } + .data : { + kdata_start = .; + *(.data); /* initialized data */ + hardcoded_ktext_size = .; + LONG(ktext_end - ktext_start); + hardcoded_kdata_size = .; + LONG(kdata_end - kdata_start); + hardcoded_load_address = .; + LONG(KERNEL_LOAD_ADDRESS); + *(.rodata*); + *(.sdata); + *(.reginfo); + *(.sbss); + *(.scommon); + *(.bss); /* uninitialized static variables */ + *(COMMON); /* global variables */ + . = ALIGN(8); + symbol_table = .; + *(symtab.*); + } + _gp = . + 0x8000; + .lit8 : { *(.lit8) } + .lit4 : { *(.lit4) } + + kdata_end = .; + + /DISCARD/ : { + *(.mdebug*); + *(.pdr); + *(.comment); + *(.note); + } +} Index: kernel/arch/mips64/include/arch.h =================================================================== --- kernel/arch/mips64/include/arch.h (revision 6a44ee4a35beb95618457c456010a40522d2996a) +++ kernel/arch/mips64/include/arch.h (revision 6a44ee4a35beb95618457c456010a40522d2996a) @@ -0,0 +1,63 @@ +/* + * Copyright (c) 2005 Martin Decky + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * - Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * - Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * - The name of the author may not be used to endorse or promote products + * derived from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR + * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES + * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. + * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT + * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF + * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +/** @addtogroup mips64 + * @{ + */ +/** @file + */ + +#ifndef KERN_mips64_ARCH_H_ +#define KERN_mips64_ARCH_H_ + +#include + +#define TASKMAP_MAX_RECORDS 32 +#define CPUMAP_MAX_RECORDS 32 +#define BOOTINFO_TASK_NAME_BUFLEN 32 + +extern size_t cpu_count; + +typedef struct { + void *addr; + size_t size; + char name[BOOTINFO_TASK_NAME_BUFLEN]; +} utask_t; + +typedef struct { + uint32_t cpumap; + size_t cnt; + utask_t tasks[TASKMAP_MAX_RECORDS]; +} bootinfo_t; + +extern void arch_pre_main(void *entry, bootinfo_t *bootinfo); + +#endif + +/** @} + */ Index: kernel/arch/mips64/include/asm.h =================================================================== --- kernel/arch/mips64/include/asm.h (revision 6a44ee4a35beb95618457c456010a40522d2996a) +++ kernel/arch/mips64/include/asm.h (revision 6a44ee4a35beb95618457c456010a40522d2996a) @@ -0,0 +1,117 @@ +/* + * Copyright (c) 2003-2004 Jakub Jermar + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * - Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * - Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * - The name of the author may not be used to endorse or promote products + * derived from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR + * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES + * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. + * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT + * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF + * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +/** @addtogroup mips64 + * @{ + */ +/** @file + */ + +#ifndef KERN_mips64_ASM_H_ +#define KERN_mips64_ASM_H_ + +#include +#include +#include + +NO_TRACE static inline void cpu_sleep(void) +{ + /* + * Unfortunatelly most of the simulators do not support + * + * asm volatile ( + * "wait" + * ); + * + */ +} + +/** Return base address of current stack + * + * Return the base address of the current stack. + * The stack is assumed to be STACK_SIZE bytes long. + * The stack must start on page boundary. + * + */ +NO_TRACE static inline uintptr_t get_stack_base(void) +{ + uintptr_t base; + + asm volatile ( + "and %[base], $29, %[mask]\n" + : [base] "=r" (base) + : [mask] "r" (~(STACK_SIZE - 1)) + ); + + return base; +} + +NO_TRACE static inline void pio_write_8(ioport8_t *port, uint8_t v) +{ + *port = v; +} + +NO_TRACE static inline void pio_write_16(ioport16_t *port, uint16_t v) +{ + *port = v; +} + +NO_TRACE static inline void pio_write_32(ioport32_t *port, uint32_t v) +{ + *port = v; +} + +NO_TRACE static inline uint8_t pio_read_8(ioport8_t *port) +{ + return *port; +} + +NO_TRACE static inline uint16_t pio_read_16(ioport16_t *port) +{ + return *port; +} + +NO_TRACE static inline uint32_t pio_read_32(ioport32_t *port) +{ + return *port; +} + +extern void cpu_halt(void) __attribute__((noreturn)); +extern void asm_delay_loop(uint32_t); +extern void userspace_asm(uintptr_t, uintptr_t, uintptr_t); + +extern ipl_t interrupts_disable(void); +extern ipl_t interrupts_enable(void); +extern void interrupts_restore(ipl_t); +extern ipl_t interrupts_read(void); +extern bool interrupts_disabled(void); + +#endif + +/** @} + */ Index: kernel/arch/mips64/include/asm/boot.h =================================================================== --- kernel/arch/mips64/include/asm/boot.h (revision 6a44ee4a35beb95618457c456010a40522d2996a) +++ kernel/arch/mips64/include/asm/boot.h (revision 6a44ee4a35beb95618457c456010a40522d2996a) @@ -0,0 +1,44 @@ +/* + * Copyright (c) 2005 Ondrej Palkovsky + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * - Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * - Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * - The name of the author may not be used to endorse or promote products + * derived from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR + * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES + * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. + * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT + * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF + * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +/** @addtogroup mips64 + * @{ + */ +/** @file + */ + +#ifndef KERN_mips64_BOOT_H_ +#define KERN_mips64_BOOT_H_ + +/* Temporary stack size for boot process */ +#define TEMP_STACK_SIZE 0x100 + +#endif + +/** @} + */ Index: kernel/arch/mips64/include/asm/regname.h =================================================================== --- kernel/arch/mips64/include/asm/regname.h (revision 6a44ee4a35beb95618457c456010a40522d2996a) +++ kernel/arch/mips64/include/asm/regname.h (revision 6a44ee4a35beb95618457c456010a40522d2996a) @@ -0,0 +1,97 @@ +/* + * Copyright (c) 2005 Ondrej Palkovsky + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * - Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * - Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * - The name of the author may not be used to endorse or promote products + * derived from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR + * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES + * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. + * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT + * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF + * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +/** @addtogroup mips64 + * @{ + */ +/** @file + */ + +#ifndef KERN_mips64_REGNAME_H_ +#define KERN_mips64_REGNAME_H_ + +#define zero 0 +#define at 1 +#define v0 2 +#define v1 3 +#define a0 4 +#define a1 5 +#define a2 6 +#define a3 7 +#define t0 8 +#define t1 9 +#define t2 10 +#define t3 11 +#define t4 12 +#define t5 13 +#define t6 14 +#define t7 15 +#define s0 16 +#define s1 17 +#define s2 18 +#define s3 19 +#define s4 20 +#define s5 21 +#define s6 22 +#define s7 23 +#define t8 24 +#define t9 25 +#define k0 26 +#define k1 27 +#define gp 28 +#define sp 29 +#define s8 30 +#define ra 31 + +#define rindex 0 +#define rrandom 1 +#define entrylo0 2 +#define entrylo1 3 +#define context 4 +#define pagemask 5 +#define wired 6 +#define badvaddr 8 +#define count 9 +#define entryhi 10 +#define compare 11 +#define status 12 +#define cause 13 +#define epc 14 +#define rconfig 16 +#define lladdr 17 +#define watchlo 18 +#define watchhi 19 +#define xcontext 20 +#define rdebug 23 +#define depc 24 +#define eepc 30 + +#endif + +/** @} + */ Index: kernel/arch/mips64/include/atomic.h =================================================================== --- kernel/arch/mips64/include/atomic.h (revision 6a44ee4a35beb95618457c456010a40522d2996a) +++ kernel/arch/mips64/include/atomic.h (revision 6a44ee4a35beb95618457c456010a40522d2996a) @@ -0,0 +1,114 @@ +/* + * Copyright (c) 2005 Ondrej Palkovsky + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * - Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * - Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * - The name of the author may not be used to endorse or promote products + * derived from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR + * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES + * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. + * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT + * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF + * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +/** @addtogroup mips64 + * @{ + */ +/** @file + */ + +#ifndef KERN_mips64_ATOMIC_H_ +#define KERN_mips64_ATOMIC_H_ + +#include + +#define atomic_inc(x) ((void) atomic_add(x, 1)) +#define atomic_dec(x) ((void) atomic_add(x, -1)) + +#define atomic_postinc(x) (atomic_add(x, 1) - 1) +#define atomic_postdec(x) (atomic_add(x, -1) + 1) + +#define atomic_preinc(x) atomic_add(x, 1) +#define atomic_predec(x) atomic_add(x, -1) + +/* Atomic addition of immediate value. + * + * @param val Memory location to which will be the immediate value added. + * @param i Signed immediate that will be added to *val. + * + * @return Value after addition. + * + */ +NO_TRACE static inline atomic_count_t atomic_add(atomic_t *val, + atomic_count_t i) +{ + atomic_count_t tmp; + atomic_count_t v; + + asm volatile ( + "1:\n" + " lld %0, %1\n" + " daddu %0, %0, %3\n" /* same as daddi, but never traps on overflow */ + " move %2, %0\n" + " scd %0, %1\n" + " beq %0, %4, 1b\n" /* if the atomic operation failed, try again */ + " nop\n" + : "=&r" (tmp), + "+m" (val->count), + "=&r" (v) + : "r" (i), + "i" (0) + ); + + return v; +} + +NO_TRACE static inline atomic_count_t test_and_set(atomic_t *val) +{ + atomic_count_t tmp; + atomic_count_t v; + + asm volatile ( + "1:\n" + " lld %2, %1\n" + " bnez %2, 2f\n" + " dli %0, %3\n" + " scd %0, %1\n" + " beqz %0, 1b\n" + " nop\n" + "2:\n" + : "=&r" (tmp), + "+m" (val->count), + "=&r" (v) + : "i" (1) + ); + + return v; +} + +NO_TRACE static inline void atomic_lock_arch(atomic_t *val) +{ + do { + while (val->count); + } while (test_and_set(val)); +} + +#endif + +/** @} + */ Index: kernel/arch/mips64/include/barrier.h =================================================================== --- kernel/arch/mips64/include/barrier.h (revision 6a44ee4a35beb95618457c456010a40522d2996a) +++ kernel/arch/mips64/include/barrier.h (revision 6a44ee4a35beb95618457c456010a40522d2996a) @@ -0,0 +1,54 @@ +/* + * Copyright (c) 2005 Jakub Jermar + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * - Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * - Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * - The name of the author may not be used to endorse or promote products + * derived from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR + * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES + * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. + * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT + * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF + * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +/** @addtogroup mips64 + * @{ + */ +/** @file + */ + +#ifndef KERN_mips64_BARRIER_H_ +#define KERN_mips64_BARRIER_H_ + +/* + * TODO: implement true MIPS memory barriers for macros below. + */ +#define CS_ENTER_BARRIER() asm volatile ("" ::: "memory") +#define CS_LEAVE_BARRIER() asm volatile ("" ::: "memory") + +#define memory_barrier() asm volatile ("" ::: "memory") +#define read_barrier() asm volatile ("" ::: "memory") +#define write_barrier() asm volatile ("" ::: "memory") + +#define smc_coherence(a) +#define smc_coherence_block(a, l) + +#endif + +/** @} + */ Index: kernel/arch/mips64/include/cache.h =================================================================== --- kernel/arch/mips64/include/cache.h (revision 6a44ee4a35beb95618457c456010a40522d2996a) +++ kernel/arch/mips64/include/cache.h (revision 6a44ee4a35beb95618457c456010a40522d2996a) @@ -0,0 +1,45 @@ +/* + * Copyright (c) 2003-2004 Jakub Jermar + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * - Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * - Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * - The name of the author may not be used to endorse or promote products + * derived from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR + * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES + * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. + * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT + * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF + * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +/** @addtogroup mips64 + * @{ + */ +/** @file + */ + +#ifndef KERN_mips64_CACHE_H_ +#define KERN_mips64_CACHE_H_ + +#include + +extern void cache_error(istate_t *); + +#endif + +/** @} + */ Index: kernel/arch/mips64/include/context.h =================================================================== --- kernel/arch/mips64/include/context.h (revision 6a44ee4a35beb95618457c456010a40522d2996a) +++ kernel/arch/mips64/include/context.h (revision 6a44ee4a35beb95618457c456010a40522d2996a) @@ -0,0 +1,80 @@ +/* + * Copyright (c) 2003-2004 Jakub Jermar + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * - Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * - Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * - The name of the author may not be used to endorse or promote products + * derived from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR + * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES + * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. + * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT + * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF + * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +/** @addtogroup mips64 + * @{ + */ +/** @file + */ + +#ifndef KERN_mips64_CONTEXT_H_ +#define KERN_mips64_CONTEXT_H_ + +#include +#include + +/* + * Put one item onto the stack to support get_stack_base() and align it up. + */ +#define SP_DELTA (0 + ALIGN_UP(STACK_ITEM_SIZE, STACK_ALIGNMENT)) + +#ifndef __ASM__ + +#include + +#define context_set(ctx, pc, stack, size) \ + context_set_generic(ctx, pc, stack, size) + +/* + * Only save registers that must be preserved across + * function calls. + */ +typedef struct { + uintptr_t sp; + uintptr_t pc; + + uint64_t s0; + uint64_t s1; + uint64_t s2; + uint64_t s3; + uint64_t s4; + uint64_t s5; + uint64_t s6; + uint64_t s7; + uint64_t s8; + uint64_t gp; + + ipl_t ipl; +} context_t; + +#endif /* __ASM__ */ + +#endif + +/** @} + */ Index: kernel/arch/mips64/include/context_offset.h =================================================================== --- kernel/arch/mips64/include/context_offset.h (revision 6a44ee4a35beb95618457c456010a40522d2996a) +++ kernel/arch/mips64/include/context_offset.h (revision 6a44ee4a35beb95618457c456010a40522d2996a) @@ -0,0 +1,181 @@ +/* + * Copyright (c) 2005 Martin Decky + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * - Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * - Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * - The name of the author may not be used to endorse or promote products + * derived from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR + * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES + * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. + * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT + * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF + * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +#ifndef KERN_mips64_CONTEXT_OFFSET_H_ +#define KERN_mips64_CONTEXT_OFFSET_H_ + +#define OFFSET_SP 0x00 +#define OFFSET_PC 0x08 +#define OFFSET_S0 0x10 +#define OFFSET_S1 0x18 +#define OFFSET_S2 0x20 +#define OFFSET_S3 0x28 +#define OFFSET_S4 0x30 +#define OFFSET_S5 0x38 +#define OFFSET_S6 0x40 +#define OFFSET_S7 0x48 +#define OFFSET_S8 0x50 +#define OFFSET_GP 0x58 + +#ifdef KERNEL + #define OFFSET_IPL 0x60 +#else + #define OFFSET_TLS 0x60 + + #define OFFSET_F20 0x68 + #define OFFSET_F21 0x70 + #define OFFSET_F22 0x78 + #define OFFSET_F23 0x80 + #define OFFSET_F24 0x88 + #define OFFSET_F25 0x90 + #define OFFSET_F26 0x98 + #define OFFSET_F27 0xa0 + #define OFFSET_F28 0xa8 + #define OFFSET_F29 0xb0 + #define OFFSET_F30 0xb8 +#endif /* KERNEL */ + +#ifdef __ASM__ + +#include + +# ctx: address of the structure with saved context +.macro CONTEXT_SAVE_ARCH_CORE ctx:req + sd $s0, OFFSET_S0(\ctx) + sd $s1, OFFSET_S1(\ctx) + sd $s2, OFFSET_S2(\ctx) + sd $s3, OFFSET_S3(\ctx) + sd $s4, OFFSET_S4(\ctx) + sd $s5, OFFSET_S5(\ctx) + sd $s6, OFFSET_S6(\ctx) + sd $s7, OFFSET_S7(\ctx) + sd $s8, OFFSET_S8(\ctx) + sd $gp, OFFSET_GP(\ctx) + +#ifndef KERNEL + sd $k1, OFFSET_TLS(\ctx) + +#ifdef CONFIG_FPU + dmfc1 $t0, $20 + sd $t0, OFFSET_F20(\ctx) + + dmfc1 $t0,$21 + sd $t0, OFFSET_F21(\ctx) + + dmfc1 $t0,$22 + sd $t0, OFFSET_F22(\ctx) + + dmfc1 $t0,$23 + sd $t0, OFFSET_F23(\ctx) + + dmfc1 $t0,$24 + sd $t0, OFFSET_F24(\ctx) + + dmfc1 $t0,$25 + sd $t0, OFFSET_F25(\ctx) + + dmfc1 $t0,$26 + sd $t0, OFFSET_F26(\ctx) + + dmfc1 $t0,$27 + sd $t0, OFFSET_F27(\ctx) + + dmfc1 $t0,$28 + sd $t0, OFFSET_F28(\ctx) + + dmfc1 $t0,$29 + sd $t0, OFFSET_F29(\ctx) + + dmfc1 $t0,$30 + sd $t0, OFFSET_F30(\ctx) +#endif /* CONFIG_FPU */ +#endif /* KERNEL */ + + sd $ra, OFFSET_PC(\ctx) + sd $sp, OFFSET_SP(\ctx) +.endm + +# ctx: address of the structure with saved context +.macro CONTEXT_RESTORE_ARCH_CORE ctx:req + ld $s0, OFFSET_S0(\ctx) + ld $s1, OFFSET_S1(\ctx) + ld $s2, OFFSET_S2(\ctx) + ld $s3, OFFSET_S3(\ctx) + ld $s4, OFFSET_S4(\ctx) + ld $s5, OFFSET_S5(\ctx) + ld $s6, OFFSET_S6(\ctx) + ld $s7, OFFSET_S7(\ctx) + ld $s8, OFFSET_S8(\ctx) + ld $gp, OFFSET_GP(\ctx) + +#ifndef KERNEL + ld $k1, OFFSET_TLS(\ctx) + +#ifdef CONFIG_FPU + ld $t0, OFFSET_F20(\ctx) + dmtc1 $t0,$20 + + ld $t0, OFFSET_F21(\ctx) + dmtc1 $t0,$21 + + ld $t0, OFFSET_F22(\ctx) + dmtc1 $t0,$22 + + ld $t0, OFFSET_F23(\ctx) + dmtc1 $t0,$23 + + ld $t0, OFFSET_F24(\ctx) + dmtc1 $t0,$24 + + ld $t0, OFFSET_F25(\ctx) + dmtc1 $t0,$25 + + ld $t0, OFFSET_F26(\ctx) + dmtc1 $t0,$26 + + ld $t0, OFFSET_F27(\ctx) + dmtc1 $t0,$27 + + ld $t0, OFFSET_F28(\ctx) + dmtc1 $t0,$28 + + ld $t0, OFFSET_F29(\ctx) + dmtc1 $t0,$29 + + ld $t0, OFFSET_F30(\ctx) + dmtc1 $t0,$30 +#endif /* CONFIG_FPU */ +#endif /* KERNEL */ + + ld $ra, OFFSET_PC(\ctx) + ld $sp, OFFSET_SP(\ctx) +.endm + +#endif /* __ASM__ */ + +#endif Index: kernel/arch/mips64/include/cp0.h =================================================================== --- kernel/arch/mips64/include/cp0.h (revision 6a44ee4a35beb95618457c456010a40522d2996a) +++ kernel/arch/mips64/include/cp0.h (revision 6a44ee4a35beb95618457c456010a40522d2996a) @@ -0,0 +1,143 @@ +/* + * Copyright (c) 2003-2004 Jakub Jermar + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * - Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * - Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * - The name of the author may not be used to endorse or promote products + * derived from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR + * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES + * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. + * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT + * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF + * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +/** @addtogroup mips64 + * @{ + */ +/** @file + */ + +#ifndef KERN_mips64_CP0_H_ +#define KERN_mips64_CP0_H_ + +#ifdef KERNEL + +#include + +#else + +#include + +#endif + +#define cp0_status_ie_enabled_bit (1 << 0) +#define cp0_status_exl_exception_bit (1 << 1) +#define cp0_status_erl_error_bit (1 << 2) +#define cp0_status_um_bit (1 << 4) +#define cp0_status_bev_bootstrap_bit (1 << 22) +#define cp0_status_fpu_bit (1 << 29) + +#define cp0_status_im_shift 8 +#define cp0_status_im_mask 0xff00 + +#define cp0_cause_excno(cause) ((cause >> 2) & 0x1f) +#define cp0_cause_coperr(cause) ((cause >> 28) & 0x3) + +#define fpu_cop_id 1 + +/* + * Magic value for use in msim. + */ +#define cp0_compare_value 100000 + +#define cp0_mask_all_int() \ + cp0_status_write(cp0_status_read() & ~(cp0_status_im_mask)) + +#define cp0_unmask_all_int() \ + cp0_status_write(cp0_status_read() | cp0_status_im_mask) + +#define cp0_mask_int(it) \ + cp0_status_write(cp0_status_read() & ~(1 << (cp0_status_im_shift + (it)))) + +#define cp0_unmask_int(it) \ + cp0_status_write(cp0_status_read() | (1 << (cp0_status_im_shift + (it)))) + +#define GEN_READ_CP0(nm,reg) static inline uint64_t cp0_ ##nm##_read(void) \ + { \ + uint64_t retval; \ + asm volatile ( \ + "dmfc0 %0, $" #reg \ + : "=r" (retval) \ + ); \ + return retval; \ + } + +#define GEN_WRITE_CP0(nm,reg) static inline void cp0_ ##nm##_write(uint32_t val) \ + { \ + asm volatile ( \ + "dmtc0 %0, $" #reg \ + :: "r" (val) \ + ); \ + } + +GEN_READ_CP0(index, 0); +GEN_WRITE_CP0(index, 0); + +GEN_READ_CP0(random, 1); + +GEN_READ_CP0(entry_lo0, 2); +GEN_WRITE_CP0(entry_lo0, 2); + +GEN_READ_CP0(entry_lo1, 3); +GEN_WRITE_CP0(entry_lo1, 3); + +GEN_READ_CP0(context, 4); +GEN_WRITE_CP0(context, 4); + +GEN_READ_CP0(pagemask, 5); +GEN_WRITE_CP0(pagemask, 5); + +GEN_READ_CP0(wired, 6); +GEN_WRITE_CP0(wired, 6); + +GEN_READ_CP0(badvaddr, 8); + +GEN_READ_CP0(count, 9); +GEN_WRITE_CP0(count, 9); + +GEN_READ_CP0(entry_hi, 10); +GEN_WRITE_CP0(entry_hi, 10); + +GEN_READ_CP0(compare, 11); +GEN_WRITE_CP0(compare, 11); + +GEN_READ_CP0(status, 12); +GEN_WRITE_CP0(status, 12); + +GEN_READ_CP0(cause, 13); +GEN_WRITE_CP0(cause, 13); + +GEN_READ_CP0(epc, 14); +GEN_WRITE_CP0(epc, 14); + +GEN_READ_CP0(prid, 15); + +#endif + +/** @} + */ Index: kernel/arch/mips64/include/cpu.h =================================================================== --- kernel/arch/mips64/include/cpu.h (revision 6a44ee4a35beb95618457c456010a40522d2996a) +++ kernel/arch/mips64/include/cpu.h (revision 6a44ee4a35beb95618457c456010a40522d2996a) @@ -0,0 +1,49 @@ +/* + * Copyright (c) 2003-2004 Jakub Jermar + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * - Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * - Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * - The name of the author may not be used to endorse or promote products + * derived from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR + * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES + * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. + * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT + * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF + * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +/** @addtogroup mips64 + * @{ + */ +/** @file + */ + +#ifndef KERN_mips64_CPU_H_ +#define KERN_mips64_CPU_H_ + +#include +#include + +typedef struct { + uint32_t imp_num; + uint32_t rev_num; +} cpu_arch_t; + +#endif + +/** @} + */ Index: kernel/arch/mips64/include/cycle.h =================================================================== --- kernel/arch/mips64/include/cycle.h (revision 6a44ee4a35beb95618457c456010a40522d2996a) +++ kernel/arch/mips64/include/cycle.h (revision 6a44ee4a35beb95618457c456010a40522d2996a) @@ -0,0 +1,50 @@ +/* + * Copyright (c) 2006 Martin Decky + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * - Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * - Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * - The name of the author may not be used to endorse or promote products + * derived from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR + * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES + * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. + * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT + * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF + * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +/** @addtogroup mips64 + * @{ + */ +/** @file + */ + +#ifndef KERN_mips64_CYCLE_H_ +#define KERN_mips64_CYCLE_H_ + +#include +#include +#include + +NO_TRACE static inline uint64_t get_cycle(void) +{ + return ((uint64_t) count_hi << 32) + ((uint64_t) cp0_count_read()); +} + +#endif + +/** @} + */ Index: kernel/arch/mips64/include/debug.h =================================================================== --- kernel/arch/mips64/include/debug.h (revision 6a44ee4a35beb95618457c456010a40522d2996a) +++ kernel/arch/mips64/include/debug.h (revision 6a44ee4a35beb95618457c456010a40522d2996a) @@ -0,0 +1,71 @@ +/* + * Copyright (c) 2005 Ondrej Palkovsky + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * - Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * - Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * - The name of the author may not be used to endorse or promote products + * derived from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR + * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES + * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. + * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT + * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF + * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +/** @addtogroup mips64 + * @{ + */ +/** @file + */ + +#ifndef KERN_mips64_DEBUG_H_ +#define KERN_mips64_DEBUG_H_ + +/** Enter the simulator trace mode */ +#define ___traceon() \ + asm volatile ( \ + "\t.word\t0x39\n" \ + ); + +/** Leave the simulator trace mode */ +#define ___traceoff() \ + asm volatile ( \ + "\t.word\t0x3d\n" \ + ); + +/** Ask the simulator to dump registers */ +#define ___regview() \ + asm volatile ( \ + "\t.word\t0x37\n" \ + ); + +/** Halt the simulator */ +#define ___halt() \ + asm volatile ( \ + "\t.word\t0x28\n" \ + ); + +/** Enter the simulator interactive mode */ +#define ___intmode() \ + asm volatile ( \ + "\t.word\t0x29\n" \ + ); + +#endif + +/** @} + */ Index: kernel/arch/mips64/include/debugger.h =================================================================== --- kernel/arch/mips64/include/debugger.h (revision 6a44ee4a35beb95618457c456010a40522d2996a) +++ kernel/arch/mips64/include/debugger.h (revision 6a44ee4a35beb95618457c456010a40522d2996a) @@ -0,0 +1,78 @@ +/* + * Copyright (c) 2005 Ondrej Palkovsky + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * - Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * - Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * - The name of the author may not be used to endorse or promote products + * derived from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR + * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES + * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. + * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT + * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF + * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +/** @addtogroup mips64 + * @{ + */ +/** @file + */ + +#ifndef KERN_mips64_DEBUGGER_H_ +#define KERN_mips64_DEBUGGER_H_ + +#include +#include + +#define BKPOINTS_MAX 10 + +/** Breakpoint was shot */ +#define BKPOINT_INPROG (1 << 0) + +/** One-time breakpoint, mandatory for j/b instructions */ +#define BKPOINT_ONESHOT (1 << 1) + +/** + * Breakpoint is set on the next instruction, so that it + * could be reinstalled on the previous one + */ +#define BKPOINT_REINST (1 << 2) + +/** Call a predefined function */ +#define BKPOINT_FUNCCALL (1 << 3) + + +typedef struct { + uintptr_t address; /**< Breakpoint address */ + sysarg_t instruction; /**< Original instruction */ + sysarg_t nextinstruction; /**< Original instruction following break */ + unsigned int flags; /**< Flags regarding breakpoint */ + size_t counter; + void (*bkfunc)(void *, istate_t *); +} bpinfo_t; + +extern bpinfo_t breakpoints[BKPOINTS_MAX]; + +extern bool is_jump(sysarg_t); + +extern void debugger_init(void); +extern void debugger_bpoint(istate_t *); + +#endif + +/** @} + */ Index: kernel/arch/mips64/include/drivers/msim.h =================================================================== --- kernel/arch/mips64/include/drivers/msim.h (revision 6a44ee4a35beb95618457c456010a40522d2996a) +++ kernel/arch/mips64/include/drivers/msim.h (revision 6a44ee4a35beb95618457c456010a40522d2996a) @@ -0,0 +1,46 @@ +/* + * Copyright (c) 2005 Ondrej Palkovsky + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * - Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * - Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * - The name of the author may not be used to endorse or promote products + * derived from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR + * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES + * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. + * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT + * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF + * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +/** @addtogroup mips64 + * @{ + */ +/** @file + */ + +#ifndef KERN_mips64_MSIM_H_ +#define KERN_mips64_MSIM_H_ + +/** Address of devices. */ +#define MSIM_VIDEORAM 0xffffffff90000000 +#define MSIM_KBD_ADDRESS 0xffffffff90000000 +#define MSIM_KBD_IRQ 2 + +#endif + +/** @} + */ Index: kernel/arch/mips64/include/elf.h =================================================================== --- kernel/arch/mips64/include/elf.h (revision 6a44ee4a35beb95618457c456010a40522d2996a) +++ kernel/arch/mips64/include/elf.h (revision 6a44ee4a35beb95618457c456010a40522d2996a) @@ -0,0 +1,51 @@ +/* + * Copyright (c) 2006 Sergey Bondari + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * - Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * - Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * - The name of the author may not be used to endorse or promote products + * derived from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR + * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES + * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. + * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT + * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF + * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +/** @addtogroup mips64 + * @{ + */ +/** @file + */ + +#ifndef KERN_mips64_ELF_H_ +#define KERN_mips64_ELF_H_ + +#define ELF_MACHINE EM_MIPS + +#ifdef __BE__ + #define ELF_DATA_ENCODING ELFDATA2MSB +#else + #define ELF_DATA_ENCODING ELFDATA2LSB +#endif + +#define ELF_CLASS ELFCLASS64 + +#endif + +/** @} + */ Index: kernel/arch/mips64/include/exception.h =================================================================== --- kernel/arch/mips64/include/exception.h (revision 6a44ee4a35beb95618457c456010a40522d2996a) +++ kernel/arch/mips64/include/exception.h (revision 6a44ee4a35beb95618457c456010a40522d2996a) @@ -0,0 +1,69 @@ +/* + * Copyright (c) 2003-2004 Jakub Jermar + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * - Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * - Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * - The name of the author may not be used to endorse or promote products + * derived from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR + * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES + * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. + * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT + * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF + * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +/** @addtogroup mips64 + * @{ + */ +/** @file + */ + +#ifndef KERN_mips64_EXCEPTION_H_ +#define KERN_mips64_EXCEPTION_H_ + +#include +#include + +#define EXC_Int 0 +#define EXC_Mod 1 +#define EXC_TLBL 2 +#define EXC_TLBS 3 +#define EXC_AdEL 4 +#define EXC_AdES 5 +#define EXC_IBE 6 +#define EXC_DBE 7 +#define EXC_Sys 8 +#define EXC_Bp 9 +#define EXC_RI 10 +#define EXC_CpU 11 +#define EXC_Ov 12 +#define EXC_Tr 13 +#define EXC_VCEI 14 +#define EXC_FPE 15 +#define EXC_WATCH 23 +#define EXC_VCED 31 + +extern void exception(istate_t *istate); +extern void tlb_refill_entry(void); +extern void exception_entry(void); +extern void cache_error_entry(void); +extern void exception_init(void); + +#endif + +/** @} + */ Index: kernel/arch/mips64/include/faddr.h =================================================================== --- kernel/arch/mips64/include/faddr.h (revision 6a44ee4a35beb95618457c456010a40522d2996a) +++ kernel/arch/mips64/include/faddr.h (revision 6a44ee4a35beb95618457c456010a40522d2996a) @@ -0,0 +1,45 @@ +/* + * Copyright (c) 2005 Jakub Jermar + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * - Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * - Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * - The name of the author may not be used to endorse or promote products + * derived from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR + * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES + * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. + * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT + * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF + * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +/** @addtogroup mips64 + * @{ + */ +/** @file + */ + +#ifndef KERN_mips64_FADDR_H_ +#define KERN_mips64_FADDR_H_ + +#include + +#define FADDR(fptr) ((uintptr_t) (fptr)) + +#endif + +/** @} + */ Index: kernel/arch/mips64/include/fpu_context.h =================================================================== --- kernel/arch/mips64/include/fpu_context.h (revision 6a44ee4a35beb95618457c456010a40522d2996a) +++ kernel/arch/mips64/include/fpu_context.h (revision 6a44ee4a35beb95618457c456010a40522d2996a) @@ -0,0 +1,50 @@ +/* + * Copyright (c) 2005 Jakub Vana + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * - Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * - Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * - The name of the author may not be used to endorse or promote products + * derived from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR + * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES + * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. + * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT + * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF + * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +/** @addtogroup mips64 + * @{ + */ +/** @file + */ + +#ifndef KERN_mips64_FPU_CONTEXT_H_ +#define KERN_mips64_FPU_CONTEXT_H_ + +#include + +#define FPU_CONTEXT_ALIGN sizeof(sysarg_t) + +typedef struct { + sysarg_t dregs[32]; + sysarg_t cregs[32]; +} fpu_context_t; + +#endif + +/** @} + */ Index: kernel/arch/mips64/include/interrupt.h =================================================================== --- kernel/arch/mips64/include/interrupt.h (revision 6a44ee4a35beb95618457c456010a40522d2996a) +++ kernel/arch/mips64/include/interrupt.h (revision 6a44ee4a35beb95618457c456010a40522d2996a) @@ -0,0 +1,54 @@ +/* + * Copyright (c) 2003-2004 Jakub Jermar + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * - Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * - Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * - The name of the author may not be used to endorse or promote products + * derived from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR + * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES + * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. + * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT + * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF + * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +/** @addtogroup mips64 + * @{ + */ +/** @file + */ + +#ifndef KERN_mips64_INTERRUPT_H_ +#define KERN_mips64_INTERRUPT_H_ + +#include +#include + +#define IVT_ITEMS 32 +#define IVT_FIRST 0 + +#define VECTOR_TLB_SHOOTDOWN_IPI EXC_Int + +extern function virtual_timer_fnc; +extern uint32_t count_hi; + +extern void interrupt_init(void); + +#endif + +/** @} + */ Index: kernel/arch/mips64/include/istate.h =================================================================== --- kernel/arch/mips64/include/istate.h (revision 6a44ee4a35beb95618457c456010a40522d2996a) +++ kernel/arch/mips64/include/istate.h (revision 6a44ee4a35beb95618457c456010a40522d2996a) @@ -0,0 +1,121 @@ +/* + * Copyright (c) 2003-2004 Jakub Jermar + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * - Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * - Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * - The name of the author may not be used to endorse or promote products + * derived from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR + * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES + * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. + * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT + * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF + * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +/** @addtogroup mips64 + * @{ + */ +/** @file + */ + +#ifndef KERN_mips64_ISTATE_H_ +#define KERN_mips64_ISTATE_H_ + +#include + +#ifdef KERNEL + +#include +#include + +#else + +#include +#define NO_TRACE + +#endif + +typedef struct istate { + /* + * The first seven registers are arranged so that the istate structure + * can be used both for exception handlers and for the syscall handler. + */ + uint64_t a0; /* arg1 */ + uint64_t a1; /* arg2 */ + uint64_t a2; /* arg3 */ + uint64_t a3; /* arg4 */ + uint64_t t0; /* arg5 */ + uint64_t t1; /* arg6 */ + uint64_t v0; /* arg7 */ + uint64_t v1; + uint64_t at; + uint64_t t2; + uint64_t t3; + uint64_t t4; + uint64_t t5; + uint64_t t6; + uint64_t t7; + uint64_t s0; + uint64_t s1; + uint64_t s2; + uint64_t s3; + uint64_t s4; + uint64_t s5; + uint64_t s6; + uint64_t s7; + uint64_t t8; + uint64_t t9; + uint64_t kt0; + uint64_t kt1; /* We use it as thread-local pointer */ + uint64_t gp; + uint64_t sp; + uint64_t s8; + uint64_t ra; + + uint64_t lo; + uint64_t hi; + + uint64_t status; /* cp0_status */ + uint64_t epc; /* cp0_epc */ +} istate_t; + +NO_TRACE static inline void istate_set_retaddr(istate_t *istate, + uintptr_t retaddr) +{ + istate->epc = retaddr; +} + +/** Return true if exception happened while in userspace */ +NO_TRACE static inline int istate_from_uspace(istate_t *istate) +{ + return istate->status & cp0_status_um_bit; +} + +NO_TRACE static inline uintptr_t istate_get_pc(istate_t *istate) +{ + return istate->epc; +} + +NO_TRACE static inline uintptr_t istate_get_fp(istate_t *istate) +{ + return istate->sp; +} + +#endif + +/** @} + */ Index: kernel/arch/mips64/include/mm/as.h =================================================================== --- kernel/arch/mips64/include/mm/as.h (revision 6a44ee4a35beb95618457c456010a40522d2996a) +++ kernel/arch/mips64/include/mm/as.h (revision 6a44ee4a35beb95618457c456010a40522d2996a) @@ -0,0 +1,61 @@ +/* + * Copyright (c) 2005 Jakub Jermar + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * - Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * - Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * - The name of the author may not be used to endorse or promote products + * derived from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR + * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES + * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. + * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT + * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF + * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +/** @addtogroup mips64mm + * @{ + */ +/** @file + */ + +#ifndef KERN_mips64_AS_H_ +#define KERN_mips64_AS_H_ + +#define KERNEL_ADDRESS_SPACE_SHADOWED_ARCH 0 + +#define KERNEL_ADDRESS_SPACE_START_ARCH UINT64_C(0xffffffff80000000) +#define KERNEL_ADDRESS_SPACE_END_ARCH UINT64_C(0xffffffff9fffffff) +#define USER_ADDRESS_SPACE_START_ARCH UINT64_C(0x0000000000000000) +#define USER_ADDRESS_SPACE_END_ARCH UINT32_C(0x000000ffffffffff) + +typedef struct { +} as_arch_t; + +#include + +#define as_constructor_arch(as, flags) (as != as) +#define as_destructor_arch(as) (as != as) +#define as_create_arch(as, flags) (as != as) +#define as_deinstall_arch(as) +#define as_invalidate_translation_cache(as, page, cnt) + +extern void as_arch_init(void); + +#endif + +/** @} + */ Index: kernel/arch/mips64/include/mm/asid.h =================================================================== --- kernel/arch/mips64/include/mm/asid.h (revision 6a44ee4a35beb95618457c456010a40522d2996a) +++ kernel/arch/mips64/include/mm/asid.h (revision 6a44ee4a35beb95618457c456010a40522d2996a) @@ -0,0 +1,47 @@ +/* + * Copyright (c) 2005 Martin Decky + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * - Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * - Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * - The name of the author may not be used to endorse or promote products + * derived from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR + * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES + * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. + * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT + * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF + * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +/** @addtogroup mips64mm + * @{ + */ +/** @file + */ + +#ifndef KERN_mips64_ASID_H_ +#define KERN_mips64_ASID_H_ + +#include + +#define ASID_MAX_ARCH 255 /* 2^8 - 1 */ + +typedef uint8_t asid_t; + +#endif + +/** @} + */ Index: kernel/arch/mips64/include/mm/frame.h =================================================================== --- kernel/arch/mips64/include/mm/frame.h (revision 6a44ee4a35beb95618457c456010a40522d2996a) +++ kernel/arch/mips64/include/mm/frame.h (revision 6a44ee4a35beb95618457c456010a40522d2996a) @@ -0,0 +1,53 @@ +/* + * Copyright (c) 2005 Jakub Jermar + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * - Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * - Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * - The name of the author may not be used to endorse or promote products + * derived from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR + * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES + * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. + * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT + * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF + * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +/** @addtogroup mips64mm + * @{ + */ +/** @file + */ + +#ifndef KERN_mips64_FRAME_H_ +#define KERN_mips64_FRAME_H_ + +#define FRAME_WIDTH 14 /* 16K */ +#define FRAME_SIZE (1 << FRAME_WIDTH) + +#ifdef KERNEL +#ifndef __ASM__ + +extern void frame_arch_init(void); +extern void physmem_print(void); + +#endif /* __ASM__ */ +#endif /* KERNEL */ + +#endif + +/** @} + */ Index: kernel/arch/mips64/include/mm/page.h =================================================================== --- kernel/arch/mips64/include/mm/page.h (revision 6a44ee4a35beb95618457c456010a40522d2996a) +++ kernel/arch/mips64/include/mm/page.h (revision 6a44ee4a35beb95618457c456010a40522d2996a) @@ -0,0 +1,63 @@ +/* + * Copyright (c) 2003-2004 Jakub Jermar + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * - Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * - Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * - The name of the author may not be used to endorse or promote products + * derived from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR + * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES + * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. + * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT + * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF + * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +/** @addtogroup mips64mm + * @{ + */ +/** @file + */ + +#ifndef KERN_mips64_PAGE_H_ +#define KERN_mips64_PAGE_H_ + +#include +#include + +#define PAGE_WIDTH FRAME_WIDTH +#define PAGE_SIZE FRAME_SIZE + +#ifndef __ASM__ + #define KA2PA(addr) (((uintptr_t) (addr)) - 0xffffffff80000000) + #define PA2KA(addr) (((uintptr_t) (addr)) + 0xffffffff80000000) +#else + #define KA2PA(addr) ((addr) - 0xffffffff80000000) + #define PA2KA(addr) ((addr) + 0xffffffff80000000) +#endif + +#ifdef KERNEL +#ifndef __ASM__ + +extern void page_arch_init(void); + +#endif /* __ASM__ */ +#endif /* KERNEL */ + +#endif + +/** @} + */ Index: kernel/arch/mips64/include/mm/tlb.h =================================================================== --- kernel/arch/mips64/include/mm/tlb.h (revision 6a44ee4a35beb95618457c456010a40522d2996a) +++ kernel/arch/mips64/include/mm/tlb.h (revision 6a44ee4a35beb95618457c456010a40522d2996a) @@ -0,0 +1,181 @@ +/* + * Copyright (c) 2003-2004 Jakub Jermar + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * - Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * - Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * - The name of the author may not be used to endorse or promote products + * derived from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR + * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES + * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. + * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT + * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF + * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +/** @addtogroup mips64mm + * @{ + */ +/** @file + */ + +#ifndef KERN_mips64_TLB_H_ +#define KERN_mips64_TLB_H_ + +#include +#include +#include +#include + +#define TLB_ENTRY_COUNT 48 + +#define TLB_WIRED 1 +#define TLB_KSTACK_WIRED_INDEX 0 + +#define TLB_PAGE_MASK_4K (0x000 << 13) +#define TLB_PAGE_MASK_16K (0x003 << 13) +#define TLB_PAGE_MASK_64K (0x00f << 13) +#define TLB_PAGE_MASK_256K (0x03f << 13) +#define TLB_PAGE_MASK_1M (0x0ff << 13) +#define TLB_PAGE_MASK_4M (0x3ff << 13) +#define TLB_PAGE_MASK_16M (0xfff << 13) + +#define PAGE_UNCACHED 2 +#define PAGE_CACHEABLE_EXC_WRITE 5 + +typedef union { + struct { +#ifdef __BE__ + unsigned int : 2; /* zero */ + unsigned int pfn : 24; /* frame number */ + unsigned int c : 3; /* cache coherency attribute */ + unsigned int d : 1; /* dirty/write-protect bit */ + unsigned int v : 1; /* valid bit */ + unsigned int g : 1; /* global bit */ +#else + unsigned int g : 1; /* global bit */ + unsigned int v : 1; /* valid bit */ + unsigned int d : 1; /* dirty/write-protect bit */ + unsigned int c : 3; /* cache coherency attribute */ + unsigned int pfn : 24; /* frame number */ + unsigned int : 2; /* zero */ +#endif + } __attribute__ ((packed)); + uint32_t value; +} entry_lo_t; + +typedef union { + struct { +#ifdef __BE__ + unsigned int vpn2 : 19; + unsigned int : 5; + unsigned int asid : 8; +#else + unsigned int asid : 8; + unsigned int : 5; + unsigned int vpn2 : 19; +#endif + } __attribute__ ((packed)); + uint32_t value; +} entry_hi_t; + +typedef union { + struct { +#ifdef __BE__ + unsigned int : 7; + unsigned int mask : 12; + unsigned int : 13; +#else + unsigned int : 13; + unsigned int mask : 12; + unsigned int : 7; +#endif + } __attribute__ ((packed)); + uint32_t value; +} page_mask_t; + +typedef union { + struct { +#ifdef __BE__ + unsigned int p : 1; + unsigned int : 27; + unsigned int index : 4; +#else + unsigned int index : 4; + unsigned int : 27; + unsigned int p : 1; +#endif + } __attribute__ ((packed)); + uint32_t value; +} tlb_index_t; + +/** Probe TLB for Matching Entry + * + * Probe TLB for Matching Entry. + */ +NO_TRACE static inline void tlbp(void) +{ + asm volatile ( + "tlbp\n\t" + ); +} + +/** Read Indexed TLB Entry + * + * Read Indexed TLB Entry. + */ +NO_TRACE static inline void tlbr(void) +{ + asm volatile ( + "tlbr\n\t" + ); +} + +/** Write Indexed TLB Entry + * + * Write Indexed TLB Entry. + */ +NO_TRACE static inline void tlbwi(void) +{ + asm volatile ( + "tlbwi\n\t" + ); +} + +/** Write Random TLB Entry + * + * Write Random TLB Entry. + */ +NO_TRACE static inline void tlbwr(void) +{ + asm volatile ( + "tlbwr\n\t" + ); +} + +#define tlb_invalidate(asid) tlb_invalidate_asid(asid) + +extern void tlb_invalid(istate_t *); +extern void tlb_refill(istate_t *); +extern void tlb_modified(istate_t *); +extern void tlb_prepare_entry_lo(entry_lo_t *, bool, bool, bool, bool, + uintptr_t); +extern void tlb_prepare_entry_hi(entry_hi_t *, asid_t, uintptr_t); + +#endif + +/** @} + */ Index: kernel/arch/mips64/include/proc/task.h =================================================================== --- kernel/arch/mips64/include/proc/task.h (revision 6a44ee4a35beb95618457c456010a40522d2996a) +++ kernel/arch/mips64/include/proc/task.h (revision 6a44ee4a35beb95618457c456010a40522d2996a) @@ -0,0 +1,47 @@ +/* + * Copyright (c) 2006 Jakub Jermar + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * - Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * - Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * - The name of the author may not be used to endorse or promote products + * derived from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR + * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES + * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. + * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT + * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF + * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +/** @addtogroup mips64proc + * @{ + */ +/** @file + */ + +#ifndef KERN_mips64_TASK_H_ +#define KERN_mips64_TASK_H_ + +typedef struct { +} task_arch_t; + +#define task_create_arch(task) +#define task_destroy_arch(task) + +#endif + +/** @} + */ Index: kernel/arch/mips64/include/proc/thread.h =================================================================== --- kernel/arch/mips64/include/proc/thread.h (revision 6a44ee4a35beb95618457c456010a40522d2996a) +++ kernel/arch/mips64/include/proc/thread.h (revision 6a44ee4a35beb95618457c456010a40522d2996a) @@ -0,0 +1,48 @@ +/* + * Copyright (c) 2003-2004 Jakub Jermar + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * - Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * - Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * - The name of the author may not be used to endorse or promote products + * derived from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR + * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES + * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. + * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT + * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF + * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +/** @addtogroup mips64proc + * @{ + */ +/** @file + */ + +#ifndef KERN_mips64_THREAD_H_ +#define KERN_mips64_THREAD_H_ + +typedef struct { +} thread_arch_t; + +#define thr_constructor_arch(thread) +#define thr_destructor_arch(thread) +#define thread_create_arch(thread) + +#endif + +/** @} + */ Index: kernel/arch/mips64/include/smp/dorder.h =================================================================== --- kernel/arch/mips64/include/smp/dorder.h (revision 6a44ee4a35beb95618457c456010a40522d2996a) +++ kernel/arch/mips64/include/smp/dorder.h (revision 6a44ee4a35beb95618457c456010a40522d2996a) @@ -0,0 +1,46 @@ +/* + * Copyright (c) 2007 Martin Decky + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * - Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * - Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * - The name of the author may not be used to endorse or promote products + * derived from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR + * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES + * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. + * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT + * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF + * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +/** @addtogroup mips64 + * @{ + */ +/** @file + */ + +#ifndef KERN_mips64_DORDER_H_ +#define KERN_mips64_DORDER_H_ + +#include + +extern uint32_t dorder_cpuid(void); +extern void dorder_ipi_ack(uint32_t); + +#endif + +/** @} + */ Index: kernel/arch/mips64/include/stack.h =================================================================== --- kernel/arch/mips64/include/stack.h (revision 6a44ee4a35beb95618457c456010a40522d2996a) +++ kernel/arch/mips64/include/stack.h (revision 6a44ee4a35beb95618457c456010a40522d2996a) @@ -0,0 +1,44 @@ +/* + * Copyright (c) 2006 Josef Cejka + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * - Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * - Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * - The name of the author may not be used to endorse or promote products + * derived from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR + * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES + * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. + * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT + * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF + * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +/** @addtogroup mips64 + * @{ + */ +/** @file + */ + +#ifndef KERN_mips64_STACK_H_ +#define KERN_mips64_STACK_H_ + +#define STACK_ITEM_SIZE 8 +#define STACK_ALIGNMENT 8 + +#endif + +/** @} + */ Index: kernel/arch/mips64/include/types.h =================================================================== --- kernel/arch/mips64/include/types.h (revision 6a44ee4a35beb95618457c456010a40522d2996a) +++ kernel/arch/mips64/include/types.h (revision 6a44ee4a35beb95618457c456010a40522d2996a) @@ -0,0 +1,64 @@ +/* + * Copyright (c) 2003-2004 Jakub Jermar + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * - Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * - Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * - The name of the author may not be used to endorse or promote products + * derived from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR + * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES + * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. + * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT + * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF + * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +/** @addtogroup mips64 + * @{ + */ +/** @file + */ + +#ifndef KERN_mips64_TYPES_H_ +#define KERN_mips64_TYPES_H_ + +typedef uint64_t size_t; +typedef int64_t ssize_t; + +typedef uint64_t uintptr_t; +typedef uint64_t pfn_t; + +typedef uint64_t ipl_t; + +typedef uint64_t sysarg_t; +typedef int64_t native_t; +typedef uint64_t atomic_count_t; + +typedef struct { +} fncptr_t; + +#define INTN_C(c) INT64_C(c) +#define UINTN_C(c) UINT64_C(c) + +#define PRIdn PRId64 /**< Format for native_t. */ +#define PRIun PRIu64 /**< Format for sysarg_t. */ +#define PRIxn PRIx64 /**< Format for hexadecimal sysarg_t. */ +#define PRIua PRIu64 /**< Format for atomic_count_t. */ + +#endif + +/** @} + */ Index: kernel/arch/mips64/src/asm.S =================================================================== --- kernel/arch/mips64/src/asm.S (revision 6a44ee4a35beb95618457c456010a40522d2996a) +++ kernel/arch/mips64/src/asm.S (revision 6a44ee4a35beb95618457c456010a40522d2996a) @@ -0,0 +1,301 @@ +/* + * Copyright (c) 2003 Jakub Jermar + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * - Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * - Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * - The name of the author may not be used to endorse or promote products + * derived from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR + * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES + * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. + * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT + * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF + * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +#include + +.text + +.macro cp0_read reg + dmfc0 $2, \reg + j $31 + nop +.endm + +.macro cp0_write reg + dmtc0 $4, \reg + j $31 + nop +.endm + +.set noat +.set noreorder +.set nomacro + +.global asm_delay_loop +asm_delay_loop: + j $31 + nop + +.global cpu_halt +cpu_halt: + j cpu_halt + nop + +.global memcpy_from_uspace +.global memcpy_to_uspace +.global memcpy_from_uspace_failover_address +.global memcpy_to_uspace_failover_address +memcpy_from_uspace: +memcpy_to_uspace: + move $t2, $a0 /* save dst */ + + addiu $v0, $a1, 3 + li $v1, -4 /* 0xfffffffffffffffc */ + and $v0, $v0, $v1 + beq $a1, $v0, 3f + move $t0, $a0 + + 0: + beq $a2, $zero, 2f + move $a3, $zero + + 1: + addu $v0, $a1, $a3 + lbu $a0, 0($v0) + addu $v1, $t0, $a3 + addiu $a3, $a3, 1 + bne $a3, $a2, 1b + sb $a0, 0($v1) + + 2: + jr $ra + move $v0, $t2 + + 3: + addiu $v0, $a0, 3 + and $v0, $v0, $v1 + bne $a0, $v0, 0b + srl $t1, $a2, 2 + + beq $t1, $zero, 5f + move $a3, $zero + + move $a3, $zero + move $a0, $zero + + 4: + addu $v0, $a1, $a0 + lw $v1, 0($v0) + addiu $a3, $a3, 1 + addu $v0, $t0, $a0 + sw $v1, 0($v0) + bne $a3, $t1, 4b + addiu $a0, $a0, 4 + + 5: + andi $a2, $a2, 0x3 + beq $a2, $zero, 2b + nop + + sll $v0, $a3, 2 + addu $t1, $v0, $t0 + move $a3, $zero + addu $t0, $v0, $a1 + + 6: + addu $v0, $t0, $a3 + lbu $a0, 0($v0) + addu $v1, $t1, $a3 + addiu $a3, $a3, 1 + bne $a3, $a2, 6b + sb $a0, 0($v1) + + jr $ra + move $v0, $t2 + +memcpy_from_uspace_failover_address: +memcpy_to_uspace_failover_address: + jr $ra + move $v0, $zero + +.macro fpu_gp_save reg ctx + mfc1 $t0, $\reg + sw $t0, \reg * 4(\ctx) +.endm + +.macro fpu_gp_restore reg ctx + lw $t0, \reg * 4(\ctx) + mtc1 $t0, $\reg +.endm + +.macro fpu_ct_save reg ctx + cfc1 $t0, $1 + sw $t0, (\reg + 32) * 4(\ctx) +.endm + +.macro fpu_ct_restore reg ctx + lw $t0, (\reg + 32) * 4(\ctx) + ctc1 $t0, $\reg +.endm + +.global fpu_context_save +fpu_context_save: +#ifdef CONFIG_FPU + fpu_gp_save 0, $a0 + fpu_gp_save 1, $a0 + fpu_gp_save 2, $a0 + fpu_gp_save 3, $a0 + fpu_gp_save 4, $a0 + fpu_gp_save 5, $a0 + fpu_gp_save 6, $a0 + fpu_gp_save 7, $a0 + fpu_gp_save 8, $a0 + fpu_gp_save 9, $a0 + fpu_gp_save 10, $a0 + fpu_gp_save 11, $a0 + fpu_gp_save 12, $a0 + fpu_gp_save 13, $a0 + fpu_gp_save 14, $a0 + fpu_gp_save 15, $a0 + fpu_gp_save 16, $a0 + fpu_gp_save 17, $a0 + fpu_gp_save 18, $a0 + fpu_gp_save 19, $a0 + fpu_gp_save 20, $a0 + fpu_gp_save 21, $a0 + fpu_gp_save 22, $a0 + fpu_gp_save 23, $a0 + fpu_gp_save 24, $a0 + fpu_gp_save 25, $a0 + fpu_gp_save 26, $a0 + fpu_gp_save 27, $a0 + fpu_gp_save 28, $a0 + fpu_gp_save 29, $a0 + fpu_gp_save 30, $a0 + fpu_gp_save 31, $a0 + + fpu_ct_save 1, $a0 + fpu_ct_save 2, $a0 + fpu_ct_save 3, $a0 + fpu_ct_save 4, $a0 + fpu_ct_save 5, $a0 + fpu_ct_save 6, $a0 + fpu_ct_save 7, $a0 + fpu_ct_save 8, $a0 + fpu_ct_save 9, $a0 + fpu_ct_save 10, $a0 + fpu_ct_save 11, $a0 + fpu_ct_save 12, $a0 + fpu_ct_save 13, $a0 + fpu_ct_save 14, $a0 + fpu_ct_save 15, $a0 + fpu_ct_save 16, $a0 + fpu_ct_save 17, $a0 + fpu_ct_save 18, $a0 + fpu_ct_save 19, $a0 + fpu_ct_save 20, $a0 + fpu_ct_save 21, $a0 + fpu_ct_save 22, $a0 + fpu_ct_save 23, $a0 + fpu_ct_save 24, $a0 + fpu_ct_save 25, $a0 + fpu_ct_save 26, $a0 + fpu_ct_save 27, $a0 + fpu_ct_save 28, $a0 + fpu_ct_save 29, $a0 + fpu_ct_save 30, $a0 + fpu_ct_save 31, $a0 +#endif + j $ra + nop + +.global fpu_context_restore +fpu_context_restore: +#ifdef CONFIG_FPU + fpu_gp_restore 0, $a0 + fpu_gp_restore 1, $a0 + fpu_gp_restore 2, $a0 + fpu_gp_restore 3, $a0 + fpu_gp_restore 4, $a0 + fpu_gp_restore 5, $a0 + fpu_gp_restore 6, $a0 + fpu_gp_restore 7, $a0 + fpu_gp_restore 8, $a0 + fpu_gp_restore 9, $a0 + fpu_gp_restore 10, $a0 + fpu_gp_restore 11, $a0 + fpu_gp_restore 12, $a0 + fpu_gp_restore 13, $a0 + fpu_gp_restore 14, $a0 + fpu_gp_restore 15, $a0 + fpu_gp_restore 16, $a0 + fpu_gp_restore 17, $a0 + fpu_gp_restore 18, $a0 + fpu_gp_restore 19, $a0 + fpu_gp_restore 20, $a0 + fpu_gp_restore 21, $a0 + fpu_gp_restore 22, $a0 + fpu_gp_restore 23, $a0 + fpu_gp_restore 24, $a0 + fpu_gp_restore 25, $a0 + fpu_gp_restore 26, $a0 + fpu_gp_restore 27, $a0 + fpu_gp_restore 28, $a0 + fpu_gp_restore 29, $a0 + fpu_gp_restore 30, $a0 + fpu_gp_restore 31, $a0 + + fpu_ct_restore 1, $a0 + fpu_ct_restore 2, $a0 + fpu_ct_restore 3, $a0 + fpu_ct_restore 4, $a0 + fpu_ct_restore 5, $a0 + fpu_ct_restore 6, $a0 + fpu_ct_restore 7, $a0 + fpu_ct_restore 8, $a0 + fpu_ct_restore 9, $a0 + fpu_ct_restore 10, $a0 + fpu_ct_restore 11, $a0 + fpu_ct_restore 12, $a0 + fpu_ct_restore 13, $a0 + fpu_ct_restore 14, $a0 + fpu_ct_restore 15, $a0 + fpu_ct_restore 16, $a0 + fpu_ct_restore 17, $a0 + fpu_ct_restore 18, $a0 + fpu_ct_restore 19, $a0 + fpu_ct_restore 20, $a0 + fpu_ct_restore 21, $a0 + fpu_ct_restore 22, $a0 + fpu_ct_restore 23, $a0 + fpu_ct_restore 24, $a0 + fpu_ct_restore 25, $a0 + fpu_ct_restore 26, $a0 + fpu_ct_restore 27, $a0 + fpu_ct_restore 28, $a0 + fpu_ct_restore 29, $a0 + fpu_ct_restore 30, $a0 + fpu_ct_restore 31, $a0 +#endif + j $ra + nop + +.global early_putchar +early_putchar: + j $ra + nop Index: kernel/arch/mips64/src/cache.c =================================================================== --- kernel/arch/mips64/src/cache.c (revision 6a44ee4a35beb95618457c456010a40522d2996a) +++ kernel/arch/mips64/src/cache.c (revision 6a44ee4a35beb95618457c456010a40522d2996a) @@ -0,0 +1,1 @@ +../../mips32/src/cache.c Index: kernel/arch/mips64/src/context.S =================================================================== --- kernel/arch/mips64/src/context.S (revision 6a44ee4a35beb95618457c456010a40522d2996a) +++ kernel/arch/mips64/src/context.S (revision 6a44ee4a35beb95618457c456010a40522d2996a) @@ -0,0 +1,1 @@ +../../mips32/src/context.S Index: kernel/arch/mips64/src/cpu =================================================================== --- kernel/arch/mips64/src/cpu (revision 6a44ee4a35beb95618457c456010a40522d2996a) +++ kernel/arch/mips64/src/cpu (revision 6a44ee4a35beb95618457c456010a40522d2996a) @@ -0,0 +1,1 @@ +../../mips32/src/cpu Index: kernel/arch/mips64/src/ddi =================================================================== --- kernel/arch/mips64/src/ddi (revision 6a44ee4a35beb95618457c456010a40522d2996a) +++ kernel/arch/mips64/src/ddi (revision 6a44ee4a35beb95618457c456010a40522d2996a) @@ -0,0 +1,1 @@ +../../mips32/src/ddi Index: kernel/arch/mips64/src/debug =================================================================== --- kernel/arch/mips64/src/debug (revision 6a44ee4a35beb95618457c456010a40522d2996a) +++ kernel/arch/mips64/src/debug (revision 6a44ee4a35beb95618457c456010a40522d2996a) @@ -0,0 +1,1 @@ +../../mips32/src/debug Index: kernel/arch/mips64/src/debugger.c =================================================================== --- kernel/arch/mips64/src/debugger.c (revision 6a44ee4a35beb95618457c456010a40522d2996a) +++ kernel/arch/mips64/src/debugger.c (revision 6a44ee4a35beb95618457c456010a40522d2996a) @@ -0,0 +1,1 @@ +../../mips32/src/debugger.c Index: kernel/arch/mips64/src/exception.c =================================================================== --- kernel/arch/mips64/src/exception.c (revision 6a44ee4a35beb95618457c456010a40522d2996a) +++ kernel/arch/mips64/src/exception.c (revision 6a44ee4a35beb95618457c456010a40522d2996a) @@ -0,0 +1,231 @@ +/* + * Copyright (c) 2003-2004 Jakub Jermar + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * - Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * - Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * - The name of the author may not be used to endorse or promote products + * derived from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR + * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES + * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. + * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT + * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF + * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +/** @addtogroup mips64 + * @{ + */ +/** @file + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +static const char *exctable[] = { + "Interrupt", + "TLB Modified", + "TLB Invalid", + "TLB Invalid Store", + "Address Error - load/instr. fetch", + "Address Error - store", + "Bus Error - fetch instruction", + "Bus Error - data reference", + "Syscall", + "BreakPoint", + "Reserved Instruction", + "Coprocessor Unusable", + "Arithmetic Overflow", + "Trap", + "Virtual Coherency - instruction", + "Floating Point", + NULL, NULL, NULL, NULL, NULL, NULL, NULL, + "WatchHi/WatchLo", /* 23 */ + NULL, NULL, NULL, NULL, NULL, NULL, NULL, + "Virtual Coherency - data", +}; + +void istate_decode(istate_t *istate) +{ + printf("epc=%#018" PRIx64 "\tsta=%#018" PRIx64 "\t" + "lo =%#018" PRIx64 "\thi =%#018" PRIx64 "\n", + istate->epc, istate->status, istate->lo, istate->hi); + + printf("a0 =%#018" PRIx64 "\ta1 =%#018" PRIx64 "\t" + "a2 =%#018" PRIx64 "\ta3 =%#018" PRIx64 "\n", + istate->a0, istate->a1, istate->a2, istate->a3); + + printf("t0 =%#018" PRIx64 "\tt1 =%#018" PRIx64 "\t" + "t2 =%#018" PRIx64 "\tt3 =%#018" PRIx64 "\n", + istate->t0, istate->t1, istate->t2, istate->t3); + + printf("t4 =%#018" PRIx64 "\tt5 =%#018" PRIx64 "\t" + "t6 =%#018" PRIx64 "\tt7 =%#018" PRIx64 "\n", + istate->t4, istate->t5, istate->t6, istate->t7); + + printf("t8 =%#018" PRIx64 "\tt9 =%#018" PRIx64 "\t" + "v0 =%#018" PRIx64 "\tv1 =%#018" PRIx64 "\n", + istate->t8, istate->t9, istate->v0, istate->v1); + + printf("s0 =%#018" PRIx64 "\ts1 =%#018" PRIx64 "\t" + "s2 =%#018" PRIx64 "\ts3 =%#018" PRIx64 "\n", + istate->s0, istate->s1, istate->s2, istate->s3); + + printf("s4 =%#018" PRIx64 "\ts5 =%#018" PRIx64 "\t" + "s6 =%#018" PRIx64 "\ts7 =%#018" PRIx64 "\n", + istate->s4, istate->s5, istate->s6, istate->s7); + + printf("s8 =%#018" PRIx64 "\tat =%#018" PRIx64 "\t" + "kt0=%#018" PRIx64 "\tkt1=%#018" PRIx64 "\n", + istate->s8, istate->at, istate->kt0, istate->kt1); + + printf("sp =%#018" PRIx64 "\tra =%#018" PRIx64 "\t" + "gp =%#018" PRIx64 "\n", + istate->sp, istate->ra, istate->gp); +} + +static void unhandled_exception(unsigned int n, istate_t *istate) +{ + fault_if_from_uspace(istate, "Unhandled exception %s.", exctable[n]); + panic_badtrap(istate, n, "Unhandled exception %s.", exctable[n]); +} + +static void reserved_instr_exception(unsigned int n, istate_t *istate) +{ + if (*((uint32_t *) istate->epc) == 0x7c03e83b) { + ASSERT(THREAD); + istate->epc += 4; + istate->v1 = istate->kt1; + } else + unhandled_exception(n, istate); +} + +static void breakpoint_exception(unsigned int n, istate_t *istate) +{ +#ifdef CONFIG_DEBUG + debugger_bpoint(istate); +#else + /* it is necessary to not re-execute BREAK instruction after + returning from Exception handler + (see page 138 in R4000 Manual for more information) */ + istate->epc += 4; +#endif +} + +static void tlbmod_exception(unsigned int n, istate_t *istate) +{ + tlb_modified(istate); +} + +static void tlbinv_exception(unsigned int n, istate_t *istate) +{ + tlb_invalid(istate); +} + +#ifdef CONFIG_FPU_LAZY +static void cpuns_exception(unsigned int n, istate_t *istate) +{ + if (cp0_cause_coperr(cp0_cause_read()) == fpu_cop_id) + scheduler_fpu_lazy_request(); + else { + fault_if_from_uspace(istate, + "Unhandled Coprocessor Unusable Exception."); + panic_badtrap(istate, n, + "Unhandled Coprocessor Unusable Exception."); + } +} +#endif + +static void interrupt_exception(unsigned int n, istate_t *istate) +{ + /* Decode interrupt number and process the interrupt */ + uint32_t cause = (cp0_cause_read() >> 8) & 0xff; + + unsigned int i; + for (i = 0; i < 8; i++) { + if (cause & (1 << i)) { + irq_t *irq = irq_dispatch_and_lock(i); + if (irq) { + /* + * The IRQ handler was found. + */ + irq->handler(irq); + irq_spinlock_unlock(&irq->lock, false); + } else { + /* + * Spurious interrupt. + */ +#ifdef CONFIG_DEBUG + printf("cpu%u: spurious interrupt (inum=%u)\n", + CPU->id, i); +#endif + } + } + } +} + +/** Handle syscall userspace call */ +static void syscall_exception(unsigned int n, istate_t *istate) +{ + fault_if_from_uspace(istate, "Syscall is handled through shortcut."); +} + +void exception_init(void) +{ + unsigned int i; + + /* Clear exception table */ + for (i = 0; i < IVT_ITEMS; i++) + exc_register(i, "undef", false, + (iroutine_t) unhandled_exception); + + exc_register(EXC_Bp, "bkpoint", true, + (iroutine_t) breakpoint_exception); + exc_register(EXC_RI, "resinstr", true, + (iroutine_t) reserved_instr_exception); + exc_register(EXC_Mod, "tlb_mod", true, + (iroutine_t) tlbmod_exception); + exc_register(EXC_TLBL, "tlbinvl", true, + (iroutine_t) tlbinv_exception); + exc_register(EXC_TLBS, "tlbinvl", true, + (iroutine_t) tlbinv_exception); + exc_register(EXC_Int, "interrupt", true, + (iroutine_t) interrupt_exception); + +#ifdef CONFIG_FPU_LAZY + exc_register(EXC_CpU, "cpunus", true, + (iroutine_t) cpuns_exception); +#endif + + exc_register(EXC_Sys, "syscall", true, + (iroutine_t) syscall_exception); +} + +/** @} + */ Index: kernel/arch/mips64/src/fpu_context.c =================================================================== --- kernel/arch/mips64/src/fpu_context.c (revision 6a44ee4a35beb95618457c456010a40522d2996a) +++ kernel/arch/mips64/src/fpu_context.c (revision 6a44ee4a35beb95618457c456010a40522d2996a) @@ -0,0 +1,1 @@ +../../mips32/src/fpu_context.c Index: kernel/arch/mips64/src/interrupt.c =================================================================== --- kernel/arch/mips64/src/interrupt.c (revision 6a44ee4a35beb95618457c456010a40522d2996a) +++ kernel/arch/mips64/src/interrupt.c (revision 6a44ee4a35beb95618457c456010a40522d2996a) @@ -0,0 +1,189 @@ +/* + * Copyright (c) 2003-2004 Jakub Jermar + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * - Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * - Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * - The name of the author may not be used to endorse or promote products + * derived from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR + * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES + * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. + * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT + * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF + * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +/** @addtogroup mips64 + * @{ + */ +/** @file + */ + +#include +#include +#include +#include +#include +#include +#include