Changeset 6a27d63 in mainline for arch/ia32/src

Timestamp:

2005-05-11T21:53:09Z (21 years ago)

Author:

Jakub Vana <jakub.vana@…>

Branches:

lfn, master, serial, ticket/834-toolchain-update, topic/msim-upgrade, topic/simplify-dev-export

Children:

c884ef1

Parents:

6ba143d

Message:

Finished FPU lazy context switching - first version. I have not tested it and there are many things which must be changed when
it runs first time OK.

Location:

arch/ia32/src

Files:

• fpu_context.c (modified) (2 diffs)
• interrupt.c (modified) (1 diff)
• pm.c (modified) (1 diff)

arch/ia32/src/fpu_context.c

@@ -41 +41 @@
 void fpu_context_restore(fpu_context_t *fctx)
 {
-        if(THREAD==CPU->arch.fpu_owner) reset_TS_flag();
-        else set_TS_flag();
+        if(THREAD==CPU->arch.fpu_owner) {reset_TS_flag(); }
+        else {set_TS_flag(); ((CPU->arch).fpu_owner)->fpu_context_engaged=1;}
 }
 
@@ -48 +48 @@
 void fpu_lazy_context_save(fpu_context_t *fctx)
 {
-/*
-        pushl %eax
-        mov 8(%esp),%eax
-        fxsave (%eax)
-        popl %eax
-        ret
-*/      
+    asm(
+        "mov %0,%%eax;"
+        "fxsave (%%eax);"
+        "ret;"
+        :"=m"(fctx)
+        :
+        :"%eax"
+    );  
 }
 
 void fpu_lazy_context_restore(fpu_context_t *fctx)
 {
-/*
-        pushl %eax
-        mov 8(%esp),%eax
-        fxrstor (%eax)
-        popl %eax
-        ret
-*/      
+    asm(
+        "mov %0,%%eax;"
+        "fxrstor (%%eax);"
+        "ret;"
+        :"=m"(fctx)
+        :
+        :"%eax"
+    );
 }
+
+void fpu_init(void)
+{
+    asm(
+        "fninit;"
+    );
+}
+

arch/ia32/src/interrupt.c

@@ -86 +86 @@
 }
 
+void nm_fault(__u8 n, __u32 stack[])
+{
+
+        if (((CPU->arch).fpu_owner)!=NULL) 
+        {  
+                fpu_lazy_context_save(&(((CPU->arch).fpu_owner)->saved_fpu_context));
+                ((CPU->arch).fpu_owner)->fpu_context_engaged=0; /* Enables migration */
+        }
+        
+        if(THREAD->fpu_context_exists) fpu_lazy_context_restore(&(THREAD->saved_fpu_context));
+        else {fpu_init();THREAD->fpu_context_exists=1;}
+
+        (CPU->arch).fpu_owner=THREAD;
+
+        reset_TS_flag();
+        
+//      panic("#NM fault\n");
+}
+
+
+
 void page_fault(__u8 n, __u32 stack[])
 {

arch/ia32/src/pm.c

@@ -121 +121 @@
         }
         trap_register(13, gp_fault);
+        trap_register( 7, nm_fault);
 }