Index: kernel/genarch/src/drivers/s3c24xx_uart/s3c24xx_uart.c
===================================================================
--- kernel/genarch/src/drivers/s3c24xx_uart/s3c24xx_uart.c	(revision 277cf603dc7f8b395b1770675edbc7d85cb2c6c5)
+++ kernel/genarch/src/drivers/s3c24xx_uart/s3c24xx_uart.c	(revision 69a60c4719c00c65754e37637d85664db3fa149f)
@@ -51,4 +51,8 @@
 #define S3C24XX_UTRSTAT_RDATA		0x1
 
+#define S3C24XX_UFSTAT_TX_FULL		0x4000
+#define S3C24XX_UFSTAT_RX_FULL		0x0040
+#define S3C24XX_UFSTAT_RX_COUNT		0x002f
+
 static void s3c24xx_uart_sendb(outdev_t *dev, uint8_t byte)
 {
@@ -56,6 +60,6 @@
 	    (s3c24xx_uart_t *) dev->data;
 
-	/* Wait for transmitter to be empty. */
-	while ((pio_read_32(&uart->io->utrstat) & S3C24XX_UTRSTAT_TX_EMPTY) == 0)
+	/* Wait for space becoming available in Tx FIFO. */
+	while ((pio_read_32(&uart->io->ufstat) & S3C24XX_UFSTAT_TX_FULL) != 0)
 		;
 
@@ -85,6 +89,7 @@
 	s3c24xx_uart_t *uart = irq->instance;
 
-	if ((pio_read_32(&uart->io->utrstat) & S3C24XX_UTRSTAT_RDATA) != 0) {
+	while ((pio_read_32(&uart->io->ufstat) & S3C24XX_UFSTAT_RX_COUNT) != 0) {
 		uint32_t data = pio_read_32(&uart->io->urxh);
+		pio_read_32(&uart->io->uerstat);
 		indev_push_character(uart->indev, data & 0xff);
 	}
@@ -123,7 +128,6 @@
 	uart->irq.instance = uart;
 
-	/* Disable FIFO */
-	pio_write_32(&uart->io->ufcon,
-	    pio_read_32(&uart->io->ufcon) & ~0x01);
+	/* Enable FIFO, Tx trigger level: empty, Rx trigger level: 1 byte. */
+	pio_write_32(&uart->io->ufcon, 0x01);
 
 	/* Set RX interrupt to pulse mode */