Index: kernel/arch/arm32/src/mach/integratorcp/integratorcp.c
===================================================================
--- kernel/arch/arm32/src/mach/integratorcp/integratorcp.c	(revision 0a4e1c77c74b5ead21db7cd9a738ffaacc357307)
+++ kernel/arch/arm32/src/mach/integratorcp/integratorcp.c	(revision 69a13a460047efaa83ac475840ee5fc01319cb5e)
@@ -38,5 +38,7 @@
 #include <console/chardev.h>
 #include <genarch/drivers/pl050/pl050.h>
+#include <genarch/drivers/arm926_uart/arm926_uart.h>
 #include <genarch/kbrd/kbrd.h>
+#include <genarch/srln/srln.h>
 #include <console/console.h>
 #include <sysinfo/sysinfo.h>
@@ -53,7 +55,15 @@
 #include <print.h>
 
+
 #define SDRAM_SIZE	(sdram[((*(uint32_t *)(ICP_CMCR+ICP_SDRAMCR_OFFSET) & ICP_SDRAM_MASK) >> 2)])
-static icp_hw_map_t icp_hw_map;
-static irq_t icp_timer_irq;
+
+static struct {
+	icp_hw_map_t hw_map;
+	irq_t timer_irq;
+	arm926_uart_t uart;
+} icp;
+
+
+
 struct arm_machine_ops icp_machine_ops = {
 	icp_init,
@@ -88,12 +98,12 @@
 void icp_vga_init(void)
 {
-	*(uint32_t*)((char *)(icp_hw_map.cmcr)+0x14) = 0xA05F0000;
-	*(uint32_t*)((char *)(icp_hw_map.cmcr)+0x1C) = 0x12C11000;
-	*(uint32_t*)icp_hw_map.vga = 0x3F1F3F9C;
-	*(uint32_t*)((char *)(icp_hw_map.vga) + 0x4) = 0x080B61DF;
-	*(uint32_t*)((char *)(icp_hw_map.vga) + 0x8) = 0x067F3800;
-	*(uint32_t*)((char *)(icp_hw_map.vga) + 0x10) = ICP_FB;
-	*(uint32_t *)((char *)(icp_hw_map.vga) + 0x1C) = 0x182B;
-	*(uint32_t*)((char *)(icp_hw_map.cmcr)+0xC) = 0x33805000;
+	*(uint32_t*)((char *)(icp.hw_map.cmcr)+0x14) = 0xA05F0000;
+	*(uint32_t*)((char *)(icp.hw_map.cmcr)+0x1C) = 0x12C11000;
+	*(uint32_t*)icp.hw_map.vga = 0x3F1F3F9C;
+	*(uint32_t*)((char *)(icp.hw_map.vga) + 0x4) = 0x080B61DF;
+	*(uint32_t*)((char *)(icp.hw_map.vga) + 0x8) = 0x067F3800;
+	*(uint32_t*)((char *)(icp.hw_map.vga) + 0x10) = ICP_FB;
+	*(uint32_t *)((char *)(icp.hw_map.vga) + 0x1C) = 0x182B;
+	*(uint32_t*)((char *)(icp.hw_map.cmcr)+0xC) = 0x33805000;
 	
 }
@@ -102,5 +112,5 @@
 static inline uint32_t icp_irqc_get_sources(void)
 {
-	return *((uint32_t *) icp_hw_map.irqc);
+	return *((uint32_t *) icp.hw_map.irqc);
 }
 
@@ -112,5 +122,5 @@
 static inline void icp_irqc_mask(uint32_t irq)
 {
-	*((uint32_t *) icp_hw_map.irqc_mask) = (1 << irq);
+	*((uint32_t *) icp.hw_map.irqc_mask) = (1 << irq);
 }
 
@@ -122,33 +132,33 @@
 static inline void icp_irqc_unmask(uint32_t irq)
 {
-	*((uint32_t *) icp_hw_map.irqc_unmask) |= (1 << irq);
-}
-
-/** Initializes icp_hw_map. */
+	*((uint32_t *) icp.hw_map.irqc_unmask) |= (1 << irq);
+}
+
+/** Initializes icp.hw_map. */
 void icp_init(void)
 {
-	icp_hw_map.uart = km_map(ICP_UART, PAGE_SIZE,
-	    PAGE_WRITE | PAGE_NOT_CACHEABLE);
-	icp_hw_map.kbd_ctrl = km_map(ICP_KBD, PAGE_SIZE, PAGE_NOT_CACHEABLE);
-	icp_hw_map.kbd_stat = icp_hw_map.kbd_ctrl + ICP_KBD_STAT;
-	icp_hw_map.kbd_data = icp_hw_map.kbd_ctrl + ICP_KBD_DATA;
-	icp_hw_map.kbd_intstat = icp_hw_map.kbd_ctrl + ICP_KBD_INTR_STAT;
-	icp_hw_map.rtc = km_map(ICP_RTC, PAGE_SIZE,
-	    PAGE_WRITE | PAGE_NOT_CACHEABLE);
-	icp_hw_map.rtc1_load = icp_hw_map.rtc + ICP_RTC1_LOAD_OFFSET;
-	icp_hw_map.rtc1_read = icp_hw_map.rtc + ICP_RTC1_READ_OFFSET;
-	icp_hw_map.rtc1_ctl = icp_hw_map.rtc + ICP_RTC1_CTL_OFFSET;
-	icp_hw_map.rtc1_intrclr = icp_hw_map.rtc + ICP_RTC1_INTRCLR_OFFSET;
-	icp_hw_map.rtc1_bgload = icp_hw_map.rtc + ICP_RTC1_BGLOAD_OFFSET;
-	icp_hw_map.rtc1_intrstat = icp_hw_map.rtc + ICP_RTC1_INTRSTAT_OFFSET;
-
-	icp_hw_map.irqc = km_map(ICP_IRQC, PAGE_SIZE,
-	    PAGE_WRITE | PAGE_NOT_CACHEABLE);
-	icp_hw_map.irqc_mask = icp_hw_map.irqc + ICP_IRQC_MASK_OFFSET;
-	icp_hw_map.irqc_unmask = icp_hw_map.irqc + ICP_IRQC_UNMASK_OFFSET;
-	icp_hw_map.cmcr = km_map(ICP_CMCR, PAGE_SIZE,
-	    PAGE_WRITE | PAGE_NOT_CACHEABLE);
-	icp_hw_map.sdramcr = icp_hw_map.cmcr + ICP_SDRAMCR_OFFSET;
-	icp_hw_map.vga = km_map(ICP_VGA, PAGE_SIZE,
+	icp.hw_map.uart = km_map(ICP_UART, PAGE_SIZE,
+	    PAGE_WRITE | PAGE_NOT_CACHEABLE);
+	icp.hw_map.kbd_ctrl = km_map(ICP_KBD, PAGE_SIZE, PAGE_NOT_CACHEABLE);
+	icp.hw_map.kbd_stat = icp.hw_map.kbd_ctrl + ICP_KBD_STAT;
+	icp.hw_map.kbd_data = icp.hw_map.kbd_ctrl + ICP_KBD_DATA;
+	icp.hw_map.kbd_intstat = icp.hw_map.kbd_ctrl + ICP_KBD_INTR_STAT;
+	icp.hw_map.rtc = km_map(ICP_RTC, PAGE_SIZE,
+	    PAGE_WRITE | PAGE_NOT_CACHEABLE);
+	icp.hw_map.rtc1_load = icp.hw_map.rtc + ICP_RTC1_LOAD_OFFSET;
+	icp.hw_map.rtc1_read = icp.hw_map.rtc + ICP_RTC1_READ_OFFSET;
+	icp.hw_map.rtc1_ctl = icp.hw_map.rtc + ICP_RTC1_CTL_OFFSET;
+	icp.hw_map.rtc1_intrclr = icp.hw_map.rtc + ICP_RTC1_INTRCLR_OFFSET;
+	icp.hw_map.rtc1_bgload = icp.hw_map.rtc + ICP_RTC1_BGLOAD_OFFSET;
+	icp.hw_map.rtc1_intrstat = icp.hw_map.rtc + ICP_RTC1_INTRSTAT_OFFSET;
+
+	icp.hw_map.irqc = km_map(ICP_IRQC, PAGE_SIZE,
+	    PAGE_WRITE | PAGE_NOT_CACHEABLE);
+	icp.hw_map.irqc_mask = icp.hw_map.irqc + ICP_IRQC_MASK_OFFSET;
+	icp.hw_map.irqc_unmask = icp.hw_map.irqc + ICP_IRQC_UNMASK_OFFSET;
+	icp.hw_map.cmcr = km_map(ICP_CMCR, PAGE_SIZE,
+	    PAGE_WRITE | PAGE_NOT_CACHEABLE);
+	icp.hw_map.sdramcr = icp.hw_map.cmcr + ICP_SDRAMCR_OFFSET;
+	icp.hw_map.vga = km_map(ICP_VGA, PAGE_SIZE,
 	    PAGE_WRITE | PAGE_NOT_CACHEABLE);
 
@@ -163,7 +173,7 @@
 {
 	icp_irqc_mask(ICP_TIMER_IRQ);
-	*((uint32_t*) icp_hw_map.rtc1_load) = frequency;
-	*((uint32_t*) icp_hw_map.rtc1_bgload) = frequency;
-	*((uint32_t*) icp_hw_map.rtc1_ctl) = ICP_RTC_CTL_VALUE;
+	*((uint32_t*) icp.hw_map.rtc1_load) = frequency;
+	*((uint32_t*) icp.hw_map.rtc1_bgload) = frequency;
+	*((uint32_t*) icp.hw_map.rtc1_ctl) = ICP_RTC_CTL_VALUE;
 	icp_irqc_unmask(ICP_TIMER_IRQ);
 }
@@ -171,6 +181,6 @@
 static irq_ownership_t icp_timer_claim(irq_t *irq)
 {
-	if (icp_hw_map.rtc1_intrstat) {
-		*((uint32_t*) icp_hw_map.rtc1_intrclr) = 1;
+	if (icp.hw_map.rtc1_intrstat) {
+		*((uint32_t*) icp.hw_map.rtc1_intrclr) = 1;
 		return IRQ_ACCEPT;
 	} else
@@ -199,11 +209,11 @@
 static void icp_timer_irq_init(void)
 {
-	irq_initialize(&icp_timer_irq);
-	icp_timer_irq.devno = device_assign_devno();
-	icp_timer_irq.inr = ICP_TIMER_IRQ;
-	icp_timer_irq.claim = icp_timer_claim;
-	icp_timer_irq.handler = icp_timer_irq_handler;
-
-	irq_register(&icp_timer_irq);
+	irq_initialize(&icp.timer_irq);
+	icp.timer_irq.devno = device_assign_devno();
+	icp.timer_irq.inr = ICP_TIMER_IRQ;
+	icp.timer_irq.claim = icp_timer_claim;
+	icp.timer_irq.handler = icp_timer_irq_handler;
+
+	irq_register(&icp.timer_irq);
 }
 
@@ -230,5 +240,5 @@
 
 	if (hw_map_init_called) {
-		*size = (sdram[((*(uint32_t *)icp_hw_map.sdramcr &
+		*size = (sdram[((*(uint32_t *)icp.hw_map.sdramcr &
 		    ICP_SDRAM_MASK) >> 2)]);
 	} else {
@@ -304,4 +314,9 @@
 		stdout_wire(fbdev);
 #endif
+#ifdef CONFIG_ARM926_UART
+	if (arm926_uart_init(&icp.uart, ARM926_UART0_IRQ,
+	    ARM926_UART0_BASE_ADDRESS, sizeof(arm926_uart_regs_t)))
+		stdout_wire(&icp.uart.outdev);
+#endif
 }
 
@@ -310,7 +325,7 @@
 
 	pl050_t *pl050 = malloc(sizeof(pl050_t), FRAME_ATOMIC);
-	pl050->status = (ioport8_t *)icp_hw_map.kbd_stat;
-	pl050->data = (ioport8_t *)icp_hw_map.kbd_data;
-	pl050->ctrl = (ioport8_t *)icp_hw_map.kbd_ctrl;
+	pl050->status = (ioport8_t *)icp.hw_map.kbd_stat;
+	pl050->data = (ioport8_t *)icp.hw_map.kbd_data;
+	pl050->ctrl = (ioport8_t *)icp.hw_map.kbd_ctrl;
 		
 	pl050_instance_t *pl050_instance = pl050_init(pl050, ICP_KBD_IRQ);
@@ -335,4 +350,13 @@
 	    ICP_KBD);
 
+#ifdef CONFIG_ARM926_UART
+        srln_instance_t *srln_instance = srln_init();
+        if (srln_instance) {
+                indev_t *sink = stdin_wire();
+                indev_t *srln = srln_wire(srln_instance, sink);
+                arm926_uart_input_wire(&icp.uart, srln);
+		icp_irqc_unmask(ARM926_UART0_IRQ);
+        }
+#endif
 }