Index: uspace/drv/infrastructure/rootamdm37x/cm/mpu.h
===================================================================
--- uspace/drv/infrastructure/rootamdm37x/cm/mpu.h	(revision 68338c6a318f3595da7dfa16a5bc13cb9f60e907)
+++ uspace/drv/infrastructure/rootamdm37x/cm/mpu.h	(revision 68338c6a318f3595da7dfa16a5bc13cb9f60e907)
@@ -0,0 +1,97 @@
+/*
+ * Copyright (c) 2012 Jan Vesely
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *
+ * - Redistributions of source code must retain the above copyright
+ *   notice, this list of conditions and the following disclaimer.
+ * - Redistributions in binary form must reproduce the above copyright
+ *   notice, this list of conditions and the following disclaimer in the
+ *   documentation and/or other materials provided with the distribution.
+ * - The name of the author may not be used to endorse or promote products
+ *   derived from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
+ * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
+ * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
+ * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+ * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+ * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
+ * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+/** @addtogroup amdm37xdrvcm
+ * @{
+ */
+/** @file
+ * @brief MPU Clock Management IO register structure.
+ */
+#ifndef AMDM37x_MPU_CM_H
+#define AMDM37x_MPU_CM_H
+#include <sys/types.h>
+#include <macros.h>
+
+/* AM/DM37x TRM p.455 */
+#define MPU_CM_BASE_ADDRESS  0x48004900
+#define MPU_CM_SIZE  8192
+
+typedef struct {
+	PADD32;
+	ioport32_t clken_pll;
+#define MPU_CM_CLKEN_PLL_EN_MPU_DPLL_LP_MODE_FLAG   (1 << 10)
+#define MPU_CM_CLKEN_PLL_EN_MPU_DPLL_DRIFTGUARD   (1 << 3)
+#define MPU_CM_CLKEN_PLL_EN_MPU_DPLL_EN_MPU_DPLL_MASK   (0x7)
+#define MPU_CM_CLKEN_PLL_EN_MPU_DPLL_EN_MPU_DPLL_LP_BYPASS   (0x5)
+#define MPU_CM_CLKEN_PLL_EN_MPU_DPLL_EN_MPU_DPLL_LOCKED   (0x7)
+
+	PADD32[6];
+	const ioport32_t idlest;
+#define MPU_CM_IDLEST_ST_MPU_STANDBY_FLAG   (1 << 0)
+
+	const ioport32_t idlest_pll;
+#define MPU_CM_IDLEST_PLL_ST_MPU_CLK_LOCKED_FLAG   (1 << 0)
+
+	PADD32[3];
+	ioport32_t autoidle_pll;
+#define MPU_CM_AUTOIDLE_PLL_AUTO_MPU_DPLL_MASK   (0x7)
+#define MPU_CM_AUTOIDLE_PLL_AUTO_MPU_DPLL_DISABLED   (0x0)
+#define MPU_CM_AUTOIDLE_PLL_AUTO_MPU_DPLL_ENABLED   (0x1)
+
+	PADD32[2];
+	ioport32_t clksel1_pll;
+#define MPU_CM_CLKSEL1_PLL_MPU_CLK_SRC_MASK   (0x7 << 19)
+#define MPU_CM_CLKSEL1_PLL_MPU_CLK_SRC_SHIFT   (19)
+#define MPU_CM_CLKSEL1_PLL_MPU_CLK_SRC_VAL(x)   ((x >> 19) & 0x7)
+#define MPU_CM_CLKSEL1_PLL_MPU_CLK_SRC_CORE_DIV_1   (0x1 << 19)
+#define MPU_CM_CLKSEL1_PLL_MPU_CLK_SRC_CORE_DIV_2   (0x2 << 19)
+#define MPU_CM_CLKSEL1_PLL_MPU_CLK_SRC_CORE_DIV_4   (0x4 << 19)
+#define MPU_CM_CLKSEL1_PLL_MPU_DPLL_MULT_MASK   (0x7ff << 8)
+#define MPU_CM_CLKSEL1_PLL_MPU_DPLL_MULT_SHIFT   (8)
+#define MPU_CM_CLKSEL1_PLL_MPU_DPLL_DIV_MASK  (0x7f << 0)
+#define MPU_CM_CLKSEL1_PLL_MPU_DPLL_DIV_SHIFT  (0)
+
+	ioport32_t clksel2_pll;
+#define MPU_CM_CLKSEL2_PLL_MPU_DPLL_CLKOUT_DIV_MASK   (0x1f)
+
+	ioport32_t clkstctrl;
+#define MPU_CM_CLKSCTRL_CLKTRCTRL_MPU_MASK   (0x3)
+#define MPU_CM_CLKSCTRL_CLKTRCTRL_MPU_DISABLED   (0x0)
+#define MPU_CM_CLKSCTRL_CLKTRCTRL_MPU_START_WAKEUP   (0x2)
+#define MPU_CM_CLKSCTRL_CLKTRCTRL_MPU_AUTOMATIC   (0x3)
+
+	const ioport32_t clkstst;
+#define MPU_CM_CLKSTST_CLKACTIVITY_MPU_ACTICE_FLAG   (1 << 0)
+
+} mpu_cm_regs_t;
+
+#endif
+/**
+ * @}
+ */
+
Index: uspace/drv/infrastructure/rootamdm37x/rootamdm37x.c
===================================================================
--- uspace/drv/infrastructure/rootamdm37x/rootamdm37x.c	(revision 52e020b49b7182897ac36e66e3b74a28dc28e6f2)
+++ uspace/drv/infrastructure/rootamdm37x/rootamdm37x.c	(revision 68338c6a318f3595da7dfa16a5bc13cb9f60e907)
@@ -51,4 +51,5 @@
 #include "cm/clock_control.h"
 #include "cm/usbhost.h"
+#include "cm/mpu.h"
 #include "prm/clock_control.h"
 
@@ -59,4 +60,5 @@
 	tll_regs_t *tll;
 	struct {
+		mpu_cm_regs_t *mpu;
 		core_cm_regs_t *core;
 		clock_control_cm_regs_t *clocks;
@@ -94,4 +96,9 @@
 		return ret;
 
+	ret = pio_enable((void*)MPU_CM_BASE_ADDRESS,
+		    MPU_CM_SIZE, (void**)&device->cm.mpu);
+	if (ret != EOK)
+		return ret;
+
 	ret = pio_enable((void*)CLOCK_CONTROL_PRM_BASE_ADDRESS,
 	    CLOCK_CONTROL_PRM_SIZE, (void**)&device->prm.clocks);
@@ -113,4 +120,5 @@
 		pio_trace_enable(device->cm.clocks, CLOCK_CONTROL_CM_SIZE, log, (void*)CLOCK_CONTROL_CM_BASE_ADDRESS);
 		pio_trace_enable(device->cm.core, CORE_CM_SIZE, log, (void*)CORE_CM_BASE_ADDRESS);
+		pio_trace_enable(device->cm.mpu, MPU_CM_SIZE, log, (void*)MPU_CM_BASE_ADDRESS);
 		pio_trace_enable(device->cm.usbhost, USBHOST_CM_SIZE, log, (void*)USBHOST_CM_BASE_ADDRESS);
 		pio_trace_enable(device->uhh, AMDM37x_UHH_SIZE, log, (void*)AMDM37x_UHH_BASE_ADDRESS);
@@ -131,5 +139,6 @@
 {
 	assert(device);
-	/* Get SYS_CLK value, it is used as reference clock by all DPLLs */
+	/* Get SYS_CLK value, it is used as reference clock by all DPLLs,
+	 * NFI who sets this or why it is set to specific value. */
 	const unsigned base_clk = pio_read_32(&device->prm.clocks->clksel)
 	    & CLOCK_CONTROL_PRM_CLKSEL_SYS_CLKIN_MASK;
@@ -143,6 +152,50 @@
 	 * high frequency bypass (MPU then runs on L3 interconnect freq).
 	 * It should be setup by fw or u-boot.*/
-	// TODO: set to autoidle to save power.
-	// TODO: compute current MPU frequency.
+	mpu_cm_regs_t *mpu = device->cm.mpu;
+
+	/* Current MPU frequency. */
+	if (pio_read_32(&mpu->clkstst) & MPU_CM_CLKSTST_CLKACTIVITY_MPU_ACTICE_FLAG) {
+		if (pio_read_32(&mpu->idlest_pll) & MPU_CM_IDLEST_PLL_ST_MPU_CLK_LOCKED_FLAG) {
+			/* DPLL active and locked */
+			const uint32_t reg = pio_read_32(&mpu->clksel1_pll);
+			const unsigned multiplier =
+			    (reg & MPU_CM_CLKSEL1_PLL_MPU_DPLL_MULT_MASK)
+				>> MPU_CM_CLKSEL1_PLL_MPU_DPLL_MULT_SHIFT;
+			const unsigned divisor =
+			    (reg & MPU_CM_CLKSEL1_PLL_MPU_DPLL_MULT_MASK)
+				>> MPU_CM_CLKSEL1_PLL_MPU_DPLL_MULT_SHIFT;
+			const unsigned divisor2 =
+			    (pio_read_32(&mpu->clksel2_pll)
+			        & MPU_CM_CLKSEL2_PLL_MPU_DPLL_CLKOUT_DIV_MASK);
+			if (multiplier && divisor && divisor2) {
+				const unsigned freq =
+				    ((base_freq / divisor) * multiplier) / divisor2;
+				ddf_msg(LVL_NOTE, "MPU running at %d.%d MHz",
+				    freq / 1000, freq % 1000);
+			} else {
+				ddf_msg(LVL_WARN, "Frequency divisor and/or "
+				    "multiplier value invalid: %d %d %d",
+				    multiplier, divisor, divisor2);
+			}
+		} else {
+			/* DPLL in LP bypass mode */
+			const unsigned divisor =
+			    MPU_CM_CLKSEL1_PLL_MPU_CLK_SRC_VAL(
+			        pio_read_32(&mpu->clksel1_pll));
+			ddf_msg(LVL_NOTE, "MPU DPLL in bypass mode, running at"
+			    " CORE CLK / %d MHz", divisor);
+		}
+	} else {
+		ddf_msg(LVL_WARN, "MPU clock domain is not active, we should not be running...");
+	}
+	// TODO: Enable this (automatic MPU downclocking):
+#if 0
+	/* Enable low power bypass mode, this will take effect the next lock or
+	 * relock sequence. */
+	//TODO: We might need to force re-lock after enabling this
+	pio_set_32(&mpu->clken_pll, MPU_CM_CLKEN_PLL_EN_MPU_DPLL_LP_MODE_FLAG, 5);
+	/* Enable automatic relocking */
+	pio_change_32(&mpu->autoidle_pll, MPU_CM_AUTOIDLE_PLL_AUTO_MPU_DPLL_ENABLED, MPU_CM_AUTOIDLE_PLL_AUTO_MPU_DPLL_MASK, 5);
+#endif
 
 	/* DPLL2 provides IVA(video acceleration) clock.