Index: kernel/arch/arm32/src/fpu_context.c
===================================================================
--- kernel/arch/arm32/src/fpu_context.c	(revision b5a3b50c5e0e757d7f292db4541d06a2e1c042d6)
+++ kernel/arch/arm32/src/fpu_context.c	(revision 664fd6d5f9d3f54ffaa4804f8384c9a6e018bd39)
@@ -58,4 +58,12 @@
 	FPEXC_EX_FLAG = (1 << 31),
 	FPEXC_ENABLED_FLAG = (1 << 30),
+};
+
+/* See Architecture reference manual ch. B4.1.40 */
+enum {
+	CPACR_CP10_MASK = 0x3 << 20,
+	CPACR_CP11_MASK = 0x3 << 22,
+	CPACR_CP10_USER_ACCESS = CPACR_CP10_MASK,
+	CPACR_CP11_USER_ACCESS = CPACR_CP11_MASK,
 };
 
@@ -228,6 +236,38 @@
 }
 
+static int fpu_have_coprocessor_access()
+{
+	uint32_t cpacr;
+	asm volatile ("MRC p15, 0, %0, c1, c0, 2" :"=r" (cpacr)::);
+	/* FPU needs access to coprocessor 10 and 11.
+	 * Moreover they need to have same access enabledd */
+	if (((cpacr & CPACR_CP10_MASK) == CPACR_CP10_USER_ACCESS) &&
+	   ((cpacr & CPACR_CP11_MASK) == CPACR_CP11_USER_ACCESS))
+		return 1;
+
+	return 0;
+}
+
+static void fpu_enable_coprocessor_access()
+{
+	uint32_t cpacr;
+	asm volatile ("mrc p15, 0, %0, c1, c0, 2" :"=r" (cpacr)::);
+	/* FPU needs access to coprocessor 10 and 11.
+	 * Moreover, they need to have same access enabled */
+	cpacr |= CPACR_CP10_USER_ACCESS;
+	cpacr |= CPACR_CP11_USER_ACCESS;
+	asm volatile ("mcr p15, 0, %0, c1, c0, 2" :"=r" (cpacr)::);
+}
+
+
 void fpu_init(void)
 {
+	/* Enable coprocessor access*/
+	fpu_enable_coprocessor_access();
+
+	/* Check if we succeeded */
+	if (!fpu_have_coprocessor_access())
+		return;
+
 	/* Clear all fpu flags */
 	fpexc_write(0);
@@ -241,4 +281,8 @@
 void fpu_setup(void)
 {
+	/* Check if we have access */
+	if (!fpu_have_coprocessor_access())
+		return;
+
 	uint32_t fpsid = 0;
 	asm volatile (
@@ -288,4 +332,8 @@
 bool handle_if_fpu_exception(void)
 {
+	/* Check if we have access */
+	if (!fpu_have_coprocessor_access())
+		return false;
+
 	const uint32_t fpexc = fpexc_read();
 	if (fpexc & FPEXC_ENABLED_FLAG) {
@@ -305,4 +353,7 @@
 void fpu_enable(void)
 {
+	/* Check if we have access */
+	if (!fpu_have_coprocessor_access())
+		return;
 	/* Enable FPU instructions */
 	fpexc_write(fpexc_read() | FPEXC_ENABLED_FLAG);
@@ -311,4 +362,7 @@
 void fpu_disable(void)
 {
+	/* Check if we have access */
+	if (!fpu_have_coprocessor_access())
+		return;
 	/* Disable FPU instructions */
 	fpexc_write(fpexc_read() & ~FPEXC_ENABLED_FLAG);
@@ -317,4 +371,7 @@
 void fpu_context_save(fpu_context_t *ctx)
 {
+	/* Check if we have access */
+	if (!fpu_have_coprocessor_access())
+		return;
 	const uint32_t fpexc = fpexc_read();
 
@@ -329,4 +386,7 @@
 void fpu_context_restore(fpu_context_t *ctx)
 {
+	/* Check if we have access */
+	if (!fpu_have_coprocessor_access())
+		return;
 	if (restore_context)
 		restore_context(ctx);