Index: uspace/drv/pciintel/pci.c
===================================================================
--- uspace/drv/pciintel/pci.c	(revision 49698fac57de2ecd7140a9c7fd845dfa15affad5)
+++ uspace/drv/pciintel/pci.c	(revision 663f41c465b5ccd70664cc4423f19a9fe2351eee)
@@ -58,19 +58,19 @@
 #define NAME "pciintel"
 
-#define CONF_ADDR(bus, dev, fn, reg)   ((1 << 31) | (bus << 16) | (dev << 11) | (fn << 8) | (reg & ~3))
-
-
-static hw_resource_list_t * pciintel_get_child_resources(device_t *dev)
-{
-	pci_dev_data_t *dev_data = (pci_dev_data_t *)dev->driver_data;
-	if (NULL == dev_data) {
+#define CONF_ADDR(bus, dev, fn, reg) \
+	((1 << 31) | (bus << 16) | (dev << 11) | (fn << 8) | (reg & ~3))
+
+static hw_resource_list_t *pciintel_get_child_resources(device_t *dev)
+{
+	pci_dev_data_t *dev_data = (pci_dev_data_t *) dev->driver_data;
+	
+	if (NULL == dev_data)
 		return NULL;
-	}
 	return &dev_data->hw_resources;
 }
 
-static bool pciintel_enable_child_interrupt(device_t *dev) 
-{
-	// TODO
+static bool pciintel_enable_child_interrupt(device_t *dev)
+{
+	/* TODO */
 	
 	return false;
@@ -79,20 +79,17 @@
 static resource_iface_t pciintel_child_res_iface = {
 	&pciintel_get_child_resources,
-	&pciintel_enable_child_interrupt	
+	&pciintel_enable_child_interrupt
 };
 
 static device_ops_t pci_child_ops;
 
-
-static int pci_add_device(device_t *dev);
-
-/** The pci bus driver's standard operations.
- */
+static int pci_add_device(device_t *);
+
+/** The pci bus driver's standard operations. */
 static driver_ops_t pci_ops = {
 	.add_device = &pci_add_device
 };
 
-/** The pci bus driver structure. 
- */
+/** The pci bus driver structure. */
 static driver_t pci_driver = {
 	.name = NAME,
@@ -103,21 +100,23 @@
 	uint32_t conf_io_addr;
 	void *conf_data_port;
-	void *conf_addr_port;	
+	void *conf_addr_port;
 	fibril_mutex_t conf_mutex;
 } pci_bus_data_t;
 
-static inline pci_bus_data_t *create_pci_bus_data() 
-{
-	pci_bus_data_t *bus_data = (pci_bus_data_t *)malloc(sizeof(pci_bus_data_t));
-	if(NULL != bus_data) {
+static pci_bus_data_t *create_pci_bus_data(void)
+{
+	pci_bus_data_t *bus_data;
+	
+	bus_data = (pci_bus_data_t *) malloc(sizeof(pci_bus_data_t));
+	if (NULL != bus_data) {
 		memset(bus_data, 0, sizeof(pci_bus_data_t));
 		fibril_mutex_initialize(&bus_data->conf_mutex);
 	}
-	return bus_data;	
-}
-
-static inline void delete_pci_bus_data(pci_bus_data_t *bus_data) 
-{
-	free(bus_data);	
+	return bus_data;
+}
+
+static void delete_pci_bus_data(pci_bus_data_t *bus_data)
+{
+	free(bus_data);
 }
 
@@ -126,10 +125,11 @@
 	assert(NULL != dev->parent);
 	
-	pci_dev_data_t *dev_data = (pci_dev_data_t *)dev->driver_data;
-	pci_bus_data_t *bus_data = (pci_bus_data_t *)dev->parent->driver_data;
+	pci_dev_data_t *dev_data = (pci_dev_data_t *) dev->driver_data;
+	pci_bus_data_t *bus_data = (pci_bus_data_t *) dev->parent->driver_data;
 	
 	fibril_mutex_lock(&bus_data->conf_mutex);
 	
-	uint32_t conf_addr =  CONF_ADDR(dev_data->bus, dev_data->dev, dev_data->fn, reg);
+	uint32_t conf_addr;
+	conf_addr = CONF_ADDR(dev_data->bus, dev_data->dev, dev_data->fn, reg);
 	void *addr = bus_data->conf_data_port + (reg & 3);
 	
@@ -137,16 +137,16 @@
 	
 	switch (len) {
-		case 1:
-			buf[0] = pio_read_8(addr);
-			break;
-		case 2:
-			((uint16_t *)buf)[0] = pio_read_16(addr);
-			break;
-		case 4:
-			((uint32_t *)buf)[0] = pio_read_32(addr);
-			break;
-	}
-	
-	fibril_mutex_unlock(&bus_data->conf_mutex);	
+	case 1:
+		buf[0] = pio_read_8(addr);
+		break;
+	case 2:
+		((uint16_t *) buf)[0] = pio_read_16(addr);
+		break;
+	case 4:
+		((uint32_t *) buf)[0] = pio_read_32(addr);
+		break;
+	}
+	
+	fibril_mutex_unlock(&bus_data->conf_mutex);
 }
 
@@ -155,10 +155,11 @@
 	assert(NULL != dev->parent);
 	
-	pci_dev_data_t *dev_data = (pci_dev_data_t *)dev->driver_data;
-	pci_bus_data_t *bus_data = (pci_bus_data_t *)dev->parent->driver_data;
+	pci_dev_data_t *dev_data = (pci_dev_data_t *) dev->driver_data;
+	pci_bus_data_t *bus_data = (pci_bus_data_t *) dev->parent->driver_data;
 	
 	fibril_mutex_lock(&bus_data->conf_mutex);
 	
-	uint32_t conf_addr =  CONF_ADDR(dev_data->bus, dev_data->dev, dev_data->fn, reg);
+	uint32_t conf_addr;
+	conf_addr = CONF_ADDR(dev_data->bus, dev_data->dev, dev_data->fn, reg);
 	void *addr = bus_data->conf_data_port + (reg & 3);
 	
@@ -166,16 +167,16 @@
 	
 	switch (len) {
-		case 1:
-			pio_write_8(addr, buf[0]);
-			break;
-		case 2:
-			pio_write_16(addr, ((uint16_t *)buf)[0]);
-			break;
-		case 4:
-			pio_write_32(addr, ((uint32_t *)buf)[0]);
-			break;
-	}
-	
-	fibril_mutex_unlock(&bus_data->conf_mutex);	
+	case 1:
+		pio_write_8(addr, buf[0]);
+		break;
+	case 2:
+		pio_write_16(addr, ((uint16_t *) buf)[0]);
+		break;
+	case 4:
+		pio_write_32(addr, ((uint32_t *) buf)[0]);
+		break;
+	}
+	
+	fibril_mutex_unlock(&bus_data->conf_mutex);
 }
 
@@ -190,5 +191,5 @@
 {
 	uint16_t res;
-	pci_conf_read(dev, reg, (uint8_t *)&res, 2);
+	pci_conf_read(dev, reg, (uint8_t *) &res, 2);
 	return res;
 }
@@ -197,45 +198,47 @@
 {
 	uint32_t res;
-	pci_conf_read(dev, reg, (uint8_t *)&res, 4);
-	return res;	
-}
-
-void pci_conf_write_8(device_t *dev, int reg, uint8_t val) 
-{
-	pci_conf_write(dev, reg, (uint8_t *)&val, 1);	
-}
-
-void pci_conf_write_16(device_t *dev, int reg, uint16_t val) 
-{
-	pci_conf_write(dev, reg, (uint8_t *)&val, 2);	
-}
-
-void pci_conf_write_32(device_t *dev, int reg, uint32_t val) 
-{
-	pci_conf_write(dev, reg, (uint8_t *)&val, 4);	
-}
-
+	pci_conf_read(dev, reg, (uint8_t *) &res, 4);
+	return res;
+}
+
+void pci_conf_write_8(device_t *dev, int reg, uint8_t val)
+{
+	pci_conf_write(dev, reg, (uint8_t *) &val, 1);
+}
+
+void pci_conf_write_16(device_t *dev, int reg, uint16_t val)
+{
+	pci_conf_write(dev, reg, (uint8_t *) &val, 2);
+}
+
+void pci_conf_write_32(device_t *dev, int reg, uint32_t val)
+{
+	pci_conf_write(dev, reg, (uint8_t *) &val, 4);
+}
 
 void create_pci_match_ids(device_t *dev)
 {
-	pci_dev_data_t *dev_data = (pci_dev_data_t *)dev->driver_data;
-	match_id_t *match_id = NULL;	
-	char *match_id_str;	
+	pci_dev_data_t *dev_data = (pci_dev_data_t *) dev->driver_data;
+	match_id_t *match_id = NULL;
+	char *match_id_str;
+	
 	match_id = create_match_id();
 	if (NULL != match_id) {
-		asprintf(&match_id_str, "pci/ven=%04x&dev=%04x", dev_data->vendor_id, dev_data->device_id);
+		asprintf(&match_id_str, "pci/ven=%04x&dev=%04x",
+		    dev_data->vendor_id, dev_data->device_id);
 		match_id->id = match_id_str;
 		match_id->score = 90;
 		add_match_id(&dev->match_ids, match_id);
 	}	
-	// TODO add more ids (with subsys ids, using class id etc.)
-}
-
-void pci_add_range(device_t *dev, uint64_t range_addr, size_t range_size, bool io)
-{
-	pci_dev_data_t *dev_data = (pci_dev_data_t *)dev->driver_data;
+	/* TODO add more ids (with subsys ids, using class id etc.) */
+}
+
+void
+pci_add_range(device_t *dev, uint64_t range_addr, size_t range_size, bool io)
+{
+	pci_dev_data_t *dev_data = (pci_dev_data_t *) dev->driver_data;
 	hw_resource_list_t *hw_res_list = &dev_data->hw_resources;
 	hw_resource_t *hw_resources =  hw_res_list->resources;
-	size_t count = hw_res_list->count;	
+	size_t count = hw_res_list->count;
 	
 	assert(NULL != hw_resources);
@@ -245,43 +248,42 @@
 		hw_resources[count].type = IO_RANGE;
 		hw_resources[count].res.io_range.address = range_addr;
-		hw_resources[count].res.io_range.size = range_size;	
-		hw_resources[count].res.io_range.endianness = LITTLE_ENDIAN;	
+		hw_resources[count].res.io_range.size = range_size;
+		hw_resources[count].res.io_range.endianness = LITTLE_ENDIAN;
 	} else {
 		hw_resources[count].type = MEM_RANGE;
 		hw_resources[count].res.mem_range.address = range_addr;
-		hw_resources[count].res.mem_range.size = range_size;	
+		hw_resources[count].res.mem_range.size = range_size;
 		hw_resources[count].res.mem_range.endianness = LITTLE_ENDIAN;
 	}
 	
-	hw_res_list->count++;	
-}
-
-
-/** Read the base address register (BAR) of the device 
- *  and if it contains valid address add it to the devices hw resource list.
- * 
- * @param dev the pci device.
- * @param addr the address of the BAR in the PCI configuration address space of the device.
- * 
- * @return the addr the address of the BAR which should be read next.
+	hw_res_list->count++;
+}
+
+/** Read the base address register (BAR) of the device and if it contains valid
+ * address add it to the devices hw resource list.
+ *
+ * @param dev	The pci device.
+ * @param addr	The address of the BAR in the PCI configuration address space of
+ *		the device.
+ * @return	The addr the address of the BAR which should be read next.
  */
-int pci_read_bar(device_t *dev, int addr) 
+int pci_read_bar(device_t *dev, int addr)
 {	
-	// value of the BAR
+	/* Value of the BAR */
 	uint32_t val, mask;
-	// IO space address
+	/* IO space address */
 	bool io;
-	// 64-bit wide address
+	/* 64-bit wide address */
 	bool w64;
 	
-	// size of the io or memory range specified by the BAR
+	/* Size of the io or memory range specified by the BAR */
 	size_t range_size;
-	// beginning of the io or memory range specified by the BAR
+	/* Beginning of the io or memory range specified by the BAR */
 	uint64_t range_addr;
 	
-	// get the value of the BAR
+	/* Get the value of the BAR. */
 	val = pci_conf_read_32(dev, addr);
 	
-	io = (bool)(val & 1);
+	io = (bool) (val & 1);
 	if (io) {
 		w64 = false;
@@ -295,27 +297,29 @@
 			break;
 		default:
-			// reserved, go to the next BAR
-			return addr + 4;							
+			/* reserved, go to the next BAR */
+			return addr + 4;
 		}
 	}
 	
-	// get the address mask
+	/* Get the address mask. */
 	pci_conf_write_32(dev, addr, 0xffffffff);
-	mask = pci_conf_read_32(dev, addr);	
-	
-	// restore the original value
+	mask = pci_conf_read_32(dev, addr);
+	
+	/* Restore the original value. */
 	pci_conf_write_32(dev, addr, val);
-	val = pci_conf_read_32(dev, addr);	
+	val = pci_conf_read_32(dev, addr);
 	
 	range_size = pci_bar_mask_to_size(mask);
 	
 	if (w64) {
-		range_addr = ((uint64_t)pci_conf_read_32(dev, addr + 4) << 32) | (val & 0xfffffff0);	
+		range_addr = ((uint64_t)pci_conf_read_32(dev, addr + 4) << 32) |
+		    (val & 0xfffffff0);
 	} else {
 		range_addr = (val & 0xfffffff0);
-	}	
+	}
+	
 	if (0 != range_addr) {
 		printf(NAME ": device %s : ", dev->name);
-		printf("address = %x", range_addr);		
+		printf("address = %x", range_addr);
 		printf(", size = %x\n", range_size);
 	}
@@ -323,16 +327,16 @@
 	pci_add_range(dev, range_addr, range_size, io);
 	
-	if (w64) {
+	if (w64)
 		return addr + 8;
-	}
-	return addr + 4;	
+	
+	return addr + 4;
 }
 
 void pci_add_interrupt(device_t *dev, int irq)
 {
-	pci_dev_data_t *dev_data = (pci_dev_data_t *)dev->driver_data;
+	pci_dev_data_t *dev_data = (pci_dev_data_t *) dev->driver_data;
 	hw_resource_list_t *hw_res_list = &dev_data->hw_resources;
-	hw_resource_t *hw_resources =  hw_res_list->resources;
-	size_t count = hw_res_list->count;	
+	hw_resource_t *hw_resources = hw_res_list->resources;
+	size_t count = hw_res_list->count;
 	
 	assert(NULL != hw_resources);
@@ -342,6 +346,5 @@
 	hw_resources[count].res.interrupt.irq = irq;
 	
-	hw_res_list->count++;		
-	
+	hw_res_list->count++;
 	
 	printf(NAME ": device %s uses irq %x.\n", dev->name, irq);
@@ -351,13 +354,12 @@
 {
 	uint8_t irq = pci_conf_read_8(dev, PCI_BRIDGE_INT_LINE);
-	if (0xff != irq) {
+	if (0xff != irq)
 		pci_add_interrupt(dev, irq);
-	}	
 }
 
 /** Enumerate (recursively) and register the devices connected to a pci bus.
- * 
- * @param parent the host-to-pci bridge device.
- * @param bus_num the bus number. 
+ *
+ * @param parent	The host-to-pci bridge device.
+ * @param bus_num	The bus number.
  */
 void pci_bus_scan(device_t *parent, int bus_num) 
@@ -377,18 +379,26 @@
 		for (fnum = 0; multi && fnum < 8; fnum++) {
 			init_pci_dev_data(dev_data, bus_num, dnum, fnum);
-			dev_data->vendor_id = pci_conf_read_16(dev, PCI_VENDOR_ID);
-			dev_data->device_id = pci_conf_read_16(dev, PCI_DEVICE_ID);
-			if (dev_data->vendor_id == 0xffff) { // device is not present, go on scanning the bus
-				if (fnum == 0) {
+			dev_data->vendor_id = pci_conf_read_16(dev,
+			    PCI_VENDOR_ID);
+			dev_data->device_id = pci_conf_read_16(dev,
+			    PCI_DEVICE_ID);
+			if (dev_data->vendor_id == 0xffff) {
+				/*
+				 * The device is not present, go on scanning the
+				 * bus.
+				 */
+				if (fnum == 0)
 					break;
-				} else {
-					continue;  
-				}
+				else
+					continue;
 			}
+			
 			header_type = pci_conf_read_8(dev, PCI_HEADER_TYPE);
 			if (fnum == 0) {
-				 multi = header_type >> 7;  // is the device multifunction?
+				/* Is the device multifunction? */
+				multi = header_type >> 7;
 			}
-			header_type = header_type & 0x7F; // clear the multifunction bit
+			/* Clear the multifunction bit. */
+			header_type = header_type & 0x7F;
 			
 			create_pci_dev_name(dev);
@@ -398,29 +408,31 @@
 			pci_read_interrupt(dev);
 			
-			dev->ops = &pci_child_ops;			
-			
-			printf(NAME ": adding new child device %s.\n", dev->name);
+			dev->ops = &pci_child_ops;
+			
+			printf(NAME ": adding new child device %s.\n",
+			    dev->name);
 			
 			create_pci_match_ids(dev);
 			
-			if (EOK != child_device_register(dev, parent)) {				
-				pci_clean_resource_list(dev);				
+			if (EOK != child_device_register(dev, parent)) {
+				pci_clean_resource_list(dev);
 				clean_match_ids(&dev->match_ids);
-				free((char *)dev->name);
+				free((char *) dev->name);
 				dev->name = NULL;
 				continue;
 			}
 			
-			//printf(NAME ": new device %s was successfully registered by device manager.\n", dev->name);
-			
-			if (header_type == PCI_HEADER_TYPE_BRIDGE || header_type == PCI_HEADER_TYPE_CARDBUS ) {
-				child_bus = pci_conf_read_8(dev, PCI_BRIDGE_SEC_BUS_NUM);
-				printf(NAME ": device is pci-to-pci bridge, secondary bus number = %d.\n", bus_num);
-				if(child_bus > bus_num) {			
-					pci_bus_scan(parent, child_bus);	
-				}					
+			if (header_type == PCI_HEADER_TYPE_BRIDGE ||
+			    header_type == PCI_HEADER_TYPE_CARDBUS ) {
+				child_bus = pci_conf_read_8(dev,
+				    PCI_BRIDGE_SEC_BUS_NUM);
+				printf(NAME ": device is pci-to-pci bridge, "
+				    "secondary bus number = %d.\n", bus_num);
+				if(child_bus > bus_num)
+					pci_bus_scan(parent, child_bus);
 			}
 			
-			dev = create_device();  // alloc new aux. dev. structure
+			/* Alloc new aux. dev. structure. */
+			dev = create_device();
 			dev_data = create_pci_dev_data();
 			dev->driver_data = dev_data;
@@ -431,6 +443,7 @@
 	if (dev_data->vendor_id == 0xffff) {
 		delete_device(dev);
-		delete_pci_dev_data(dev_data);  // free the auxiliary device structure
-	}		
+		/* Free the auxiliary device structure. */
+		delete_pci_dev_data(dev_data);
+	}
 }
 
@@ -443,9 +456,11 @@
 		printf(NAME ": pci_add_device allocation failed.\n");
 		return ENOMEM;
-	}	
-	
-	dev->parent_phone = devman_parent_device_connect(dev->handle,  IPC_FLAG_BLOCKING);
-	if (dev->parent_phone <= 0) {
-		printf(NAME ": pci_add_device failed to connect to the parent's driver.\n");
+	}
+	
+	dev->parent_phone = devman_parent_device_connect(dev->handle,
+	    IPC_FLAG_BLOCKING);
+	if (dev->parent_phone < 0) {
+		printf(NAME ": pci_add_device failed to connect to the "
+		    "parent's driver.\n");
 		delete_pci_bus_data(bus_data);
 		return EPARTY;	/* FIXME: use another EC */
@@ -455,5 +470,6 @@
 	
 	if (!get_hw_resources(dev->parent_phone, &hw_resources)) {
-		printf(NAME ": pci_add_device failed to get hw resources for the device.\n");
+		printf(NAME ": pci_add_device failed to get hw resources for "
+		    "the device.\n");
 		delete_pci_bus_data(bus_data);
 		ipc_hangup(dev->parent_phone);
@@ -461,5 +477,6 @@
 	}	
 	
-	printf(NAME ": conf_addr = %x.\n", hw_resources.resources[0].res.io_range.address);	
+	printf(NAME ": conf_addr = %x.\n",
+	    hw_resources.resources[0].res.io_range.address);
 	
 	assert(hw_resources.count > 0);
@@ -467,18 +484,20 @@
 	assert(hw_resources.resources[0].res.io_range.size == 8);
 	
-	bus_data->conf_io_addr = (uint32_t)hw_resources.resources[0].res.io_range.address;
-	
-	if (pio_enable((void *)bus_data->conf_io_addr, 8, &bus_data->conf_addr_port)) {
+	bus_data->conf_io_addr =
+	    (uint32_t) hw_resources.resources[0].res.io_range.address;
+	
+	if (pio_enable((void *)bus_data->conf_io_addr, 8,
+	    &bus_data->conf_addr_port)) {
 		printf(NAME ": failed to enable configuration ports.\n");
 		delete_pci_bus_data(bus_data);
 		ipc_hangup(dev->parent_phone);
 		clean_hw_resource_list(&hw_resources);
-		return EADDRNOTAVAIL;					
-	}
-	bus_data->conf_data_port = (char *)bus_data->conf_addr_port + 4;
+		return EADDRNOTAVAIL;
+	}
+	bus_data->conf_data_port = (char *) bus_data->conf_addr_port + 4;
 	
 	dev->driver_data = bus_data;
 	
-	// enumerate child devices
+	/* Enumerate child devices. */
 	printf(NAME ": scanning the bus\n");
 	pci_bus_scan(dev, 0);
@@ -489,5 +508,5 @@
 }
 
-static void pciintel_init() 
+static void pciintel_init(void)
 {
 	pci_child_ops.interfaces[HW_RES_DEV_IFACE] = &pciintel_child_res_iface;
Index: uspace/drv/pciintel/pci.h
===================================================================
--- uspace/drv/pciintel/pci.h	(revision 49698fac57de2ecd7140a9c7fd845dfa15affad5)
+++ uspace/drv/pciintel/pci.h	(revision 663f41c465b5ccd70664cc4423f19a9fe2351eee)
@@ -1,4 +1,4 @@
 /*
- * Copyright (c) 2010 Lenka Trochtova 
+ * Copyright (c) 2010 Lenka Trochtova
  * All rights reserved.
  *
@@ -32,8 +32,7 @@
 /** @file
  */
- 
-#ifndef PCI_H
-#define PCI_H
 
+#ifndef PCI_H_
+#define PCI_H_
 
 #include <stdlib.h>
@@ -54,42 +53,42 @@
 } pci_dev_data_t;
 
-void create_pci_match_ids(device_t *dev);
+extern void create_pci_match_ids(device_t *);
 
-uint8_t pci_conf_read_8(device_t *dev, int reg);
-uint16_t pci_conf_read_16(device_t *dev, int reg);
-uint32_t pci_conf_read_32(device_t *dev, int reg);
-void pci_conf_write_8(device_t *dev, int reg, uint8_t val);
-void pci_conf_write_16(device_t *dev, int reg, uint16_t val);
-void pci_conf_write_32(device_t *dev, int reg, uint32_t val);
+extern uint8_t pci_conf_read_8(device_t *, int);
+extern uint16_t pci_conf_read_16(device_t *, int);
+extern uint32_t pci_conf_read_32(device_t *, int);
+extern void pci_conf_write_8(device_t *, int, uint8_t);
+extern void pci_conf_write_16(device_t *, int, uint16_t);
+extern void pci_conf_write_32(device_t *, int, uint32_t);
 
-void pci_add_range(device_t *dev, uint64_t range_addr, size_t range_size, bool io);
-int pci_read_bar(device_t *dev, int addr);
-void pci_read_interrupt(device_t *dev);
-void pci_add_interrupt(device_t *dev, int irq);
+extern void pci_add_range(device_t *, uint64_t, size_t, bool);
+extern int pci_read_bar(device_t *, int);
+extern void pci_read_interrupt(device_t *);
+extern void pci_add_interrupt(device_t *, int);
 
-void pci_bus_scan(device_t *parent, int bus_num);
+extern void pci_bus_scan(device_t *, int);
 
-
-static inline pci_dev_data_t *create_pci_dev_data() 
+static inline pci_dev_data_t *create_pci_dev_data(void)
 {
-	pci_dev_data_t *res = (pci_dev_data_t *)malloc(sizeof(pci_dev_data_t));
-	if (NULL != res) {
+	pci_dev_data_t *res = (pci_dev_data_t *) malloc(sizeof(pci_dev_data_t));
+	
+	if (NULL != res)
 		memset(res, 0, sizeof(pci_dev_data_t));
-	}
-	return res;	
+	return res;
 }
 
-static inline void init_pci_dev_data(pci_dev_data_t *d, int bus, int dev, int fn) 
+static inline void
+init_pci_dev_data(pci_dev_data_t *d, int bus, int dev, int fn)
 {
 	d->bus = bus;
 	d->dev = dev;
-	d->fn = fn;	
+	d->fn = fn;
 }
 
-static inline void delete_pci_dev_data(pci_dev_data_t *d) 
+static inline void delete_pci_dev_data(pci_dev_data_t *d)
 {
 	if (NULL != d) {
 		clean_hw_resource_list(&d->hw_resources);
-		free(d);	
+		free(d);
 	}
 }
@@ -97,7 +96,9 @@
 static inline void create_pci_dev_name(device_t *dev)
 {
-	pci_dev_data_t *dev_data = (pci_dev_data_t *)dev->driver_data;
+	pci_dev_data_t *dev_data = (pci_dev_data_t *) dev->driver_data;
 	char *name = NULL;
-	asprintf(&name, "%02x:%02x.%01x", dev_data->bus, dev_data->dev, dev_data->fn);
+	
+	asprintf(&name, "%02x:%02x.%01x", dev_data->bus, dev_data->dev,
+	    dev_data->fn);
 	dev->name = name;
 }
@@ -106,11 +107,14 @@
 {
 	pci_dev_data_t *dev_data = (pci_dev_data_t *)dev->driver_data;
-	dev_data->hw_resources.resources = (hw_resource_t *)malloc(PCI_MAX_HW_RES * sizeof(hw_resource_t));
-	return dev_data->hw_resources.resources != NULL;	
+	
+	dev_data->hw_resources.resources =
+	    (hw_resource_t *) malloc(PCI_MAX_HW_RES * sizeof(hw_resource_t));
+	return dev_data->hw_resources.resources != NULL;
 }
 
 static inline void pci_clean_resource_list(device_t *dev)
 {
-	pci_dev_data_t *dev_data = (pci_dev_data_t *)dev->driver_data;
+	pci_dev_data_t *dev_data = (pci_dev_data_t *) dev->driver_data;
+	
 	if (NULL != dev_data->hw_resources.resources) {
 		free(dev_data->hw_resources.resources);
@@ -119,17 +123,19 @@
 }
 
-/** Read the base address registers (BARs) of the device 
- *  and adds the addresses to its hw resource list.
- * 
+/** Read the base address registers (BARs) of the device and adds the addresses
+ * to its hw resource list.
+ *
  * @param dev the pci device.
  */
 static inline  void pci_read_bars(device_t *dev)
 {
-	// position of the BAR in the PCI configuration address space of the device
+	/*
+	 * Position of the BAR in the PCI configuration address space of the
+	 * device.
+	 */
 	int addr = PCI_BASE_ADDR_0;
 	
-	while (addr <= PCI_BASE_ADDR_5) {
-		addr = pci_read_bar(dev, addr);	
-	}	
+	while (addr <= PCI_BASE_ADDR_5)
+		addr = pci_read_bar(dev, addr);
 }
 
@@ -139,7 +145,5 @@
 }
 
-
 #endif
-
 
 /**
Index: uspace/drv/pciintel/pci_regs.h
===================================================================
--- uspace/drv/pciintel/pci_regs.h	(revision 49698fac57de2ecd7140a9c7fd845dfa15affad5)
+++ uspace/drv/pciintel/pci_regs.h	(revision 663f41c465b5ccd70664cc4423f19a9fe2351eee)
@@ -1,4 +1,4 @@
 /*
- * Copyright (c) 2010 Lenka Trochtova 
+ * Copyright (c) 2010 Lenka Trochtova
  * All rights reserved.
  *
@@ -32,69 +32,68 @@
 /** @file
  */
- 
-#ifndef PCI_REGS_H
-#define PCI_REGS_H
 
-// Header types 
-#define PCI_HEADER_TYPE_DEV			0
-#define PCI_HEADER_TYPE_BRIDGE		1
-#define PCI_HEADER_TYPE_CARDBUS		2
+#ifndef PCI_REGS_H_
+#define PCI_REGS_H_
 
-// Header type 0 and 1
-#define PCI_VENDOR_ID		 			0x00
-#define PCI_DEVICE_ID 					0x02
-#define PCI_COMMAND 					0x04
-#define PCI_STATUS 						0x06
-#define PCI_REVISION_ID 				0x08
-#define PCI_PROG_IF						0x09
-#define PCI_SUB_CLASS					0x0A
-#define PCI_BASE_CLASS					0x0B
-#define PCI_CACHE_LINE_SIZE				0x0C
-#define PCI_LATENCY_TIMER				0x0D
-#define PCI_HEADER_TYPE					0x0E
-#define PCI_BIST						0x0F
+/* Header types */
+#define PCI_HEADER_TYPE_DEV	0
+#define PCI_HEADER_TYPE_BRIDGE	1
+#define PCI_HEADER_TYPE_CARDBUS	2
 
-#define PCI_BASE_ADDR_0 				0x10
-#define PCI_BASE_ADDR_1 				0x14
+/* Header type 0 and 1 */
+#define PCI_VENDOR_ID		0x00
+#define PCI_DEVICE_ID		0x02
+#define PCI_COMMAND		0x04
+#define PCI_STATUS		0x06
+#define PCI_REVISION_ID		0x08
+#define PCI_PROG_IF		0x09
+#define PCI_SUB_CLASS		0x0A
+#define PCI_BASE_CLASS		0x0B
+#define PCI_CACHE_LINE_SIZE	0x0C
+#define PCI_LATENCY_TIMER	0x0D
+#define PCI_HEADER_TYPE		0x0E
+#define PCI_BIST		0x0F
 
-// Header type 0
-#define PCI_BASE_ADDR_2 				0x18
-#define PCI_BASE_ADDR_3 				0x1B
-#define PCI_BASE_ADDR_4 				0x20
-#define PCI_BASE_ADDR_5 				0x24
+#define PCI_BASE_ADDR_0		0x10
+#define PCI_BASE_ADDR_1		0x14
 
-#define PCI_CARDBUS_CIS_PTR				0x28
-#define PCI_SUBSYSTEM_VENDOR_ID			0x2C
-#define PCI_SUBSYSTEM_ID				0x2E
-#define PCI_EXP_ROM_BASE				0x30
-#define PCI_CAP_PTR						0x34
-#define PCI_INT_LINE					0x3C
-#define PCI_INT_PIN						0x3D
-#define PCI_MIN_GNT						0x3E
-#define PCI_MAX_LAT						0x3F
+/* Header type 0 */
+#define PCI_BASE_ADDR_2			0x18
+#define PCI_BASE_ADDR_3			0x1B
+#define PCI_BASE_ADDR_4			0x20
+#define PCI_BASE_ADDR_5			0x24
 
-// Header type 1
-#define PCI_BRIDGE_PRIM_BUS_NUM 		0x18
-#define PCI_BRIDGE_SEC_BUS_NUM 			0x19
-#define PCI_BRIDGE_SUBORD_BUS_NUM 		0x1A
-#define PCI_BRIDGE_SEC_LATENCY_TIMER 	0x1B
-#define PCI_BRIDGE_IO_BASE 				0x1C
-#define PCI_BRIDGE_IO_LIMIT 			0x1D
-#define PCI_BRIDGE_SEC_STATUS 			0x1E
-#define PCI_BRIDGE_MEMORY_BASE			0x20
-#define PCI_BRIDGE_MEMORY_LIMIT			0x22
-#define PCI_BRIDGE_PREF_MEMORY_BASE		0x24
+#define PCI_CARDBUS_CIS_PTR		0x28
+#define PCI_SUBSYSTEM_VENDOR_ID		0x2C
+#define PCI_SUBSYSTEM_ID		0x2E
+#define PCI_EXP_ROM_BASE		0x30
+#define PCI_CAP_PTR			0x34
+#define PCI_INT_LINE			0x3C
+#define PCI_INT_PIN			0x3D
+#define PCI_MIN_GNT			0x3E
+#define PCI_MAX_LAT			0x3F
+
+/* Header type 1 */
+#define PCI_BRIDGE_PRIM_BUS_NUM		0x18
+#define PCI_BRIDGE_SEC_BUS_NUM		0x19
+#define PCI_BRIDGE_SUBORD_BUS_NUM	0x1A
+#define PCI_BRIDGE_SEC_LATENCY_TIMER	0x1B
+#define PCI_BRIDGE_IO_BASE		0x1C
+#define PCI_BRIDGE_IO_LIMIT		0x1D
+#define PCI_BRIDGE_SEC_STATUS		0x1E
+#define PCI_BRIDGE_MEMORY_BASE		0x20
+#define PCI_BRIDGE_MEMORY_LIMIT		0x22
+#define PCI_BRIDGE_PREF_MEMORY_BASE	0x24
 #define PCI_BRIDGE_PREF_MEMORY_LIMIT	0x26
 #define PCI_BRIDGE_PREF_MEMORY_BASE_UP	0x28
 #define PCI_BRIDGE_PREF_MEMORY_LIMIT_UP	0x2C
-#define PCI_BRIDGE_IO_BASE_UP			0x30
-#define PCI_BRIDGE_IO_LIMIT_UP 			0x32
-#define PCI_BRIDGE_EXP_ROM_BASE			0x38
-#define PCI_BRIDGE_INT_LINE				0x3C
-#define PCI_BRIDGE_INT_PIN				0x3D
-#define PCI_BRIDGE_CTL					0x3E
+#define PCI_BRIDGE_IO_BASE_UP		0x30
+#define PCI_BRIDGE_IO_LIMIT_UP		0x32
+#define PCI_BRIDGE_EXP_ROM_BASE		0x38
+#define PCI_BRIDGE_INT_LINE		0x3C
+#define PCI_BRIDGE_INT_PIN		0x3D
+#define PCI_BRIDGE_CTL			0x3E
 
 #endif
-
 
 /**