Changes in kernel/arch/arm32/src/cpu/cpu.c [46a6a5d:65871bb] in mainline

File:

• kernel/arch/arm32/src/cpu/cpu.c (modified) (4 diffs)

kernel/arch/arm32/src/cpu/cpu.c

@@ -98 +98 @@
 void cpu_arch_init(void)
 {
+#if defined(PROCESSOR_armv7_a) | defined(PROCESSOR_armv6)
         uint32_t control_reg = 0;
         asm volatile (
@@ -104 +105 @@
         );
         
-        /* Turn off tex remap, RAZ/WI prior to armv7 */
+        /* Turn off tex remap, RAZ ignores writes prior to armv7 */
         control_reg &= ~CP15_R1_TEX_REMAP_EN;
-        /* Turn off accessed flag, RAZ/WI prior to armv7 */
+        /* Turn off accessed flag, RAZ ignores writes prior to armv7 */
         control_reg &= ~(CP15_R1_ACCESS_FLAG_EN | CP15_R1_HW_ACCESS_FLAG_EN);
-        /* Enable branch prediction RAZ/WI if not supported */
-        control_reg |= CP15_R1_BRANCH_PREDICT_EN;
-
-        /* Unaligned access is supported on armv6+ */
-#if defined(PROCESSOR_ARCH_armv7_a) | defined(PROCESSOR_ARCH_armv6)
-        /* Enable unaligned access, RAZ/WI prior to armv6
-         * switchable on armv6, RAO/WI writes on armv7,
+        /* Enable unaligned access, RAZ ignores writes prior to armv6
+         * switchable on armv6, RAO ignores writes on armv7,
          * see ARM Architecture Reference Manual ARMv7-A and ARMv7-R edition
          * L.3.1 (p. 2456) */
@@ -128 +124 @@
          *    ARM Architecture Reference Manual ARMv7-A and ARMv7-R Edition
          *    B3.11.1 (p. 1383)
-         * We are safe to turn this on. For arm v6 see ch L.6.2 (p. 2469)
-         * L2 Cache for armv7 was enabled in boot code.
+         * ICache coherency is elaborate on in barrier.h.
+         * We are safe to turn these on.
          */
-        control_reg |= CP15_R1_CACHE_EN;
-#endif
-#ifdef PROCESSOR_cortex_a8
-         /* ICache coherency is elaborate on in barrier.h.
-          * Cortex-A8 implements IVIPT extension.
-          * Cortex-A8 TRM ch. 7.2.6 p. 7-4 (PDF 245) */
-        control_reg |= CP15_R1_INST_CACHE_EN;
-#endif
+        control_reg |= CP15_R1_CACHE_EN | CP15_R1_INST_CACHE_EN;
         
         asm volatile (
@@ -144 +133 @@
                 :: [control_reg] "r" (control_reg)
         );
+#endif
 #ifdef CONFIG_FPU
         fpu_setup();