Index: kernel/arch/amd64/include/arch/atomic.h
===================================================================
--- kernel/arch/amd64/include/arch/atomic.h	(revision 013e5d32c9af4ea5eff1d29e41946a398895b296)
+++ kernel/arch/amd64/include/arch/atomic.h	(revision 64532a970f3247a33dafe22f848eaf9f61ea730f)
@@ -45,11 +45,11 @@
 #ifdef CONFIG_SMP
 	asm volatile (
-		"lock incq %[count]\n"
-		: [count] "+m" (val->count)
-	);
-#else
-	asm volatile (
-		"incq %[count]\n"
-		: [count] "+m" (val->count)
+	    "lock incq %[count]\n"
+	    : [count] "+m" (val->count)
+	);
+#else
+	asm volatile (
+	    "incq %[count]\n"
+	    : [count] "+m" (val->count)
 	);
 #endif /* CONFIG_SMP */
@@ -60,11 +60,11 @@
 #ifdef CONFIG_SMP
 	asm volatile (
-		"lock decq %[count]\n"
-		: [count] "+m" (val->count)
-	);
-#else
-	asm volatile (
-		"decq %[count]\n"
-		: [count] "+m" (val->count)
+	    "lock decq %[count]\n"
+	    : [count] "+m" (val->count)
+	);
+#else
+	asm volatile (
+	    "decq %[count]\n"
+	    : [count] "+m" (val->count)
 	);
 #endif /* CONFIG_SMP */
@@ -76,7 +76,7 @@
 
 	asm volatile (
-		"lock xaddq %[r], %[count]\n"
-		: [count] "+m" (val->count),
-		  [r] "+r" (r)
+	    "lock xaddq %[r], %[count]\n"
+	    : [count] "+m" (val->count),
+	      [r] "+r" (r)
 	);
 
@@ -89,7 +89,7 @@
 
 	asm volatile (
-		"lock xaddq %[r], %[count]\n"
-		: [count] "+m" (val->count),
-		  [r] "+r" (r)
+	    "lock xaddq %[r], %[count]\n"
+	    : [count] "+m" (val->count),
+	      [r] "+r" (r)
 	);
 
@@ -105,7 +105,7 @@
 
 	asm volatile (
-		"xchgq %[v], %[count]\n"
-		: [v] "+r" (v),
-		  [count] "+m" (val->count)
+	    "xchgq %[v], %[count]\n"
+	    : [v] "+r" (v),
+	      [count] "+m" (val->count)
 	);
 
@@ -120,16 +120,16 @@
 	preemption_disable();
 	asm volatile (
-		"0:\n"
-		"	pause\n"
-		"	mov %[count], %[tmp]\n"
-		"	testq %[tmp], %[tmp]\n"
-		"	jnz 0b\n"       /* lightweight looping on locked spinlock */
-
-		"	incq %[tmp]\n"  /* now use the atomic operation */
-		"	xchgq %[count], %[tmp]\n"
-		"	testq %[tmp], %[tmp]\n"
-		"	jnz 0b\n"
-		: [count] "+m" (val->count),
-		  [tmp] "=&r" (tmp)
+	    "0:\n"
+	    "	pause\n"
+	    "	mov %[count], %[tmp]\n"
+	    "	testq %[tmp], %[tmp]\n"
+	    "	jnz 0b\n"       /* lightweight looping on locked spinlock */
+
+	    "	incq %[tmp]\n"  /* now use the atomic operation */
+	    "	xchgq %[count], %[tmp]\n"
+	    "	testq %[tmp], %[tmp]\n"
+	    "	jnz 0b\n"
+	    : [count] "+m" (val->count),
+	      [tmp] "=&r" (tmp)
 	);
 
Index: kernel/arch/amd64/include/arch/cpuid.h
===================================================================
--- kernel/arch/amd64/include/arch/cpuid.h	(revision 013e5d32c9af4ea5eff1d29e41946a398895b296)
+++ kernel/arch/amd64/include/arch/cpuid.h	(revision 64532a970f3247a33dafe22f848eaf9f61ea730f)
@@ -55,5 +55,5 @@
 	uint32_t cpuid_ecx;
 	uint32_t cpuid_edx;
-} __attribute__ ((packed)) cpu_info_t;
+} __attribute__((packed)) cpu_info_t;
 
 extern int has_cpuid(void);
Index: kernel/arch/amd64/include/arch/cycle.h
===================================================================
--- kernel/arch/amd64/include/arch/cycle.h	(revision 013e5d32c9af4ea5eff1d29e41946a398895b296)
+++ kernel/arch/amd64/include/arch/cycle.h	(revision 64532a970f3247a33dafe22f848eaf9f61ea730f)
@@ -44,7 +44,7 @@
 
 	asm volatile (
-		"rdtsc\n"
-		: "=a" (lower),
-		  "=d" (upper)
+	    "rdtsc\n"
+	    : "=a" (lower),
+	      "=d" (upper)
 	);
 
Index: kernel/arch/amd64/include/arch/mm/page.h
===================================================================
--- kernel/arch/amd64/include/arch/mm/page.h	(revision 013e5d32c9af4ea5eff1d29e41946a398895b296)
+++ kernel/arch/amd64/include/arch/mm/page.h	(revision 64532a970f3247a33dafe22f848eaf9f61ea730f)
@@ -198,5 +198,5 @@
 	unsigned int accessed : 1;
 	unsigned int dirty : 1;
-	unsigned int unused: 1;
+	unsigned int unused : 1;
 	unsigned int global : 1;
 	unsigned int soft_valid : 1;  /**< Valid content even if present bit is cleared. */
@@ -205,5 +205,5 @@
 	unsigned int addr_32_51 : 21;
 	unsigned int no_execute : 1;
-} __attribute__ ((packed)) pte_t;
+} __attribute__((packed)) pte_t;
 
 NO_TRACE static inline unsigned int get_pt_flags(pte_t *pt, size_t i)
Index: kernel/arch/amd64/include/arch/pm.h
===================================================================
--- kernel/arch/amd64/include/arch/pm.h	(revision 013e5d32c9af4ea5eff1d29e41946a398895b296)
+++ kernel/arch/amd64/include/arch/pm.h	(revision 64532a970f3247a33dafe22f848eaf9f61ea730f)
@@ -37,6 +37,6 @@
 
 #ifndef __ASSEMBLER__
-	#include <typedefs.h>
-	#include <arch/context.h>
+#include <typedefs.h>
+#include <arch/context.h>
 #endif
 
@@ -91,55 +91,55 @@
 
 typedef struct {
-	unsigned limit_0_15: 16;
-	unsigned base_0_15: 16;
-	unsigned base_16_23: 8;
-	unsigned access: 8;
-	unsigned limit_16_19: 4;
-	unsigned available: 1;
-	unsigned longmode: 1;
-	unsigned special: 1;
+	unsigned limit_0_15 : 16;
+	unsigned base_0_15 : 16;
+	unsigned base_16_23 : 8;
+	unsigned access : 8;
+	unsigned limit_16_19 : 4;
+	unsigned available : 1;
+	unsigned longmode : 1;
+	unsigned special : 1;
 	unsigned granularity : 1;
-	unsigned base_24_31: 8;
-} __attribute__ ((packed)) descriptor_t;
+	unsigned base_24_31 : 8;
+} __attribute__((packed)) descriptor_t;
 
 typedef struct {
-	unsigned limit_0_15: 16;
-	unsigned base_0_15: 16;
-	unsigned base_16_23: 8;
-	unsigned type: 4;
+	unsigned limit_0_15 : 16;
+	unsigned base_0_15 : 16;
+	unsigned base_16_23 : 8;
+	unsigned type : 4;
 	unsigned : 1;
 	unsigned dpl : 2;
 	unsigned present : 1;
-	unsigned limit_16_19: 4;
-	unsigned available: 1;
+	unsigned limit_16_19 : 4;
+	unsigned available : 1;
 	unsigned : 2;
 	unsigned granularity : 1;
-	unsigned base_24_31: 8;
+	unsigned base_24_31 : 8;
 	unsigned base_32_63 : 32;
 	unsigned  : 32;
-} __attribute__ ((packed)) tss_descriptor_t;
+} __attribute__((packed)) tss_descriptor_t;
 
 typedef struct {
-	unsigned offset_0_15: 16;
-	unsigned selector: 16;
-	unsigned ist:3;
-	unsigned unused: 5;
-	unsigned type: 5;
-	unsigned dpl: 2;
+	unsigned offset_0_15 : 16;
+	unsigned selector : 16;
+	unsigned ist : 3;
+	unsigned unused : 5;
+	unsigned type : 5;
+	unsigned dpl : 2;
 	unsigned present : 1;
-	unsigned offset_16_31: 16;
-	unsigned offset_32_63: 32;
+	unsigned offset_16_31 : 16;
+	unsigned offset_32_63 : 32;
 	unsigned  : 32;
-} __attribute__ ((packed)) idescriptor_t;
+} __attribute__((packed)) idescriptor_t;
 
 typedef struct {
 	uint16_t limit;
 	uint64_t base;
-} __attribute__ ((packed)) ptr_16_64_t;
+} __attribute__((packed)) ptr_16_64_t;
 
 typedef struct {
 	uint16_t limit;
 	uint32_t base;
-} __attribute__ ((packed)) ptr_16_32_t;
+} __attribute__((packed)) ptr_16_32_t;
 
 typedef struct {
@@ -160,5 +160,5 @@
 	uint16_t iomap_base;
 	uint8_t iomap[TSS_IOMAP_SIZE];
-} __attribute__ ((packed)) tss_t;
+} __attribute__((packed)) tss_t;
 
 extern tss_t *tss_p;
Index: kernel/arch/amd64/src/cpu/cpu.c
===================================================================
--- kernel/arch/amd64/src/cpu/cpu.c	(revision 013e5d32c9af4ea5eff1d29e41946a398895b296)
+++ kernel/arch/amd64/src/cpu/cpu.c	(revision 64532a970f3247a33dafe22f848eaf9f61ea730f)
@@ -136,5 +136,5 @@
 }
 
-void cpu_print_report(cpu_t* m)
+void cpu_print_report(cpu_t *m)
 {
 	printf("cpu%d: (%s family=%d model=%d stepping=%d apicid=%u) %dMHz\n",
Index: kernel/arch/amd64/src/fpu_context.c
===================================================================
--- kernel/arch/amd64/src/fpu_context.c	(revision 013e5d32c9af4ea5eff1d29e41946a398895b296)
+++ kernel/arch/amd64/src/fpu_context.c	(revision 64532a970f3247a33dafe22f848eaf9f61ea730f)
@@ -40,6 +40,6 @@
 {
 	asm volatile (
-		"fxsave %[fctx]\n"
-		: [fctx] "=m" (fctx->fpu)
+	    "fxsave %[fctx]\n"
+	    : [fctx] "=m" (fctx->fpu)
 	);
 }
@@ -49,6 +49,6 @@
 {
 	asm volatile (
-		"fxrstor %[fctx]\n"
-		: [fctx] "=m" (fctx->fpu)
+	    "fxrstor %[fctx]\n"
+	    : [fctx] "=m" (fctx->fpu)
 	);
 }
@@ -60,5 +60,5 @@
 	 * it masks all FPU exceptions*/
 	asm volatile (
-		"fninit\n"
+	    "fninit\n"
 	);
 }
Index: kernel/arch/amd64/src/interrupt.c
===================================================================
--- kernel/arch/amd64/src/interrupt.c	(revision 013e5d32c9af4ea5eff1d29e41946a398895b296)
+++ kernel/arch/amd64/src/interrupt.c	(revision 64532a970f3247a33dafe22f848eaf9f61ea730f)
@@ -60,7 +60,7 @@
  */
 
-void (* disable_irqs_function)(uint16_t irqmask) = NULL;
-void (* enable_irqs_function)(uint16_t irqmask) = NULL;
-void (* eoi_function)(void) = NULL;
+void (*disable_irqs_function)(uint16_t irqmask) = NULL;
+void (*enable_irqs_function)(uint16_t irqmask) = NULL;
+void (*eoi_function)(void) = NULL;
 const char *irqs_info = NULL;
 
@@ -231,5 +231,5 @@
 	    (iroutine_t) tlb_shootdown_ipi);
 	exc_register(VECTOR_SMP_CALL_IPI, "smp_call", true,
-		(iroutine_t) arch_smp_call_ipi_recv);
+	    (iroutine_t) arch_smp_call_ipi_recv);
 #endif
 }
Index: kernel/arch/amd64/src/pm.c
===================================================================
--- kernel/arch/amd64/src/pm.c	(revision 013e5d32c9af4ea5eff1d29e41946a398895b296)
+++ kernel/arch/amd64/src/pm.c	(revision 64532a970f3247a33dafe22f848eaf9f61ea730f)
@@ -55,5 +55,5 @@
 		.limit_0_15 = 0xffffU,
 		.limit_16_19 = 0xfU,
-	  	.access = AR_PRESENT | AR_CODE | DPL_KERNEL | AR_READABLE,
+		.access = AR_PRESENT | AR_CODE | DPL_KERNEL | AR_READABLE,
 		.longmode = 1,
 		.granularity = 1