Index: kernel/arch/sparc64/include/arch/asm.h
===================================================================
--- kernel/arch/sparc64/include/arch/asm.h	(revision d19b3fcc8f46d58029778b0ba79ad3d796f39697)
+++ kernel/arch/sparc64/include/arch/asm.h	(revision 62101beefba91c0ff7d989250af8474affc836b5)
@@ -44,5 +44,5 @@
 #include <trace.h>
 
-NO_TRACE static inline void pio_write_8(ioport8_t *port, uint8_t v)
+_NO_TRACE static inline void pio_write_8(ioport8_t *port, uint8_t v)
 {
 	*port = v;
@@ -50,5 +50,5 @@
 }
 
-NO_TRACE static inline void pio_write_16(ioport16_t *port, uint16_t v)
+_NO_TRACE static inline void pio_write_16(ioport16_t *port, uint16_t v)
 {
 	*port = v;
@@ -56,5 +56,5 @@
 }
 
-NO_TRACE static inline void pio_write_32(ioport32_t *port, uint32_t v)
+_NO_TRACE static inline void pio_write_32(ioport32_t *port, uint32_t v)
 {
 	*port = v;
@@ -62,5 +62,5 @@
 }
 
-NO_TRACE static inline uint8_t pio_read_8(ioport8_t *port)
+_NO_TRACE static inline uint8_t pio_read_8(ioport8_t *port)
 {
 	uint8_t rv = *port;
@@ -69,5 +69,5 @@
 }
 
-NO_TRACE static inline uint16_t pio_read_16(ioport16_t *port)
+_NO_TRACE static inline uint16_t pio_read_16(ioport16_t *port)
 {
 	uint16_t rv = *port;
@@ -76,5 +76,5 @@
 }
 
-NO_TRACE static inline uint32_t pio_read_32(ioport32_t *port)
+_NO_TRACE static inline uint32_t pio_read_32(ioport32_t *port)
 {
 	uint32_t rv = *port;
@@ -88,5 +88,5 @@
  *
  */
-NO_TRACE static inline uint64_t pstate_read(void)
+_NO_TRACE static inline uint64_t pstate_read(void)
 {
 	uint64_t v;
@@ -105,5 +105,5 @@
  *
  */
-NO_TRACE static inline void pstate_write(uint64_t v)
+_NO_TRACE static inline void pstate_write(uint64_t v)
 {
 	asm volatile (
@@ -119,5 +119,5 @@
  *
  */
-NO_TRACE static inline uint64_t tick_compare_read(void)
+_NO_TRACE static inline uint64_t tick_compare_read(void)
 {
 	uint64_t v;
@@ -136,5 +136,5 @@
  *
  */
-NO_TRACE static inline void tick_compare_write(uint64_t v)
+_NO_TRACE static inline void tick_compare_write(uint64_t v)
 {
 	asm volatile (
@@ -150,5 +150,5 @@
  *
  */
-NO_TRACE static inline uint64_t stick_compare_read(void)
+_NO_TRACE static inline uint64_t stick_compare_read(void)
 {
 	uint64_t v;
@@ -167,5 +167,5 @@
  *
  */
-NO_TRACE static inline void stick_compare_write(uint64_t v)
+_NO_TRACE static inline void stick_compare_write(uint64_t v)
 {
 	asm volatile (
@@ -181,5 +181,5 @@
  *
  */
-NO_TRACE static inline uint64_t tick_read(void)
+_NO_TRACE static inline uint64_t tick_read(void)
 {
 	uint64_t v;
@@ -198,5 +198,5 @@
  *
  */
-NO_TRACE static inline void tick_write(uint64_t v)
+_NO_TRACE static inline void tick_write(uint64_t v)
 {
 	asm volatile (
@@ -212,5 +212,5 @@
  *
  */
-NO_TRACE static inline uint64_t fprs_read(void)
+_NO_TRACE static inline uint64_t fprs_read(void)
 {
 	uint64_t v;
@@ -229,5 +229,5 @@
  *
  */
-NO_TRACE static inline void fprs_write(uint64_t v)
+_NO_TRACE static inline void fprs_write(uint64_t v)
 {
 	asm volatile (
@@ -243,5 +243,5 @@
  *
  */
-NO_TRACE static inline uint64_t softint_read(void)
+_NO_TRACE static inline uint64_t softint_read(void)
 {
 	uint64_t v;
@@ -260,5 +260,5 @@
  *
  */
-NO_TRACE static inline void softint_write(uint64_t v)
+_NO_TRACE static inline void softint_write(uint64_t v)
 {
 	asm volatile (
@@ -276,5 +276,5 @@
  *
  */
-NO_TRACE static inline void clear_softint_write(uint64_t v)
+_NO_TRACE static inline void clear_softint_write(uint64_t v)
 {
 	asm volatile (
@@ -292,5 +292,5 @@
  *
  */
-NO_TRACE static inline void set_softint_write(uint64_t v)
+_NO_TRACE static inline void set_softint_write(uint64_t v)
 {
 	asm volatile (
@@ -309,5 +309,5 @@
  *
  */
-NO_TRACE static inline ipl_t interrupts_enable(void)
+_NO_TRACE static inline ipl_t interrupts_enable(void)
 {
 	pstate_reg_t pstate;
@@ -329,5 +329,5 @@
  *
  */
-NO_TRACE static inline ipl_t interrupts_disable(void)
+_NO_TRACE static inline ipl_t interrupts_disable(void)
 {
 	pstate_reg_t pstate;
@@ -348,5 +348,5 @@
  *
  */
-NO_TRACE static inline void interrupts_restore(ipl_t ipl)
+_NO_TRACE static inline void interrupts_restore(ipl_t ipl)
 {
 	pstate_reg_t pstate;
@@ -364,5 +364,5 @@
  *
  */
-NO_TRACE static inline ipl_t interrupts_read(void)
+_NO_TRACE static inline ipl_t interrupts_read(void)
 {
 	return (ipl_t) pstate_read();
@@ -374,5 +374,5 @@
  *
  */
-NO_TRACE static inline bool interrupts_disabled(void)
+_NO_TRACE static inline bool interrupts_disabled(void)
 {
 	pstate_reg_t pstate;
@@ -389,5 +389,5 @@
  *
  */
-NO_TRACE static inline uintptr_t get_stack_base(void)
+_NO_TRACE static inline uintptr_t get_stack_base(void)
 {
 	uintptr_t unbiased_sp;
@@ -407,5 +407,5 @@
  *
  */
-NO_TRACE static inline uint64_t ver_read(void)
+_NO_TRACE static inline uint64_t ver_read(void)
 {
 	uint64_t v;
@@ -424,5 +424,5 @@
  *
  */
-NO_TRACE static inline uint64_t tpc_read(void)
+_NO_TRACE static inline uint64_t tpc_read(void)
 {
 	uint64_t v;
@@ -441,5 +441,5 @@
  *
  */
-NO_TRACE static inline uint64_t tl_read(void)
+_NO_TRACE static inline uint64_t tl_read(void)
 {
 	uint64_t v;
@@ -458,5 +458,5 @@
  *
  */
-NO_TRACE static inline uint64_t tba_read(void)
+_NO_TRACE static inline uint64_t tba_read(void)
 {
 	uint64_t v;
@@ -475,5 +475,5 @@
  *
  */
-NO_TRACE static inline void tba_write(uint64_t v)
+_NO_TRACE static inline void tba_write(uint64_t v)
 {
 	asm volatile (
@@ -493,5 +493,5 @@
  *
  */
-NO_TRACE static inline uint64_t asi_u64_read(asi_t asi, uintptr_t va)
+_NO_TRACE static inline uint64_t asi_u64_read(asi_t asi, uintptr_t va)
 {
 	uint64_t v;
@@ -514,5 +514,5 @@
  *
  */
-NO_TRACE static inline void asi_u64_write(asi_t asi, uintptr_t va, uint64_t v)
+_NO_TRACE static inline void asi_u64_write(asi_t asi, uintptr_t va, uint64_t v)
 {
 	asm volatile (
@@ -526,5 +526,5 @@
 
 /** Flush all valid register windows to memory. */
-NO_TRACE static inline void flushw(void)
+_NO_TRACE static inline void flushw(void)
 {
 	asm volatile ("flushw\n");
@@ -532,5 +532,5 @@
 
 /** Switch to nucleus by setting TL to 1. */
-NO_TRACE static inline void nucleus_enter(void)
+_NO_TRACE static inline void nucleus_enter(void)
 {
 	asm volatile ("wrpr %g0, 1, %tl\n");
@@ -538,5 +538,5 @@
 
 /** Switch from nucleus by setting TL to 0. */
-NO_TRACE static inline void nucleus_leave(void)
+_NO_TRACE static inline void nucleus_leave(void)
 {
 	asm volatile ("wrpr %g0, %g0, %tl\n");
Index: kernel/arch/sparc64/include/arch/barrier.h
===================================================================
--- kernel/arch/sparc64/include/arch/barrier.h	(revision d19b3fcc8f46d58029778b0ba79ad3d796f39697)
+++ kernel/arch/sparc64/include/arch/barrier.h	(revision 62101beefba91c0ff7d989250af8474affc836b5)
@@ -39,5 +39,5 @@
 
 /** Flush Instruction pipeline. */
-NO_TRACE static inline void flush_pipeline(void)
+_NO_TRACE static inline void flush_pipeline(void)
 {
 	unsigned long pc;
@@ -62,5 +62,5 @@
 
 /** Memory Barrier instruction. */
-NO_TRACE static inline void membar(void)
+_NO_TRACE static inline void membar(void)
 {
 	asm volatile (
Index: kernel/arch/sparc64/include/arch/cycle.h
===================================================================
--- kernel/arch/sparc64/include/arch/cycle.h	(revision d19b3fcc8f46d58029778b0ba79ad3d796f39697)
+++ kernel/arch/sparc64/include/arch/cycle.h	(revision 62101beefba91c0ff7d989250af8474affc836b5)
@@ -39,5 +39,5 @@
 #include <trace.h>
 
-NO_TRACE static inline uint64_t get_cycle(void)
+_NO_TRACE static inline uint64_t get_cycle(void)
 {
 	return tick_read();
Index: kernel/arch/sparc64/include/arch/istate.h
===================================================================
--- kernel/arch/sparc64/include/arch/istate.h	(revision d19b3fcc8f46d58029778b0ba79ad3d796f39697)
+++ kernel/arch/sparc64/include/arch/istate.h	(revision 62101beefba91c0ff7d989250af8474affc836b5)
@@ -51,5 +51,5 @@
 #endif /* KERNEL */
 
-NO_TRACE static inline void istate_set_retaddr(istate_t *istate,
+_NO_TRACE static inline void istate_set_retaddr(istate_t *istate,
     uintptr_t retaddr)
 {
@@ -57,15 +57,15 @@
 }
 
-NO_TRACE static inline int istate_from_uspace(istate_t *istate)
+_NO_TRACE static inline int istate_from_uspace(istate_t *istate)
 {
 	return !(istate->tstate & TSTATE_PRIV_BIT);
 }
 
-NO_TRACE static inline uintptr_t istate_get_pc(istate_t *istate)
+_NO_TRACE static inline uintptr_t istate_get_pc(istate_t *istate)
 {
 	return istate->tpc;
 }
 
-NO_TRACE static inline uintptr_t istate_get_fp(istate_t *istate)
+_NO_TRACE static inline uintptr_t istate_get_fp(istate_t *istate)
 {
 	/* TODO */
Index: kernel/arch/sparc64/include/arch/mm/sun4u/tlb.h
===================================================================
--- kernel/arch/sparc64/include/arch/mm/sun4u/tlb.h	(revision d19b3fcc8f46d58029778b0ba79ad3d796f39697)
+++ kernel/arch/sparc64/include/arch/mm/sun4u/tlb.h	(revision 62101beefba91c0ff7d989250af8474affc836b5)
@@ -243,5 +243,5 @@
  * Determine the number of entries in the DMMU's small TLB.
  */
-NO_TRACE static inline uint16_t tlb_dsmall_size(void)
+_NO_TRACE static inline uint16_t tlb_dsmall_size(void)
 {
 	return 16;
@@ -251,5 +251,5 @@
  * Determine the number of entries in each DMMU's big TLB.
  */
-NO_TRACE static inline uint16_t tlb_dbig_size(void)
+_NO_TRACE static inline uint16_t tlb_dbig_size(void)
 {
 	return 512;
@@ -259,5 +259,5 @@
  * Determine the number of entries in the IMMU's small TLB.
  */
-NO_TRACE static inline uint16_t tlb_ismall_size(void)
+_NO_TRACE static inline uint16_t tlb_ismall_size(void)
 {
 	return 16;
@@ -267,5 +267,5 @@
  * Determine the number of entries in the IMMU's big TLB.
  */
-NO_TRACE static inline uint16_t tlb_ibig_size(void)
+_NO_TRACE static inline uint16_t tlb_ibig_size(void)
 {
 	if (((ver_reg_t) ver_read()).impl == IMPL_ULTRASPARCIV_PLUS)
@@ -281,5 +281,5 @@
  * @return		Current value of Primary Context Register.
  */
-NO_TRACE static inline uint64_t mmu_primary_context_read(void)
+_NO_TRACE static inline uint64_t mmu_primary_context_read(void)
 {
 	return asi_u64_read(ASI_DMMU, VA_PRIMARY_CONTEXT_REG);
@@ -290,5 +290,5 @@
  * @param v		New value of Primary Context Register.
  */
-NO_TRACE static inline void mmu_primary_context_write(uint64_t v)
+_NO_TRACE static inline void mmu_primary_context_write(uint64_t v)
 {
 	asi_u64_write(ASI_DMMU, VA_PRIMARY_CONTEXT_REG, v);
@@ -300,5 +300,5 @@
  * @return		Current value of Secondary Context Register.
  */
-NO_TRACE static inline uint64_t mmu_secondary_context_read(void)
+_NO_TRACE static inline uint64_t mmu_secondary_context_read(void)
 {
 	return asi_u64_read(ASI_DMMU, VA_SECONDARY_CONTEXT_REG);
@@ -309,5 +309,5 @@
  * @param v		New value of Primary Context Register.
  */
-NO_TRACE static inline void mmu_secondary_context_write(uint64_t v)
+_NO_TRACE static inline void mmu_secondary_context_write(uint64_t v)
 {
 	asi_u64_write(ASI_DMMU, VA_SECONDARY_CONTEXT_REG, v);
@@ -324,5 +324,5 @@
  * 			Register.
  */
-NO_TRACE static inline uint64_t itlb_data_access_read(size_t entry)
+_NO_TRACE static inline uint64_t itlb_data_access_read(size_t entry)
 {
 	itlb_data_access_addr_t reg;
@@ -338,5 +338,5 @@
  * @param value		Value to be written.
  */
-NO_TRACE static inline void itlb_data_access_write(size_t entry, uint64_t value)
+_NO_TRACE static inline void itlb_data_access_write(size_t entry, uint64_t value)
 {
 	itlb_data_access_addr_t reg;
@@ -355,5 +355,5 @@
  * 			Register.
  */
-NO_TRACE static inline uint64_t dtlb_data_access_read(size_t entry)
+_NO_TRACE static inline uint64_t dtlb_data_access_read(size_t entry)
 {
 	dtlb_data_access_addr_t reg;
@@ -369,5 +369,5 @@
  * @param value		Value to be written.
  */
-NO_TRACE static inline void dtlb_data_access_write(size_t entry, uint64_t value)
+_NO_TRACE static inline void dtlb_data_access_write(size_t entry, uint64_t value)
 {
 	dtlb_data_access_addr_t reg;
@@ -385,5 +385,5 @@
  * @return		Current value of specified IMMU TLB Tag Read Register.
  */
-NO_TRACE static inline uint64_t itlb_tag_read_read(size_t entry)
+_NO_TRACE static inline uint64_t itlb_tag_read_read(size_t entry)
 {
 	itlb_tag_read_addr_t tag;
@@ -400,5 +400,5 @@
  * @return		Current value of specified DMMU TLB Tag Read Register.
  */
-NO_TRACE static inline uint64_t dtlb_tag_read_read(size_t entry)
+_NO_TRACE static inline uint64_t dtlb_tag_read_read(size_t entry)
 {
 	dtlb_tag_read_addr_t tag;
@@ -419,5 +419,5 @@
  * 			Register.
  */
-NO_TRACE static inline uint64_t itlb_data_access_read(int tlb, size_t entry)
+_NO_TRACE static inline uint64_t itlb_data_access_read(int tlb, size_t entry)
 {
 	itlb_data_access_addr_t reg;
@@ -434,5 +434,5 @@
  * @param value		Value to be written.
  */
-NO_TRACE static inline void itlb_data_access_write(int tlb, size_t entry,
+_NO_TRACE static inline void itlb_data_access_write(int tlb, size_t entry,
     uint64_t value)
 {
@@ -454,5 +454,5 @@
  * 			Register.
  */
-NO_TRACE static inline uint64_t dtlb_data_access_read(int tlb, size_t entry)
+_NO_TRACE static inline uint64_t dtlb_data_access_read(int tlb, size_t entry)
 {
 	dtlb_data_access_addr_t reg;
@@ -470,5 +470,5 @@
  * @param value		Value to be written.
  */
-NO_TRACE static inline void dtlb_data_access_write(int tlb, size_t entry,
+_NO_TRACE static inline void dtlb_data_access_write(int tlb, size_t entry,
     uint64_t value)
 {
@@ -489,5 +489,5 @@
  * @return		Current value of specified IMMU TLB Tag Read Register.
  */
-NO_TRACE static inline uint64_t itlb_tag_read_read(int tlb, size_t entry)
+_NO_TRACE static inline uint64_t itlb_tag_read_read(int tlb, size_t entry)
 {
 	itlb_tag_read_addr_t tag;
@@ -506,5 +506,5 @@
  * @return		Current value of specified DMMU TLB Tag Read Register.
  */
-NO_TRACE static inline uint64_t dtlb_tag_read_read(int tlb, size_t entry)
+_NO_TRACE static inline uint64_t dtlb_tag_read_read(int tlb, size_t entry)
 {
 	dtlb_tag_read_addr_t tag;
@@ -522,5 +522,5 @@
  * @param v		Value to be written.
  */
-NO_TRACE static inline void itlb_tag_access_write(uint64_t v)
+_NO_TRACE static inline void itlb_tag_access_write(uint64_t v)
 {
 	asi_u64_write(ASI_IMMU, VA_IMMU_TAG_ACCESS, v);
@@ -532,5 +532,5 @@
  * @return		Current value of IMMU TLB Tag Access Register.
  */
-NO_TRACE static inline uint64_t itlb_tag_access_read(void)
+_NO_TRACE static inline uint64_t itlb_tag_access_read(void)
 {
 	return asi_u64_read(ASI_IMMU, VA_IMMU_TAG_ACCESS);
@@ -541,5 +541,5 @@
  * @param v		Value to be written.
  */
-NO_TRACE static inline void dtlb_tag_access_write(uint64_t v)
+_NO_TRACE static inline void dtlb_tag_access_write(uint64_t v)
 {
 	asi_u64_write(ASI_DMMU, VA_DMMU_TAG_ACCESS, v);
@@ -551,5 +551,5 @@
  * @return 		Current value of DMMU TLB Tag Access Register.
  */
-NO_TRACE static inline uint64_t dtlb_tag_access_read(void)
+_NO_TRACE static inline uint64_t dtlb_tag_access_read(void)
 {
 	return asi_u64_read(ASI_DMMU, VA_DMMU_TAG_ACCESS);
@@ -560,5 +560,5 @@
  * @param v		Value to be written.
  */
-NO_TRACE static inline void itlb_data_in_write(uint64_t v)
+_NO_TRACE static inline void itlb_data_in_write(uint64_t v)
 {
 	asi_u64_write(ASI_ITLB_DATA_IN_REG, 0, v);
@@ -570,5 +570,5 @@
  * @param v		Value to be written.
  */
-NO_TRACE static inline void dtlb_data_in_write(uint64_t v)
+_NO_TRACE static inline void dtlb_data_in_write(uint64_t v)
 {
 	asi_u64_write(ASI_DTLB_DATA_IN_REG, 0, v);
@@ -580,5 +580,5 @@
  * @return		Current content of I-SFSR register.
  */
-NO_TRACE static inline uint64_t itlb_sfsr_read(void)
+_NO_TRACE static inline uint64_t itlb_sfsr_read(void)
 {
 	return asi_u64_read(ASI_IMMU, VA_IMMU_SFSR);
@@ -589,5 +589,5 @@
  * @param v		New value of I-SFSR register.
  */
-NO_TRACE static inline void itlb_sfsr_write(uint64_t v)
+_NO_TRACE static inline void itlb_sfsr_write(uint64_t v)
 {
 	asi_u64_write(ASI_IMMU, VA_IMMU_SFSR, v);
@@ -599,5 +599,5 @@
  * @return		Current content of D-SFSR register.
  */
-NO_TRACE static inline uint64_t dtlb_sfsr_read(void)
+_NO_TRACE static inline uint64_t dtlb_sfsr_read(void)
 {
 	return asi_u64_read(ASI_DMMU, VA_DMMU_SFSR);
@@ -608,5 +608,5 @@
  * @param v		New value of D-SFSR register.
  */
-NO_TRACE static inline void dtlb_sfsr_write(uint64_t v)
+_NO_TRACE static inline void dtlb_sfsr_write(uint64_t v)
 {
 	asi_u64_write(ASI_DMMU, VA_DMMU_SFSR, v);
@@ -618,5 +618,5 @@
  * @return		Current content of D-SFAR register.
  */
-NO_TRACE static inline uint64_t dtlb_sfar_read(void)
+_NO_TRACE static inline uint64_t dtlb_sfar_read(void)
 {
 	return asi_u64_read(ASI_DMMU, VA_DMMU_SFAR);
@@ -631,5 +631,5 @@
  * @param page		Address which is on the page to be demapped.
  */
-NO_TRACE static inline void itlb_demap(int type, int context_encoding, uintptr_t page)
+_NO_TRACE static inline void itlb_demap(int type, int context_encoding, uintptr_t page)
 {
 	tlb_demap_addr_t da;
@@ -657,5 +657,5 @@
  * @param page		Address which is on the page to be demapped.
  */
-NO_TRACE static inline void dtlb_demap(int type, int context_encoding, uintptr_t page)
+_NO_TRACE static inline void dtlb_demap(int type, int context_encoding, uintptr_t page)
 {
 	tlb_demap_addr_t da;
Index: kernel/arch/sparc64/include/arch/mm/sun4v/tlb.h
===================================================================
--- kernel/arch/sparc64/include/arch/mm/sun4v/tlb.h	(revision d19b3fcc8f46d58029778b0ba79ad3d796f39697)
+++ kernel/arch/sparc64/include/arch/mm/sun4v/tlb.h	(revision 62101beefba91c0ff7d989250af8474affc836b5)
@@ -88,5 +88,5 @@
  * @return	Current value of Primary Context Register.
  */
-NO_TRACE static inline uint64_t mmu_primary_context_read(void)
+_NO_TRACE static inline uint64_t mmu_primary_context_read(void)
 {
 	return asi_u64_read(ASI_PRIMARY_CONTEXT_REG, VA_PRIMARY_CONTEXT_REG);
@@ -97,5 +97,5 @@
  * @param v	New value of Primary Context Register.
  */
-NO_TRACE static inline void mmu_primary_context_write(uint64_t v)
+_NO_TRACE static inline void mmu_primary_context_write(uint64_t v)
 {
 	asi_u64_write(ASI_PRIMARY_CONTEXT_REG, VA_PRIMARY_CONTEXT_REG, v);
@@ -106,5 +106,5 @@
  * @return	Current value of Secondary Context Register.
  */
-NO_TRACE static inline uint64_t mmu_secondary_context_read(void)
+_NO_TRACE static inline uint64_t mmu_secondary_context_read(void)
 {
 	return asi_u64_read(ASI_SECONDARY_CONTEXT_REG, VA_SECONDARY_CONTEXT_REG);
@@ -115,5 +115,5 @@
  * @param v	New value of Secondary Context Register.
  */
-NO_TRACE static inline void mmu_secondary_context_write(uint64_t v)
+_NO_TRACE static inline void mmu_secondary_context_write(uint64_t v)
 {
 	asi_u64_write(ASI_SECONDARY_CONTEXT_REG, VA_SECONDARY_CONTEXT_REG, v);
@@ -126,5 +126,5 @@
  * @param mmu_flag	MMU_FLAG_DTLB, MMU_FLAG_ITLB or a combination of both
  */
-NO_TRACE static inline void mmu_demap_ctx(int context, int mmu_flag)
+_NO_TRACE static inline void mmu_demap_ctx(int context, int mmu_flag)
 {
 	__hypercall_fast4(MMU_DEMAP_CTX, 0, 0, context, mmu_flag);
@@ -138,5 +138,5 @@
  * @param mmu_flag	MMU_FLAG_DTLB, MMU_FLAG_ITLB or a combination of both
  */
-NO_TRACE static inline void mmu_demap_page(uintptr_t vaddr, int context, int mmu_flag)
+_NO_TRACE static inline void mmu_demap_page(uintptr_t vaddr, int context, int mmu_flag)
 {
 	__hypercall_fast5(MMU_DEMAP_PAGE, 0, 0, vaddr, context, mmu_flag);
Index: kernel/arch/sparc64/include/arch/sun4u/asm.h
===================================================================
--- kernel/arch/sparc64/include/arch/sun4u/asm.h	(revision d19b3fcc8f46d58029778b0ba79ad3d796f39697)
+++ kernel/arch/sparc64/include/arch/sun4u/asm.h	(revision 62101beefba91c0ff7d989250af8474affc836b5)
@@ -43,5 +43,5 @@
  *
  */
-NO_TRACE static inline uint64_t ver_read(void)
+_NO_TRACE static inline uint64_t ver_read(void)
 {
 	uint64_t v;
Index: kernel/arch/sparc64/include/arch/sun4u/cpu.h
===================================================================
--- kernel/arch/sparc64/include/arch/sun4u/cpu.h	(revision d19b3fcc8f46d58029778b0ba79ad3d796f39697)
+++ kernel/arch/sparc64/include/arch/sun4u/cpu.h	(revision 62101beefba91c0ff7d989250af8474affc836b5)
@@ -76,5 +76,5 @@
  *
  */
-NO_TRACE static inline uint32_t read_mid(void)
+_NO_TRACE static inline uint32_t read_mid(void)
 {
 	uint64_t icbus_config = asi_u64_read(ASI_ICBUS_CONFIG, 0);