Index: kernel/arch/ppc32/src/asm.S =================================================================== --- kernel/arch/ppc32/src/asm.S (revision 1b20da07baaa3e3c424f62c927274e676e4295cd) +++ kernel/arch/ppc32/src/asm.S (revision 615e83d68dc1cfdb51a3e2557d4776a37010a7ca) @@ -40,32 +40,32 @@ * r5 = entry */ - + /* Disable interrupts */ - + mfmsr r31 rlwinm r31, r31, 0, 17, 15 mtmsr r31 isync - + /* Set entry point */ - + mtsrr0 r5 - + /* Set privileged state, enable interrupts */ - + ori r31, r31, MSR_PR ori r31, r31, MSR_EE mtsrr1 r31 - + /* Set stack */ - + mr sp, r4 - + /* %r6 is defined to hold pcb_ptr - set it to 0 */ - + xor r6, r6, r6 - + /* Jump to userspace */ - + rfi FUNCTION_END(userspace_asm) @@ -73,10 +73,10 @@ SYMBOL(iret) /* Disable interrupts */ - + mfmsr r31 rlwinm r31, r31, 0, 17, 15 mtmsr r31 isync - + lwz r0, ISTATE_OFFSET_R0(sp) lwz r2, ISTATE_OFFSET_R2(sp) @@ -109,36 +109,36 @@ lwz r30, ISTATE_OFFSET_R30(sp) lwz r31, ISTATE_OFFSET_R31(sp) - + lwz r12, ISTATE_OFFSET_CR(sp) mtcr r12 - + lwz r12, ISTATE_OFFSET_PC(sp) mtsrr0 r12 - + lwz r12, ISTATE_OFFSET_SRR1(sp) mtsrr1 r12 - + lwz r12, ISTATE_OFFSET_LR(sp) mtlr r12 - + lwz r12, ISTATE_OFFSET_CTR(sp) mtctr r12 - + lwz r12, ISTATE_OFFSET_XER(sp) mtxer r12 - + lwz r12, ISTATE_OFFSET_R12(sp) lwz sp, ISTATE_OFFSET_SP(sp) - + rfi SYMBOL(iret_syscall) /* Disable interrupts */ - + mfmsr r31 rlwinm r31, r31, 0, 17, 15 mtmsr r31 isync - + lwz r0, ISTATE_OFFSET_R0(sp) lwz r2, ISTATE_OFFSET_R2(sp) @@ -170,26 +170,26 @@ lwz r30, ISTATE_OFFSET_R30(sp) lwz r31, ISTATE_OFFSET_R31(sp) - + lwz r12, ISTATE_OFFSET_CR(sp) mtcr r12 - + lwz r12, ISTATE_OFFSET_PC(sp) mtsrr0 r12 - + lwz r12, ISTATE_OFFSET_SRR1(sp) mtsrr1 r12 - + lwz r12, ISTATE_OFFSET_LR(sp) mtlr r12 - + lwz r12, ISTATE_OFFSET_CTR(sp) mtctr r12 - + lwz r12, ISTATE_OFFSET_XER(sp) mtxer r12 - + lwz r12, ISTATE_OFFSET_R12(sp) lwz sp, ISTATE_OFFSET_SP(sp) - + rfi @@ -200,11 +200,11 @@ addi r4, r4, -4 beq 2f - + andi. r0, r6, 3 mtctr r7 bne 5f - + 1: - + lwz r7, 4(r4) lwzu r8, 8(r4) @@ -212,18 +212,18 @@ stwu r8, 8(r6) bdnz 1b - + andi. r5, r5, 7 - + 2: - + cmplwi 0, r5, 4 blt 3f - + lwzu r0, 4(r4) addi r5, r5, -4 stwu r0, 4(r6) - + 3: - + cmpwi 0, r5, 0 beqlr @@ -231,19 +231,19 @@ addi r4, r4, 3 addi r6, r6, 3 - + 4: - + lbzu r0, 1(r4) stbu r0, 1(r6) bdnz 4b blr - + 5: - + subfic r0, r0, 4 mtctr r0 - + 6: - + lbz r7, 4(r4) addi r4, r4, 1 Index: kernel/arch/ppc32/src/boot/boot.S =================================================================== --- kernel/arch/ppc32/src/boot/boot.S (revision 1b20da07baaa3e3c424f62c927274e676e4295cd) +++ kernel/arch/ppc32/src/boot/boot.S (revision 615e83d68dc1cfdb51a3e2557d4776a37010a7ca) @@ -35,16 +35,16 @@ SYMBOL(kernel_image_start) # load temporal kernel stack - + lis sp, kernel_stack@ha addi sp, sp, kernel_stack@l - + # set kernel stack for interrupt handling - + mr r31, sp subis r31, r31, 0x8000 mtsprg0 r31 - + # r3 contains physical address of bootinfo_t - + addis r3, r3, 0x8000 bl ppc32_pre_main Index: kernel/arch/ppc32/src/context.S =================================================================== --- kernel/arch/ppc32/src/context.S (revision 1b20da07baaa3e3c424f62c927274e676e4295cd) +++ kernel/arch/ppc32/src/context.S (revision 615e83d68dc1cfdb51a3e2557d4776a37010a7ca) @@ -55,11 +55,11 @@ stw r30, CONTEXT_OFFSET_R30(r3) stw r31, CONTEXT_OFFSET_R31(r3) - + mflr r4 stw r4, CONTEXT_OFFSET_PC(r3) - + mfcr r4 stw r4, CONTEXT_OFFSET_CR(r3) - + # context_save returns 1 li r3, 1 @@ -89,11 +89,11 @@ lwz r30, CONTEXT_OFFSET_R30(r3) lwz r31, CONTEXT_OFFSET_R31(r3) - + lwz r4, CONTEXT_OFFSET_CR(r3) mtcr r4 - + lwz r4, CONTEXT_OFFSET_PC(r3) mtlr r4 - + # context_restore returns 0 li r3, 0 Index: kernel/arch/ppc32/src/cpu/cpu.c =================================================================== --- kernel/arch/ppc32/src/cpu/cpu.c (revision 1b20da07baaa3e3c424f62c927274e676e4295cd) +++ kernel/arch/ppc32/src/cpu/cpu.c (revision 615e83d68dc1cfdb51a3e2557d4776a37010a7ca) @@ -54,5 +54,5 @@ { const char *name; - + switch (cpu->arch.version) { case 8: @@ -71,5 +71,5 @@ name = "unknown"; } - + printf("cpu%u: version=%" PRIu16" (%s), revision=%" PRIu16 "\n", cpu->id, cpu->arch.version, name, cpu->arch.revision); Index: kernel/arch/ppc32/src/drivers/pic.c =================================================================== --- kernel/arch/ppc32/src/drivers/pic.c (revision 1b20da07baaa3e3c424f62c927274e676e4295cd) +++ kernel/arch/ppc32/src/drivers/pic.c (revision 615e83d68dc1cfdb51a3e2557d4776a37010a7ca) @@ -55,5 +55,5 @@ pic[PIC_MASK_HIGH] = pic[PIC_MASK_HIGH] | (1 << (intnum - 32)); } - + } @@ -85,14 +85,14 @@ if (pic) { uint32_t pending; - + pending = pic[PIC_PENDING_LOW]; if (pending != 0) return fnzb32(pending); - + pending = pic[PIC_PENDING_HIGH]; if (pending != 0) return fnzb32(pending) + 32; } - + return 255; } Index: kernel/arch/ppc32/src/exception.S =================================================================== --- kernel/arch/ppc32/src/exception.S (revision 1b20da07baaa3e3c424f62c927274e676e4295cd) +++ kernel/arch/ppc32/src/exception.S (revision 615e83d68dc1cfdb51a3e2557d4776a37010a7ca) @@ -38,29 +38,29 @@ .macro CONTEXT_STORE - + # save r12 in SPRG1, backup CR in r12 # save SP in SPRG2 - + mtsprg1 r12 mfcr r12 mtsprg2 sp - + # check whether the previous mode was user or kernel - + mfsrr1 sp # use sp as a temporary register to hold SRR1 andi. sp, sp, MSR_PR bne 1f # previous mode was kernel - + mfsprg2 sp subis sp, sp, 0x8000 b 2f - + 1: # previous mode was user - + mfsprg0 sp 2: - + subi sp, sp, ALIGN_UP(ISTATE_SIZE, STACK_ALIGNMENT) stw r0, ISTATE_OFFSET_R0(sp) @@ -94,28 +94,28 @@ stw r30, ISTATE_OFFSET_R30(sp) stw r31, ISTATE_OFFSET_R31(sp) - + stw r12, ISTATE_OFFSET_CR(sp) - + mfsrr0 r12 stw r12, ISTATE_OFFSET_PC(sp) - + mfsrr1 r12 stw r12, ISTATE_OFFSET_SRR1(sp) - + mflr r12 stw r12, ISTATE_OFFSET_LR(sp) - + mfctr r12 stw r12, ISTATE_OFFSET_CTR(sp) - + mfxer r12 stw r12, ISTATE_OFFSET_XER(sp) - + mfdar r12 stw r12, ISTATE_OFFSET_DAR(sp) - + mfsprg1 r12 stw r12, ISTATE_OFFSET_R12(sp) - + mfsprg2 r12 stw r12, ISTATE_OFFSET_SP(sp) @@ -129,5 +129,5 @@ SYMBOL(exc_system_reset) CONTEXT_STORE - + li r3, 0 b jump_to_kernel @@ -136,5 +136,5 @@ SYMBOL(exc_machine_check) CONTEXT_STORE - + li r3, 1 b jump_to_kernel @@ -143,5 +143,5 @@ SYMBOL(exc_data_storage) CONTEXT_STORE - + li r3, 2 b jump_to_kernel @@ -150,5 +150,5 @@ SYMBOL(exc_instruction_storage) CONTEXT_STORE - + li r3, 3 b jump_to_kernel @@ -157,5 +157,5 @@ SYMBOL(exc_external) CONTEXT_STORE - + li r3, 4 b jump_to_kernel @@ -164,5 +164,5 @@ SYMBOL(exc_alignment) CONTEXT_STORE - + li r3, 5 b jump_to_kernel @@ -171,5 +171,5 @@ SYMBOL(exc_program) CONTEXT_STORE - + li r3, 6 b jump_to_kernel @@ -178,5 +178,5 @@ SYMBOL(exc_fp_unavailable) CONTEXT_STORE - + li r3, 7 b jump_to_kernel @@ -185,5 +185,5 @@ SYMBOL(exc_decrementer) CONTEXT_STORE - + li r3, 8 b jump_to_kernel @@ -192,5 +192,5 @@ SYMBOL(exc_reserved0) CONTEXT_STORE - + li r3, 9 b jump_to_kernel @@ -199,5 +199,5 @@ SYMBOL(exc_reserved1) CONTEXT_STORE - + li r3, 10 b jump_to_kernel @@ -206,5 +206,5 @@ SYMBOL(exc_syscall) CONTEXT_STORE - + b jump_to_kernel_syscall @@ -212,5 +212,5 @@ SYMBOL(exc_trace) CONTEXT_STORE - + li r3, 12 b jump_to_kernel @@ -219,5 +219,5 @@ SYMBOL(exc_itlb_miss) CONTEXT_STORE - + li r3, 13 b jump_to_kernel @@ -226,5 +226,5 @@ SYMBOL(exc_dtlb_miss_load) CONTEXT_STORE - + li r3, 14 b jump_to_kernel @@ -233,5 +233,5 @@ SYMBOL(exc_dtlb_miss_store) CONTEXT_STORE - + li r3, 15 b jump_to_kernel @@ -244,5 +244,5 @@ # Previous mode was kernel. # We can construct a proper frame linkage. - + mfsrr0 r12 stw r12, ISTATE_OFFSET_LR_FRAME(sp) @@ -265,8 +265,8 @@ ori r12, r12, (MSR_IR | MSR_DR) mtsrr1 r12 - + addis sp, sp, 0x8000 mr r4, sp - + rfi @@ -275,5 +275,5 @@ addi r12, r12, syscall_handler@l mtsrr0 r12 - + lis r12, iret_syscall@ha addi r12, r12, iret_syscall@l @@ -286,5 +286,5 @@ ori r12, r12, (MSR_IR | MSR_DR | MSR_EE) mtsrr1 r12 - + addis sp, sp, 0x8000 rfi Index: kernel/arch/ppc32/src/fpu_context.S =================================================================== --- kernel/arch/ppc32/src/fpu_context.S (revision 1b20da07baaa3e3c424f62c927274e676e4295cd) +++ kernel/arch/ppc32/src/fpu_context.S (revision 615e83d68dc1cfdb51a3e2557d4776a37010a7ca) @@ -106,8 +106,8 @@ FUNCTION_BEGIN(fpu_context_save) FPU_CONTEXT_STORE r3 - + mffs fr0 stfd fr0, FPU_CONTEXT_OFFSET_FPSCR(r3) - + blr FUNCTION_END(fpu_context_save) @@ -116,7 +116,7 @@ lfd fr0, FPU_CONTEXT_OFFSET_FPSCR(r3) mtfsf 0xff, fr0 - + FPU_CONTEXT_LOAD r3 - + blr FUNCTION_END(fpu_context_restore) @@ -125,12 +125,12 @@ mfmsr r0 ori r0, r0, MSR_FP - + # Disable FPU exceptions li r3, MSR_FE0 | MSR_FE1 andc r0, r0, r3 - + mtmsr r0 isync - + blr FUNCTION_END(fpu_init) Index: kernel/arch/ppc32/src/interrupt.c =================================================================== --- kernel/arch/ppc32/src/interrupt.c (revision 1b20da07baaa3e3c424f62c927274e676e4295cd) +++ kernel/arch/ppc32/src/interrupt.c (revision 615e83d68dc1cfdb51a3e2557d4776a37010a7ca) @@ -66,41 +66,41 @@ log_printf("r0 =%0#10" PRIx32 "\tr1 =%0#10" PRIx32 "\t" "r2 =%0#10" PRIx32 "\n", istate->r0, istate->sp, istate->r2); - + log_printf("r3 =%0#10" PRIx32 "\tr4 =%0#10" PRIx32 "\t" "r5 =%0#10" PRIx32 "\n", istate->r3, istate->r4, istate->r5); - + log_printf("r6 =%0#10" PRIx32 "\tr7 =%0#10" PRIx32 "\t" "r8 =%0#10" PRIx32 "\n", istate->r6, istate->r7, istate->r8); - + log_printf("r9 =%0#10" PRIx32 "\tr10=%0#10" PRIx32 "\t" "r11=%0#10" PRIx32 "\n", istate->r9, istate->r10, istate->r11); - + log_printf("r12=%0#10" PRIx32 "\tr13=%0#10" PRIx32 "\t" "r14=%0#10" PRIx32 "\n", istate->r12, istate->r13, istate->r14); - + log_printf("r15=%0#10" PRIx32 "\tr16=%0#10" PRIx32 "\t" "r17=%0#10" PRIx32 "\n", istate->r15, istate->r16, istate->r17); - + log_printf("r18=%0#10" PRIx32 "\tr19=%0#10" PRIx32 "\t" "r20=%0#10" PRIx32 "\n", istate->r18, istate->r19, istate->r20); - + log_printf("r21=%0#10" PRIx32 "\tr22=%0#10" PRIx32 "\t" "r23=%0#10" PRIx32 "\n", istate->r21, istate->r22, istate->r23); - + log_printf("r24=%0#10" PRIx32 "\tr25=%0#10" PRIx32 "\t" "r26=%0#10" PRIx32 "\n", istate->r24, istate->r25, istate->r26); - + log_printf("r27=%0#10" PRIx32 "\tr28=%0#10" PRIx32 "\t" "r29=%0#10" PRIx32 "\n", istate->r27, istate->r28, istate->r29); - + log_printf("r30=%0#10" PRIx32 "\tr31=%0#10" PRIx32 "\n", istate->r30, istate->r31); - + log_printf("cr =%0#10" PRIx32 "\tpc =%0#10" PRIx32 "\t" "lr =%0#10" PRIx32 "\n", istate->cr, istate->pc, istate->lr); - + log_printf("ctr=%0#10" PRIx32 "\txer=%0#10" PRIx32 "\t" "dar=%0#10" PRIx32 "\n", istate->ctr, istate->xer, istate->dar); - + log_printf("srr1=%0#10" PRIx32 "\n", istate->srr1); } @@ -119,5 +119,5 @@ * The IRQ handler was found. */ - + if (irq->preack) { /* Acknowledge the interrupt before processing */ @@ -125,12 +125,12 @@ irq->cir(irq->cir_arg, irq->inr); } - + irq->handler(irq); - + if (!irq->preack) { if (irq->cir) irq->cir(irq->cir_arg, irq->inr); } - + irq_spinlock_unlock(&irq->lock, false); } else { Index: kernel/arch/ppc32/src/mm/as.c =================================================================== --- kernel/arch/ppc32/src/mm/as.c (revision 1b20da07baaa3e3c424f62c927274e676e4295cd) +++ kernel/arch/ppc32/src/mm/as.c (revision 615e83d68dc1cfdb51a3e2557d4776a37010a7ca) @@ -56,9 +56,9 @@ { uint32_t sr; - + /* Lower 2 GB, user and supervisor access */ for (sr = 0; sr < 8; sr++) sr_set(0x6000, as->asid, sr); - + /* Upper 2 GB, only supervisor access */ for (sr = 8; sr < 16; sr++) Index: kernel/arch/ppc32/src/mm/frame.c =================================================================== --- kernel/arch/ppc32/src/mm/frame.c (revision 1b20da07baaa3e3c424f62c927274e676e4295cd) +++ kernel/arch/ppc32/src/mm/frame.c (revision 615e83d68dc1cfdb51a3e2557d4776a37010a7ca) @@ -45,5 +45,5 @@ { printf("[base ] [size ]\n"); - + size_t i; for (i = 0; i < memmap.cnt; i++) { @@ -57,5 +57,5 @@ pfn_t minconf = 2; size_t i; - + for (i = 0; i < memmap.cnt; i++) { /* To be safe, make the available zone possibly smaller */ @@ -64,5 +64,5 @@ size_t size = ALIGN_DOWN(memmap.zones[i].size - (base - ((uintptr_t) memmap.zones[i].start)), FRAME_SIZE); - + if (!frame_adjust_zone_bounds(low, &base, &size)) return; @@ -86,5 +86,5 @@ } } - + } @@ -92,12 +92,12 @@ { frame_common_arch_init(true); - + /* First is exception vector, second is 'implementation specific', third and fourth is reserved, other contain real mode code */ frame_mark_unavailable(0, 8); - + /* Mark the Page Hash Table frames as unavailable */ uint32_t sdr1 = sdr1_get(); - + // FIXME: compute size of PHT exactly frame_mark_unavailable(ADDR2PFN(sdr1 & 0xffff000), 16); Index: kernel/arch/ppc32/src/mm/pht.c =================================================================== --- kernel/arch/ppc32/src/mm/pht.c (revision 1b20da07baaa3e3c424f62c927274e676e4295cd) +++ kernel/arch/ppc32/src/mm/pht.c (revision 615e83d68dc1cfdb51a3e2557d4776a37010a7ca) @@ -93,11 +93,11 @@ uint32_t page = (vaddr >> 12) & 0xffff; uint32_t api = (vaddr >> 22) & 0x3f; - + uint32_t vsid = sr_get(vaddr); uint32_t sdr1 = sdr1_get(); - + // FIXME: compute size of PHT exactly phte_t *phte = (phte_t *) PA2KA(sdr1 & 0xffff0000); - + /* Primary hash (xor) */ uint32_t h = 0; @@ -106,5 +106,5 @@ uint32_t i; bool found = false; - + /* Find colliding PTE in PTEG */ for (i = 0; i < 8; i++) { @@ -117,5 +117,5 @@ } } - + if (!found) { /* Find unused PTE in PTEG */ @@ -127,9 +127,9 @@ } } - + if (!found) { /* Secondary hash (not) */ uint32_t base2 = (~hash & 0x3ff) << 3; - + /* Find colliding PTE in PTEG */ for (i = 0; i < 8; i++) { @@ -144,5 +144,5 @@ } } - + if (!found) { /* Find unused PTE in PTEG */ @@ -156,9 +156,9 @@ } } - + if (!found) i = RANDI(seed) % 8; } - + phte[base + i].v = 1; phte[base + i].vsid = vsid; @@ -181,14 +181,14 @@ { uintptr_t badvaddr; - + if (n == VECTOR_DATA_STORAGE) badvaddr = istate->dar; else badvaddr = istate->pc; - + pte_t pte; bool found = find_mapping_and_check(AS, badvaddr, PF_ACCESS_READ /* FIXME */, istate, &pte); - + if (found) { /* Record access to PTE */ @@ -201,8 +201,8 @@ { uint32_t sdr1 = sdr1_get(); - + // FIXME: compute size of PHT exactly phte_t *phte = (phte_t *) PA2KA(sdr1 & 0xffff0000); - + // FIXME: this invalidates all PHT entries, // which is an overkill, invalidate only Index: kernel/arch/ppc32/src/mm/tlb.c =================================================================== --- kernel/arch/ppc32/src/mm/tlb.c (revision 1b20da07baaa3e3c424f62c927274e676e4295cd) +++ kernel/arch/ppc32/src/mm/tlb.c (revision 615e83d68dc1cfdb51a3e2557d4776a37010a7ca) @@ -42,5 +42,5 @@ ptehi_t ptehi; ptelo_t ptelo; - + asm volatile ( "mfspr %[tlbmiss], 980\n" @@ -51,15 +51,15 @@ [ptelo] "=r" (ptelo) ); - + uint32_t badvaddr = tlbmiss & 0xfffffffc; uint32_t physmem = physmem_top(); - + if ((badvaddr < PA2KA(0)) || (badvaddr >= PA2KA(physmem))) return; // FIXME - + ptelo.rpn = KA2PA(badvaddr) >> 12; ptelo.wimg = 0; ptelo.pp = 2; // FIXME - + uint32_t index = 0; asm volatile ( @@ -84,5 +84,5 @@ "sync\n" ); - + for (unsigned int i = 0; i < 0x00040000; i += 0x00001000) { asm volatile ( @@ -91,5 +91,5 @@ ); } - + asm volatile ( "eieio\n" @@ -143,8 +143,8 @@ { uint32_t sr; - + for (sr = 0; sr < 16; sr++) { uint32_t vsid = sr_get(sr << 28); - + printf("sr[%02" PRIu32 "]: vsid=%#0" PRIx32 " (asid=%" PRIu32 ")" "%s%s\n", sr, vsid & UINT32_C(0x00ffffff), @@ -153,15 +153,15 @@ ((vsid >> 29) & 1) ? " user" : ""); } - + uint32_t upper; uint32_t lower; uint32_t mask; uint32_t length; - + PRINT_BAT("ibat[0]", 528, 529); PRINT_BAT("ibat[1]", 530, 531); PRINT_BAT("ibat[2]", 532, 533); PRINT_BAT("ibat[3]", 534, 535); - + PRINT_BAT("dbat[0]", 536, 537); PRINT_BAT("dbat[1]", 538, 539); Index: kernel/arch/ppc32/src/ppc32.c =================================================================== --- kernel/arch/ppc32/src/ppc32.c (revision 1b20da07baaa3e3c424f62c927274e676e4295cd) +++ kernel/arch/ppc32/src/ppc32.c (revision 615e83d68dc1cfdb51a3e2557d4776a37010a7ca) @@ -91,5 +91,5 @@ bootinfo->taskmap.tasks[i].name); } - + /* Copy physical memory map. */ memmap.total = bootinfo->memmap.total; @@ -99,9 +99,9 @@ memmap.zones[i].size = bootinfo->memmap.zones[i].size; } - + /* Copy boot allocations info. */ ballocs.base = bootinfo->ballocs.base; ballocs.size = bootinfo->ballocs.size; - + /* Copy OFW tree. */ ofw_tree_init(bootinfo->ofw_root); @@ -112,5 +112,5 @@ /* Initialize dispatch table */ interrupt_init(); - + ofw_tree_node_t *cpus_node; ofw_tree_node_t *cpu_node; @@ -144,17 +144,17 @@ uint32_t fb_scanline = 0; unsigned int visual = VISUAL_UNKNOWN; - + ofw_tree_property_t *prop = ofw_tree_getprop(node, "address"); if ((prop) && (prop->value)) fb_addr = *((uintptr_t *) prop->value); - + prop = ofw_tree_getprop(node, "width"); if ((prop) && (prop->value)) fb_width = *((uint32_t *) prop->value); - + prop = ofw_tree_getprop(node, "height"); if ((prop) && (prop->value)) fb_height = *((uint32_t *) prop->value); - + prop = ofw_tree_getprop(node, "depth"); if ((prop) && (prop->value)) { @@ -180,9 +180,9 @@ } } - + prop = ofw_tree_getprop(node, "linebytes"); if ((prop) && (prop->value)) fb_scanline = *((uint32_t *) prop->value); - + if ((fb_addr) && (fb_width > 0) && (fb_height > 0) && (fb_scanline > 0) && (visual != VISUAL_UNKNOWN)) { @@ -195,10 +195,10 @@ .visual = visual, }; - + outdev_t *fbdev = fb_init(&fb_prop); if (fbdev) stdout_wire(fbdev); } - + return true; } @@ -213,8 +213,8 @@ /* Map OFW information into sysinfo */ ofw_sysinfo_map(); - + /* Initialize IRQ routing */ irq_init(IRQ_COUNT, IRQ_COUNT); - + /* Merge all zones to 1 big zone */ zone_merge_all(); @@ -225,14 +225,14 @@ { ofw_pci_reg_t *assigned_address = NULL; - + ofw_tree_property_t *prop = ofw_tree_getprop(node, "assigned-addresses"); if ((prop) && (prop->value)) assigned_address = ((ofw_pci_reg_t *) prop->value); - + if (assigned_address) { /* Initialize PIC */ pic_init(assigned_address[0].addr, PAGE_SIZE, &pic_cir, &pic_cir_arg); - + #ifdef CONFIG_MAC_KBD uintptr_t pa = assigned_address[0].addr + 0x16000; @@ -240,8 +240,8 @@ size_t offset = pa - aligned_addr; size_t size = 2 * PAGE_SIZE; - + cuda_t *cuda = (cuda_t *) (km_map(aligned_addr, offset + size, PAGE_WRITE | PAGE_NOT_CACHEABLE) + offset); - + /* Initialize I/O controller */ cuda_instance_t *cuda_instance = @@ -256,5 +256,5 @@ } } - + /* * This is the necessary evil until the userspace driver is entirely @@ -266,5 +266,5 @@ #endif } - + /* Consider only a single device for now */ return false; @@ -299,5 +299,5 @@ kernel_uarg->uspace_stack_size - SP_DELTA, (uintptr_t) kernel_uarg->uspace_entry); - + /* Unreachable */ while (true); Index: kernel/arch/ppc32/src/proc/scheduler.c =================================================================== --- kernel/arch/ppc32/src/proc/scheduler.c (revision 1b20da07baaa3e3c424f62c927274e676e4295cd) +++ kernel/arch/ppc32/src/proc/scheduler.c (revision 615e83d68dc1cfdb51a3e2557d4776a37010a7ca) @@ -52,5 +52,5 @@ { tlb_invalidate_all(); - + asm volatile ( "mtsprg0 %[ksp]\n"