Index: kernel/arch/arm32/Makefile.inc
===================================================================
--- kernel/arch/arm32/Makefile.inc	(revision a640bc16cd3d7e9a79be3f918bb85b4f75d7d096)
+++ kernel/arch/arm32/Makefile.inc	(revision 5fcd5372fa4cc52bb3d6d189df950427675f6acd)
@@ -33,5 +33,5 @@
 ATSIGN = %
 
-GCC_CFLAGS += -fno-omit-frame-pointer -mapcs-frame -march=$(subst _,-,$(PROCESSOR)) -mno-unaligned-access
+GCC_CFLAGS += -fno-omit-frame-pointer -mapcs-frame -march=$(subst _,-,$(PROCESSOR_ARCH)) -mno-unaligned-access
 
 ifeq ($(MACHINE),beagleboardxm)
Index: kernel/arch/arm32/include/asm.h
===================================================================
--- kernel/arch/arm32/include/asm.h	(revision a640bc16cd3d7e9a79be3f918bb85b4f75d7d096)
+++ kernel/arch/arm32/include/asm.h	(revision 5fcd5372fa4cc52bb3d6d189df950427675f6acd)
@@ -48,11 +48,17 @@
  * ARM920T has custom coprocessor action to do the same. See ARM920T Technical
  * Reference Manual ch 4.9 p. 4-23 (103 in the PDF)
+ * ARM926EJ-S uses the same coprocessor instruction as ARM920T. See ARM926EJ-S
+ * chapter 2.3.8 p.2-22 (52 in the PDF)
+ *
+ * @note Although mcr p15, 0, R0, c7, c0, 4 is defined in ARM Architecture
+ * reference manual for armv4/5 CP15 implementation is mandatory only for
+ * armv6+.
  */
 NO_TRACE static inline void cpu_sleep(void)
 {
-#ifdef PROCESSOR_armv7_a
-	asm volatile ( "wfe" :: );
-#elif defined(MACHINE_gta02)
-	asm volatile ( "mcr p15,0,R0,c7,c0,4" :: );
+#ifdef PROCESSOR_ARCH_armv7_a
+	asm volatile ( "wfe" );
+#elif defined(PROCESSOR_ARCH_armv6) | defined(PROCESSOR_arm926ej_s) | defined(PROCESSOR_arm920t)
+	asm volatile ( "mcr p15, 0, R0, c7, c0, 4" );
 #endif
 }
Index: kernel/arch/arm32/include/barrier.h
===================================================================
--- kernel/arch/arm32/include/barrier.h	(revision a640bc16cd3d7e9a79be3f918bb85b4f75d7d096)
+++ kernel/arch/arm32/include/barrier.h	(revision 5fcd5372fa4cc52bb3d6d189df950427675f6acd)
@@ -60,9 +60,23 @@
 #define read_barrier()    asm volatile ("dsb" ::: "memory")
 #define write_barrier()   asm volatile ("dsb st" ::: "memory")
+#elif defined PROCESSOR_ARCH_armv6
+/* ARMv6- use system control coprocessor (CP15) for memory barrier instructions.
+ * Although at least mcr p15, 0, r0, c7, c10, 4 is mentioned in earlier archs,
+ * CP15 implementation is mandatory only for armv6+.
+ */
+#define memory_barrier()  asm volatile ("ldr r0, =0\nmcr p15, 0, r0, c7, c10, 5" ::: "r0", "memory")
+#define read_barrier()    asm volatile ("ldr r0, =0\nmcr p15, 0, r0, c7, c10, 4" ::: "r0", "memory")
+#define write_barrier()   read_barrier()
 #else
+/* Older manuals mention syscalls as a way to implement cache coherency and
+ * barriers. See for example ARM Architecture Reference Manual Version D
+ * chapter 2.7.4 Prefetching and self-modifying code (p. A2-28)
+ */
+// TODO implement on per PROCESSOR basis
 #define memory_barrier()  asm volatile ("" ::: "memory")
 #define read_barrier()    asm volatile ("" ::: "memory")
 #define write_barrier()   asm volatile ("" ::: "memory")
 #endif
+
 /*
  * There are multiple ways ICache can be implemented on ARM machines. Namely
Index: kernel/arch/arm32/include/mm/frame.h
===================================================================
--- kernel/arch/arm32/include/mm/frame.h	(revision a640bc16cd3d7e9a79be3f918bb85b4f75d7d096)
+++ kernel/arch/arm32/include/mm/frame.h	(revision 5fcd5372fa4cc52bb3d6d189df950427675f6acd)
@@ -47,9 +47,18 @@
 
 #ifdef MACHINE_gta02
+
+#define PHYSMEM_START_ADDR       0x30008000
 #define BOOT_PAGE_TABLE_ADDRESS  0x30010000
+
 #elif defined MACHINE_beagleboardxm
+
+#define PHYSMEM_START_ADDR       0x80000000
 #define BOOT_PAGE_TABLE_ADDRESS  0x80008000
+
 #else
+
+#define PHYSMEM_START_ADDR       0x00000000
 #define BOOT_PAGE_TABLE_ADDRESS  0x00008000
+
 #endif
 
@@ -57,11 +66,4 @@
 #define BOOT_PAGE_TABLE_SIZE_IN_FRAMES  (BOOT_PAGE_TABLE_SIZE >> FRAME_WIDTH)
 
-#ifdef MACHINE_gta02
-#define PHYSMEM_START_ADDR	0x30008000
-#elif defined MACHINE_beagleboardxm
-#define PHYSMEM_START_ADDR      0x80000000
-#else
-#define PHYSMEM_START_ADDR	0x00000000
-#endif
 
 extern void frame_low_arch_init(void);
Index: kernel/arch/arm32/include/mm/page.h
===================================================================
--- kernel/arch/arm32/include/mm/page.h	(revision a640bc16cd3d7e9a79be3f918bb85b4f75d7d096)
+++ kernel/arch/arm32/include/mm/page.h	(revision 5fcd5372fa4cc52bb3d6d189df950427675f6acd)
@@ -129,7 +129,7 @@
 	set_pt_level1_present((pte_t *) (ptl3), (size_t) (i))
 
-#if defined(PROCESSOR_armv6) | defined(PROCESSOR_armv7_a)
+#if defined(PROCESSOR_ARCH_armv6) | defined(PROCESSOR_ARCH_armv7_a)
 #include "page_armv6.h"
-#elif defined(PROCESSOR_armv4) | defined(PROCESSOR_armv5)
+#elif defined(PROCESSOR_ARCH_armv4) | defined(PROCESSOR_ARCH_armv5)
 #include "page_armv4.h"
 #else
Index: kernel/arch/arm32/include/regutils.h
===================================================================
--- kernel/arch/arm32/include/regutils.h	(revision a640bc16cd3d7e9a79be3f918bb85b4f75d7d096)
+++ kernel/arch/arm32/include/regutils.h	(revision 5fcd5372fa4cc52bb3d6d189df950427675f6acd)
@@ -47,5 +47,5 @@
 #define CP15_R1_CACHE_EN          (1 << 2)
 #define CP15_R1_CP15_BARRIER_EN   (1 << 5)
-#define CP15_R1_B_EN              (1 << 7)  /* ARMv6- only big endian switch */
+#define CP15_R1_B_EN              (1 << 7)  /* ARMv6- only, big endian switch */
 #define CP15_R1_SWAP_EN           (1 << 10)
 #define CP15_R1_BRANCH_PREDICT_EN (1 << 11)
Index: kernel/arch/arm32/src/cpu/cpu.c
===================================================================
--- kernel/arch/arm32/src/cpu/cpu.c	(revision a640bc16cd3d7e9a79be3f918bb85b4f75d7d096)
+++ kernel/arch/arm32/src/cpu/cpu.c	(revision 5fcd5372fa4cc52bb3d6d189df950427675f6acd)
@@ -98,5 +98,9 @@
 void cpu_arch_init(void)
 {
-#if defined(PROCESSOR_armv7_a) | defined(PROCESSOR_armv6)
+	/* Get rid of any boot code hiding in ICache
+	 * This is safe without regards to ICache state. */
+	memory_barrier();
+	smc_coherence();
+
 	uint32_t control_reg = 0;
 	asm volatile (
@@ -105,10 +109,15 @@
 	);
 	
-	/* Turn off tex remap, RAZ ignores writes prior to armv7 */
+	/* Turn off tex remap, RAZ/WI prior to armv7 */
 	control_reg &= ~CP15_R1_TEX_REMAP_EN;
-	/* Turn off accessed flag, RAZ ignores writes prior to armv7 */
+	/* Turn off accessed flag, RAZ/WI prior to armv7 */
 	control_reg &= ~(CP15_R1_ACCESS_FLAG_EN | CP15_R1_HW_ACCESS_FLAG_EN);
-	/* Enable unaligned access, RAZ ignores writes prior to armv6
-	 * switchable on armv6, RAO ignores writes on armv7,
+	/* Disable branch prediction RAZ/WI if not supported */
+	control_reg &= ~CP15_R1_BRANCH_PREDICT_EN;
+
+	/* Unaligned access is supported on armv6+ */
+#if defined(PROCESSOR_ARCH_armv7_a) | defined(PROCESSOR_ARCH_armv6)
+	/* Enable unaligned access, RAZ/WI prior to armv6
+	 * switchable on armv6, RAO/WI writes on armv7,
 	 * see ARM Architecture Reference Manual ARMv7-A and ARMv7-R edition
 	 * L.3.1 (p. 2456) */
@@ -124,8 +133,15 @@
 	 *    ARM Architecture Reference Manual ARMv7-A and ARMv7-R Edition
 	 *    B3.11.1 (p. 1383)
-	 * ICache coherency is elaborate on in barrier.h.
-	 * We are safe to turn these on.
+	 * We are safe to turn this on. For arm v6 see ch L.6.2 (p. 2469)
+	 * L2 Cache for armv7 was enabled in boot code.
 	 */
-	control_reg |= CP15_R1_CACHE_EN | CP15_R1_INST_CACHE_EN;
+	control_reg |= CP15_R1_CACHE_EN;
+#endif
+#ifdef PROCESSOR_cortex_a8
+	 /* ICache coherency is elaborate on in barrier.h.
+	  * Cortex-A8 implements IVIPT extension.
+	  * Cortex-A8 TRM ch. 7.2.6 p. 7-4 (PDF 245) */
+	control_reg |= CP15_R1_INST_CACHE_EN;
+#endif
 	
 	asm volatile (
@@ -133,5 +149,4 @@
 		:: [control_reg] "r" (control_reg)
 	);
-#endif
 #ifdef CONFIG_FPU
 	fpu_setup();
Index: kernel/arch/arm32/src/fpu_context.c
===================================================================
--- kernel/arch/arm32/src/fpu_context.c	(revision a640bc16cd3d7e9a79be3f918bb85b4f75d7d096)
+++ kernel/arch/arm32/src/fpu_context.c	(revision 5fcd5372fa4cc52bb3d6d189df950427675f6acd)
@@ -119,5 +119,5 @@
  * rely on user decision to use CONFIG_FPU.
  */
-#ifdef PROCESSOR_armv7_a
+#ifdef PROCESSOR_ARC_armv7_a
 	const uint32_t cpacr = CPACR_read();
 	/* FPU needs access to coprocessor 10 and 11.
@@ -148,5 +148,5 @@
  * rely on user decision to use CONFIG_FPU.
  */
-#ifndef PROCESSOR_armv7_a
+#ifndef PROCESSOR_ARCH_armv7_a
 	return;
 #endif
Index: kernel/arch/arm32/src/mm/page_fault.c
===================================================================
--- kernel/arch/arm32/src/mm/page_fault.c	(revision a640bc16cd3d7e9a79be3f918bb85b4f75d7d096)
+++ kernel/arch/arm32/src/mm/page_fault.c	(revision 5fcd5372fa4cc52bb3d6d189df950427675f6acd)
@@ -174,5 +174,5 @@
 }
 
-#if defined(PROCESSOR_armv4) | defined(PROCESSOR_armv5)
+#if defined(PROCESSOR_ARCH_armv4) | defined(PROCESSOR_ARCH_armv5)
 /** Decides whether read or write into memory is requested.
  *
@@ -281,8 +281,8 @@
 	}
 
-#if defined(PROCESSOR_armv6) | defined(PROCESSOR_armv7_a)
+#if defined(PROCESSOR_ARCH_armv6) | defined(PROCESSOR_ARCH_armv7_a)
 	const pf_access_t access =
 	    fsr.data.wr ? PF_ACCESS_WRITE : PF_ACCESS_READ;
-#elif defined(PROCESSOR_armv4) | defined(PROCESSOR_armv5)
+#elif defined(PROCESSOR_ARCH_armv4) | defined(PROCESSOR_ARCH_armv5)
 	const pf_access_t access = get_memory_access_type(istate->pc, badvaddr);
 #else