Changeset 5f70118 in mainline for kernel/arch/arm32


Ignore:
Timestamp:
2010-01-10T12:16:59Z (16 years ago)
Author:
Jiri Svoboda <jiri@…>
Branches:
lfn, master, serial, ticket/834-toolchain-update, topic/msim-upgrade, topic/simplify-dev-export
Children:
c77a64f
Parents:
309ede1 (diff), 1ac3a52 (diff)
Note: this is a merge changeset, the changes displayed below correspond to the merge itself.
Use the (diff) links above to see all the changes relative to each parent.
Message:

Merge mainline changes.

Location:
kernel/arch/arm32
Files:
3 added
12 edited
1 moved

Legend:

Unmodified
Added
Removed

  • kernel/arch/arm32/Makefile.inc

    r309ede1 r5f70118  
    5757        arch/$(KARCH)/src/exception.c \
    5858        arch/$(KARCH)/src/userspace.c \
     59        arch/$(KARCH)/src/debug/stacktrace.c \
     60        arch/$(KARCH)/src/debug/stacktrace_asm.S \
    5961        arch/$(KARCH)/src/mm/as.c \
    6062        arch/$(KARCH)/src/mm/frame.c \
    6163        arch/$(KARCH)/src/mm/page.c \
    6264        arch/$(KARCH)/src/mm/tlb.c \
    63         arch/$(KARCH)/src/mm/page_fault.c
     65        arch/$(KARCH)/src/mm/page_fault.c \
     66        arch/$(KARCH)/src/ras.c
    6467
    6568ifeq ($(MACHINE),testarm)

  • kernel/arch/arm32/_link.ld.in

    r309ede1 r5f70118  
    3434                *(.sdata);
    3535                *(.reginfo);
     36                . = ALIGN(8);
    3637                symbol_table = .;
    3738                *(symtab.*);

  • kernel/arch/arm32/include/atomic.h

    r309ede1 r5f70118  
    3737#define KERN_arm32_ATOMIC_H_
    3838
     39#include <arch/asm.h>
     40
    3941/** Atomic addition.
    4042 *
    … …  
    4749static inline long atomic_add(atomic_t *val, int i)
    4850{
    49         int ret;
    50         volatile long *mem = &(val->count);
    51        
    52         asm volatile (
    53                 "1:\n"
    54                         "ldr r2, [%[mem]]\n"
    55                         "add r3, r2, %[i]\n"
    56                         "str r3, %[ret]\n"
    57                         "swp r3, r3, [%[mem]]\n"
    58                         "cmp r3, r2\n"
    59                         "bne 1b\n"
    60                 : [ret] "=m" (ret)
    61                 : [mem] "r" (mem), [i] "r" (i)
    62                 : "r3", "r2"
    63         );
     51        long ret;
     52
     53        /*
     54         * This implementation is for UP pre-ARMv6 systems where we do not have
     55         * the LDREX and STREX instructions.
     56         */
     57        ipl_t ipl = interrupts_disable();
     58        val->count += i;
     59        ret = val->count;
     60        interrupts_restore(ipl);
    6461       
    6562        return ret;

  • kernel/arch/arm32/include/exception.h

    r309ede1 r5f70118  
    8686
    8787/** Struct representing CPU state saved when an exception occurs. */
    88 typedef struct {
     88typedef struct istate {
    8989        uint32_t spsr;
    9090        uint32_t sp;
    … …  
    133133}
    134134
     135static inline unative_t istate_get_fp(istate_t *istate)
     136{
     137        return istate->r11;
     138}
     139
    135140
    136141extern void install_exception_handlers(void);

  • kernel/arch/arm32/include/mm/as.h

    r309ede1 r5f70118  
    5454#define as_destructor_arch(as)                  (as != as)
    5555#define as_create_arch(as, flags)               (as != as)
    56 #define as_install_arch(as)
    5756#define as_deinstall_arch(as)
    5857#define as_invalidate_translation_cache(as, page, cnt)

  • kernel/arch/arm32/include/mm/page.h

    r309ede1 r5f70118  
    7575/* Get PTE address accessors for each level. */
    7676#define GET_PTL1_ADDRESS_ARCH(ptl0, i) \
    77         ((pte_t *) ((((pte_level0_t *)(ptl0))[(i)]).coarse_table_addr << 10))
     77        ((pte_t *) ((((pte_t *)(ptl0))[(i)].l0).coarse_table_addr << 10))
    7878#define GET_PTL2_ADDRESS_ARCH(ptl1, i) \
    7979        (ptl1)
    … …  
    8181        (ptl2)
    8282#define GET_FRAME_ADDRESS_ARCH(ptl3, i) \
    83         ((uintptr_t) ((((pte_level1_t *)(ptl3))[(i)]).frame_base_addr << 12))
     83        ((uintptr_t) ((((pte_t *)(ptl3))[(i)].l1).frame_base_addr << 12))
    8484
    8585/* Set PTE address accessors for each level. */
    8686#define SET_PTL0_ADDRESS_ARCH(ptl0) \
    87         (set_ptl0_addr((pte_level0_t *) (ptl0)))
     87        (set_ptl0_addr((pte_t *) (ptl0)))
    8888#define SET_PTL1_ADDRESS_ARCH(ptl0, i, a) \
    89         (((pte_level0_t *) (ptl0))[(i)].coarse_table_addr = (a) >> 10)
     89        (((pte_t *) (ptl0))[(i)].l0.coarse_table_addr = (a) >> 10)
    9090#define SET_PTL2_ADDRESS_ARCH(ptl1, i, a)
    9191#define SET_PTL3_ADDRESS_ARCH(ptl2, i, a)
    9292#define SET_FRAME_ADDRESS_ARCH(ptl3, i, a) \
    93         (((pte_level1_t *) (ptl3))[(i)].frame_base_addr = (a) >> 12)
     93        (((pte_t *) (ptl3))[(i)].l1.frame_base_addr = (a) >> 12)
    9494
    9595/* Get PTE flags accessors for each level. */
    9696#define GET_PTL1_FLAGS_ARCH(ptl0, i) \
    97         get_pt_level0_flags((pte_level0_t *) (ptl0), (size_t) (i))
     97        get_pt_level0_flags((pte_t *) (ptl0), (size_t) (i))
    9898#define GET_PTL2_FLAGS_ARCH(ptl1, i) \
    9999        PAGE_PRESENT
    … …  
    101101        PAGE_PRESENT
    102102#define GET_FRAME_FLAGS_ARCH(ptl3, i) \
    103         get_pt_level1_flags((pte_level1_t *) (ptl3), (size_t) (i))
     103        get_pt_level1_flags((pte_t *) (ptl3), (size_t) (i))
    104104
    105105/* Set PTE flags accessors for each level. */
    106106#define SET_PTL1_FLAGS_ARCH(ptl0, i, x) \
    107         set_pt_level0_flags((pte_level0_t *) (ptl0), (size_t) (i), (x))
     107        set_pt_level0_flags((pte_t *) (ptl0), (size_t) (i), (x))
    108108#define SET_PTL2_FLAGS_ARCH(ptl1, i, x)
    109109#define SET_PTL3_FLAGS_ARCH(ptl2, i, x)
    110110#define SET_FRAME_FLAGS_ARCH(ptl3, i, x) \
    111         set_pt_level1_flags((pte_level1_t *) (ptl3), (size_t) (i), (x))
     111        set_pt_level1_flags((pte_t *) (ptl3), (size_t) (i), (x))
    112112
    113113/* Macros for querying the last-level PTE entries. */
    … …  
    115115        (*((uint32_t *) (pte)) != 0)
    116116#define PTE_PRESENT_ARCH(pte) \
    117         (((pte_level0_t *) (pte))->descriptor_type != 0)
     117        (((pte_t *) (pte))->l0.descriptor_type != 0)
    118118#define PTE_GET_FRAME_ARCH(pte) \
    119         (((pte_level1_t *) (pte))->frame_base_addr << FRAME_WIDTH)
     119        (((pte_t *) (pte))->l1.frame_base_addr << FRAME_WIDTH)
    120120#define PTE_WRITABLE_ARCH(pte) \
    121         (((pte_level1_t *) (pte))->access_permission_0 == \
    122             PTE_AP_USER_RW_KERNEL_RW)
     121        (((pte_t *) (pte))->l1.access_permission_0 == PTE_AP_USER_RW_KERNEL_RW)
    123122#define PTE_EXECUTABLE_ARCH(pte) \
    124123        1
    … …  
    159158} ATTRIBUTE_PACKED pte_level1_t;
    160159
     160typedef union {
     161        pte_level0_t l0;
     162        pte_level1_t l1;
     163} pte_t;
    161164
    162165/* Level 1 page tables access permissions */
    … …  
    191194 * @param pt    Pointer to the page table to set.
    192195 */   
    193 static inline void set_ptl0_addr(pte_level0_t *pt)
     196static inline void set_ptl0_addr(pte_t *pt)
    194197{
    195198        asm volatile (
    … …  
    205208 *  @param i      Index of the entry to return.
    206209 */
    207 static inline int get_pt_level0_flags(pte_level0_t *pt, size_t i)
    208 {
    209         pte_level0_t *p = &pt[i];
     210static inline int get_pt_level0_flags(pte_t *pt, size_t i)
     211{
     212        pte_level0_t *p = &pt[i].l0;
    210213        int np = (p->descriptor_type == PTE_DESCRIPTOR_NOT_PRESENT);
    211214
    … …  
    220223 *  @param i      Index of the entry to return.
    221224 */
    222 static inline int get_pt_level1_flags(pte_level1_t *pt, size_t i)
    223 {
    224         pte_level1_t *p = &pt[i];
     225static inline int get_pt_level1_flags(pte_t *pt, size_t i)
     226{
     227        pte_level1_t *p = &pt[i].l1;
    225228
    226229        int dt = p->descriptor_type;
    … …  
    245248 *  @param flags  new flags
    246249 */
    247 static inline void set_pt_level0_flags(pte_level0_t *pt, size_t i, int flags)
    248 {
    249         pte_level0_t *p = &pt[i];
     250static inline void set_pt_level0_flags(pte_t *pt, size_t i, int flags)
     251{
     252        pte_level0_t *p = &pt[i].l0;
    250253
    251254        if (flags & PAGE_NOT_PRESENT) {
    … …  
    273276 *  @param flags  New flags.
    274277 */ 
    275 static inline void set_pt_level1_flags(pte_level1_t *pt, size_t i, int flags)
    276 {
    277         pte_level1_t *p = &pt[i];
     278static inline void set_pt_level1_flags(pte_t *pt, size_t i, int flags)
     279{
     280        pte_level1_t *p = &pt[i].l1;
    278281       
    279282        if (flags & PAGE_NOT_PRESENT) {

  • kernel/arch/arm32/include/types.h

    r309ede1 r5f70118  
    8787#define PRIxn "x"       /**< Format for hexadecimal (u)native_t. */
    8888
    89 /** Page table entry.
    90  *
    91  *  We have different structs for level 0 and level 1 page table entries.
    92  *  See page.h for definition of pte_level*_t.
    93  */
    94 typedef struct {
    95         unsigned dummy : 32;
    96 } pte_t;
    97 
    9889#endif
    9990

  • kernel/arch/arm32/src/arm32.c

    r309ede1 r5f70118  
    4848#include <macros.h>
    4949#include <string.h>
     50#include <arch/ras.h>
    5051
    5152#ifdef MACHINE_testarm
    … …  
    8889        exception_init();
    8990        interrupt_init();
     91
     92        /* Initialize Restartable Atomic Sequences support. */
     93        ras_init();
    9094       
    9195        machine_output_init();
    … …  
    136140        uint8_t *stck;
    137141       
    138         tlb_invalidate_all();
    139142        stck = &THREAD->kstack[THREAD_STACK_SIZE - SP_DELTA];
    140143        supervisor_sp = (uintptr_t) stck;

  • kernel/arch/arm32/src/debug/stacktrace.c

    r309ede1 r5f70118  
    11/*
    2  * Copyright (c) 2005 Jakub Jermar
     2 * Copyright (c) 2010 Jakub Jermar
    33 * All rights reserved.
    44 *
    … …  
    2727 */
    2828
    29 /** @addtogroup mips32 
     29/** @addtogroup arm32
    3030 * @{
    3131 */
    … …  
    3333 */
    3434
    35 #ifndef KERN_mips32_ARG_H_
    36 #define KERN_mips32_ARG_H_
     35#include <stacktrace.h>
     36#include <syscall/copy.h>
     37#include <arch/types.h>
     38#include <typedefs.h>
    3739
    38 #include <arch/types.h>
     40bool kernel_frame_pointer_validate(uintptr_t fp)
     41{
     42        return false;
     43}
    3944
    40 /**
    41  * va_arg macro for MIPS32 - problem is that 64 bit values must be aligned on an 8-byte boundary (32bit values not)
    42  * To satisfy this, paddings must be sometimes inserted.
    43  */
     45bool kernel_frame_pointer_prev(uintptr_t fp, uintptr_t *prev)
     46{
     47        return false;
     48}
    4449
    45 typedef uintptr_t va_list;
     50bool kernel_return_address_get(uintptr_t fp, uintptr_t *ra)
     51{
     52        return false;
     53}
    4654
    47 #define va_start(ap, lst) \
    48         ((ap) = (va_list)&(lst) + sizeof(lst))
     55bool uspace_frame_pointer_validate(uintptr_t fp)
     56{
     57        return false;
     58}
    4959
    50 #define va_arg(ap, type)        \
    51         (((type *)((ap) = (va_list)( (sizeof(type) <= 4) ? ((uintptr_t)((ap) + 2*4 - 1) & (~3)) : ((uintptr_t)((ap) + 2*8 -1) & (~7)) )))[-1])
     60bool uspace_frame_pointer_prev(uintptr_t fp, uintptr_t *prev)
     61{
     62        return false;
     63}
    5264
    53 #define va_copy(dst,src) ((dst)=(src))
    54 
    55 #define va_end(ap)
    56 
    57 #endif
     65bool uspace_return_address_get(uintptr_t fp, uintptr_t *ra)
     66{
     67        return false;
     68}
    5869
    5970/** @}

  • kernel/arch/arm32/src/exc_handler.S

    r309ede1 r5f70118  
    148148        mov r0, #0
    149149        mov r1, r13
    150         bl exc_dispatch
     150        bl ras_check
    151151        LOAD_REGS_FROM_STACK
    152152
    … …  
    156156        mov r0, #5
    157157        mov r1, r13
    158         bl exc_dispatch
     158        bl ras_check
    159159        LOAD_REGS_FROM_STACK
    160160
    … …  
    164164        mov r0, #6
    165165        mov r1, r13
    166         bl exc_dispatch
     166        bl ras_check
    167167        LOAD_REGS_FROM_STACK
    168168
    … …  
    171171        mov r0, #1
    172172        mov r1, r13
    173         bl exc_dispatch
     173        bl ras_check
    174174        LOAD_REGS_FROM_STACK
    175175
    … …  
    179179        mov r0, #3
    180180        mov r1, r13
    181         bl exc_dispatch
     181        bl ras_check
    182182        LOAD_REGS_FROM_STACK
    183183
    … …  
    187187        mov r0, #4
    188188        mov r1, r13
    189         bl exc_dispatch
     189        bl ras_check
    190190        LOAD_REGS_FROM_STACK
    191191
    … …  
    195195        mov r0, #2
    196196        mov r1, r13
    197         bl exc_dispatch
     197        bl ras_check
    198198        LOAD_REGS_FROM_STACK
    199199

  • kernel/arch/arm32/src/mm/as.c

    r309ede1 r5f70118  
    3636#include <arch/mm/as.h>
    3737#include <genarch/mm/as_pt.h>
     38#include <genarch/mm/page_pt.h>
    3839#include <genarch/mm/asid_fifo.h>
    3940#include <mm/as.h>
     41#include <mm/tlb.h>
    4042#include <arch.h>
    4143
    … …  
    4951}
    5052
     53void as_install_arch(as_t *as)
     54{
     55        tlb_invalidate_all();
     56}
     57
    5158/** @}
    5259 */

  • kernel/arch/arm32/src/mm/page.c

    r309ede1 r5f70118  
    8888            KA2PA(KERNEL_ADDRESS_SPACE_END_ARCH)) {
    8989                panic("Unable to map physical memory %p (%d bytes).",
    90                     physaddr, size)
     90                    physaddr, size);
    9191        }
    9292       

  • kernel/arch/arm32/src/userspace.c

    r309ede1 r5f70118  
    3535
    3636#include <userspace.h>
     37#include <arch/ras.h>
    3738
    3839/** Struct for holding all general purpose registers.
    … …  
    7475        ustate.r1 = 0;
    7576
     77        /* pass the RAS page address in %r2 */
     78        ustate.r2 = (uintptr_t) ras_page;
     79
    7680        /* clear other registers */
    77         ustate.r2 = ustate.r3  = ustate.r4  = ustate.r5 =
    78             ustate.r6  = ustate.r7  = ustate.r8  = ustate.r9 = ustate.r10 =
    79             ustate.r11 = ustate.r12 = ustate.lr = 0;
     81        ustate.r3  = ustate.r4  = ustate.r5 = ustate.r6 = ustate.r7 =
     82            ustate.r8 = ustate.r9 = ustate.r10 = ustate.r11 = ustate.r12 =
     83            ustate.lr = 0;
    8084
    8185        /* set user stack */
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