Index: kernel/arch/sparc64/include/mm/sun4u/mmu.h =================================================================== --- kernel/arch/sparc64/include/mm/sun4u/mmu.h (revision 5f678b1cc94b4f085d978e9abf075070da605a36) +++ kernel/arch/sparc64/include/mm/sun4u/mmu.h (revision 5f678b1cc94b4f085d978e9abf075070da605a36) @@ -0,0 +1,123 @@ +/* + * Copyright (c) 2005 Jakub Jermar + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * - Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * - Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * - The name of the author may not be used to endorse or promote products + * derived from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR + * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES + * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. + * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT + * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF + * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +/** @addtogroup sparc64mm + * @{ + */ +/** @file + */ + +#ifndef KERN_sparc64_sun4u_MMU_H_ +#define KERN_sparc64_sun4u_MMU_H_ + +#if defined(US) +/* LSU Control Register ASI. */ +#define ASI_LSU_CONTROL_REG 0x45 /**< Load/Store Unit Control Register. */ +#endif + +/* I-MMU ASIs. */ +#define ASI_IMMU 0x50 +#define ASI_IMMU_TSB_8KB_PTR_REG 0x51 +#define ASI_IMMU_TSB_64KB_PTR_REG 0x52 +#define ASI_ITLB_DATA_IN_REG 0x54 +#define ASI_ITLB_DATA_ACCESS_REG 0x55 +#define ASI_ITLB_TAG_READ_REG 0x56 +#define ASI_IMMU_DEMAP 0x57 + +/* Virtual Addresses within ASI_IMMU. */ +#define VA_IMMU_TSB_TAG_TARGET 0x0 /**< IMMU TSB tag target register. */ +#define VA_IMMU_SFSR 0x18 /**< IMMU sync fault status register. */ +#define VA_IMMU_TSB_BASE 0x28 /**< IMMU TSB base register. */ +#define VA_IMMU_TAG_ACCESS 0x30 /**< IMMU TLB tag access register. */ +#if defined (US3) +#define VA_IMMU_PRIMARY_EXTENSION 0x48 /**< IMMU TSB primary extension register */ +#define VA_IMMU_NUCLEUS_EXTENSION 0x58 /**< IMMU TSB nucleus extension register */ +#endif + + +/* D-MMU ASIs. */ +#define ASI_DMMU 0x58 +#define ASI_DMMU_TSB_8KB_PTR_REG 0x59 +#define ASI_DMMU_TSB_64KB_PTR_REG 0x5a +#define ASI_DMMU_TSB_DIRECT_PTR_REG 0x5b +#define ASI_DTLB_DATA_IN_REG 0x5c +#define ASI_DTLB_DATA_ACCESS_REG 0x5d +#define ASI_DTLB_TAG_READ_REG 0x5e +#define ASI_DMMU_DEMAP 0x5f + +/* Virtual Addresses within ASI_DMMU. */ +#define VA_DMMU_TSB_TAG_TARGET 0x0 /**< DMMU TSB tag target register. */ +#define VA_PRIMARY_CONTEXT_REG 0x8 /**< DMMU primary context register. */ +#define VA_SECONDARY_CONTEXT_REG 0x10 /**< DMMU secondary context register. */ +#define VA_DMMU_SFSR 0x18 /**< DMMU sync fault status register. */ +#define VA_DMMU_SFAR 0x20 /**< DMMU sync fault address register. */ +#define VA_DMMU_TSB_BASE 0x28 /**< DMMU TSB base register. */ +#define VA_DMMU_TAG_ACCESS 0x30 /**< DMMU TLB tag access register. */ +#define VA_DMMU_VA_WATCHPOINT_REG 0x38 /**< DMMU VA data watchpoint register. */ +#define VA_DMMU_PA_WATCHPOINT_REG 0x40 /**< DMMU PA data watchpoint register. */ +#if defined (US3) +#define VA_DMMU_PRIMARY_EXTENSION 0x48 /**< DMMU TSB primary extension register */ +#define VA_DMMU_SECONDARY_EXTENSION 0x50 /**< DMMU TSB secondary extension register */ +#define VA_DMMU_NUCLEUS_EXTENSION 0x58 /**< DMMU TSB nucleus extension register */ +#endif + +#ifndef __ASM__ + +#include +#include +#include + +#if defined(US) +/** LSU Control Register. */ +typedef union { + uint64_t value; + struct { + unsigned : 23; + unsigned pm : 8; + unsigned vm : 8; + unsigned pr : 1; + unsigned pw : 1; + unsigned vr : 1; + unsigned vw : 1; + unsigned : 1; + unsigned fm : 16; + unsigned dm : 1; /**< D-MMU enable. */ + unsigned im : 1; /**< I-MMU enable. */ + unsigned dc : 1; /**< D-Cache enable. */ + unsigned ic : 1; /**< I-Cache enable. */ + + } __attribute__ ((packed)); +} lsu_cr_reg_t; +#endif /* US */ + +#endif /* !def __ASM__ */ + +#endif + +/** @} + */ Index: kernel/arch/sparc64/include/sun4u/cpu.h =================================================================== --- kernel/arch/sparc64/include/sun4u/cpu.h (revision 5f678b1cc94b4f085d978e9abf075070da605a36) +++ kernel/arch/sparc64/include/sun4u/cpu.h (revision 5f678b1cc94b4f085d978e9abf075070da605a36) @@ -0,0 +1,99 @@ +/* + * Copyright (c) 2005 Jakub Jermar + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * - Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * - Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * - The name of the author may not be used to endorse or promote products + * derived from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR + * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES + * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. + * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT + * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF + * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +/** @addtogroup sparc64 + * @{ + */ +/** @file + */ + +#ifndef KERN_sparc64_CPU_H_ +#define KERN_sparc64_CPU_H_ + +#define MANUF_FUJITSU 0x04 +#define MANUF_ULTRASPARC 0x17 /**< UltraSPARC I, UltraSPARC II */ +#define MANUF_SUN 0x3e + +#define IMPL_ULTRASPARCI 0x10 +#define IMPL_ULTRASPARCII 0x11 +#define IMPL_ULTRASPARCII_I 0x12 +#define IMPL_ULTRASPARCII_E 0x13 +#define IMPL_ULTRASPARCIII 0x14 +#define IMPL_ULTRASPARCIII_PLUS 0x15 +#define IMPL_ULTRASPARCIII_I 0x16 +#define IMPL_ULTRASPARCIV 0x18 +#define IMPL_ULTRASPARCIV_PLUS 0x19 + +#define IMPL_SPARC64V 0x5 + +#ifndef __ASM__ + +#include +#include +#include +#include +#include + +#ifdef CONFIG_SMP +#include +#endif + +typedef struct { + uint32_t mid; /**< Processor ID as read from + UPA_CONFIG/FIREPLANE_CONFIG. */ + ver_reg_t ver; + uint32_t clock_frequency; /**< Processor frequency in Hz. */ + uint64_t next_tick_cmpr; /**< Next clock interrupt should be + generated when the TICK register + matches this value. */ +} cpu_arch_t; + + +/** + * Reads the module ID (agent ID/CPUID) of the current CPU. + */ +static inline uint32_t read_mid(void) +{ + uint64_t icbus_config = asi_u64_read(ASI_ICBUS_CONFIG, 0); + icbus_config = icbus_config >> ICBUS_CONFIG_MID_SHIFT; +#if defined (US) + return icbus_config & 0x1f; +#elif defined (US3) + if (((ver_reg_t) ver_read()).impl == IMPL_ULTRASPARCIII_I) + return icbus_config & 0x1f; + else + return icbus_config & 0x3ff; +#endif +} + +#endif + +#endif + +/** @} + */ Index: kernel/arch/sparc64/src/proc/sun4u/scheduler.c =================================================================== --- kernel/arch/sparc64/src/proc/sun4u/scheduler.c (revision 5f678b1cc94b4f085d978e9abf075070da605a36) +++ kernel/arch/sparc64/src/proc/sun4u/scheduler.c (revision 5f678b1cc94b4f085d978e9abf075070da605a36) @@ -0,0 +1,83 @@ +/* + * Copyright (c) 2006 Jakub Jermar + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * - Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * - Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * - The name of the author may not be used to endorse or promote products + * derived from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR + * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES + * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. + * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT + * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF + * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +/** @addtogroup sparc64proc + * @{ + */ +/** @file + */ + +#include +#include +#include +#include +#include + +/** Perform sparc64 specific tasks needed before the new task is run. */ +void before_task_runs_arch(void) +{ +} + +/** Perform sparc64 specific steps before scheduling a thread. + * + * For userspace threads, initialize reserved global registers in the alternate + * and interrupt sets. + */ +void before_thread_runs_arch(void) +{ + if ((THREAD->flags & THREAD_FLAG_USPACE)) { + /* + * Write kernel stack address to %g6 of the alternate and + * interrupt global sets. + * + * Write pointer to the last item in the userspace window buffer + * to %g7 in the alternate set. Write to the interrupt %g7 is + * not necessary because: + * - spill traps operate only in the alternate global set, + * - preemptible trap handler switches to alternate globals + * before it explicitly uses %g7. + */ + uint64_t sp = (uintptr_t) THREAD->kstack + STACK_SIZE - + (STACK_BIAS + ALIGN_UP(STACK_ITEM_SIZE, STACK_ALIGNMENT)); + write_to_ig_g6(sp); + write_to_ag_g6(sp); + write_to_ag_g7((uintptr_t) THREAD->arch.uspace_window_buffer); + } +} + +/** Perform sparc64 specific steps before a thread stops running. */ +void after_thread_ran_arch(void) +{ + if ((THREAD->flags & THREAD_FLAG_USPACE)) { + /* sample the state of the userspace window buffer */ + THREAD->arch.uspace_window_buffer = (uint8_t *) read_from_ag_g7(); + } +} + +/** @} + */ Index: kernel/arch/sparc64/src/proc/sun4v/scheduler.c =================================================================== --- kernel/arch/sparc64/src/proc/sun4v/scheduler.c (revision 5f678b1cc94b4f085d978e9abf075070da605a36) +++ kernel/arch/sparc64/src/proc/sun4v/scheduler.c (revision 5f678b1cc94b4f085d978e9abf075070da605a36) @@ -0,0 +1,78 @@ +/* + * Copyright (c) 2006 Jakub Jermar + * Copyright (c) 2009 Pavel Rimsky + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * - Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * - Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * - The name of the author may not be used to endorse or promote products + * derived from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR + * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES + * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. + * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT + * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF + * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +/** @addtogroup sparc64proc + * @{ + */ +/** @file + */ + +#include +#include +#include +#include +#include +#include +#include +#include + +/** Perform sparc64 specific tasks needed before the new task is run. */ +void before_task_runs_arch(void) +{ +} + +/** Perform sparc64 specific steps before scheduling a thread. + * + * For userspace threads, initialize pointer to the kernel stack and for the + * userspace window buffer. + */ +void before_thread_runs_arch(void) +{ + if ((THREAD->flags & THREAD_FLAG_USPACE)) { + uint64_t sp = (uintptr_t) THREAD->kstack + STACK_SIZE - + (STACK_BIAS + ALIGN_UP(STACK_ITEM_SIZE, STACK_ALIGNMENT)); + asi_u64_write(ASI_SCRATCHPAD, SCRATCHPAD_KSTACK, sp); + asi_u64_write(ASI_SCRATCHPAD, SCRATCHPAD_WBUF, + (uintptr_t) THREAD->arch.uspace_window_buffer); + } +} + +/** Perform sparc64 specific steps before a thread stops running. */ +void after_thread_ran_arch(void) +{ + if ((THREAD->flags & THREAD_FLAG_USPACE)) { + /* sample the state of the userspace window buffer */ + THREAD->arch.uspace_window_buffer = + (uint8_t *) asi_u64_read(ASI_SCRATCHPAD, SCRATCHPAD_WBUF); + + } +} + +/** @} + */ Index: kernel/arch/sparc64/src/trap/sun4u/mmu.S =================================================================== --- kernel/arch/sparc64/src/trap/sun4u/mmu.S (revision 5f678b1cc94b4f085d978e9abf075070da605a36) +++ kernel/arch/sparc64/src/trap/sun4u/mmu.S (revision 5f678b1cc94b4f085d978e9abf075070da605a36) @@ -0,0 +1,42 @@ +# +# Copyright (c) 2006 Jakub Jermar +# All rights reserved. +# +# Redistribution and use in source and binary forms, with or without +# modification, are permitted provided that the following conditions +# are met: +# +# - Redistributions of source code must retain the above copyright +# notice, this list of conditions and the following disclaimer. +# - Redistributions in binary form must reproduce the above copyright +# notice, this list of conditions and the following disclaimer in the +# documentation and/or other materials provided with the distribution. +# - The name of the author may not be used to endorse or promote products +# derived from this software without specific prior written permission. +# +# THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR +# IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES +# OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. +# IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, +# INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT +# NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF +# THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +# + +/** + * @file + * @brief MMU trap handlers that do not fit into the trap table. + */ + +.register %g2, #scratch +.register %g3, #scratch + +.text + +#include +#include +#include + Index: kernel/arch/sparc64/src/trap/sun4v/mmu.S =================================================================== --- kernel/arch/sparc64/src/trap/sun4v/mmu.S (revision 5f678b1cc94b4f085d978e9abf075070da605a36) +++ kernel/arch/sparc64/src/trap/sun4v/mmu.S (revision 5f678b1cc94b4f085d978e9abf075070da605a36) @@ -0,0 +1,74 @@ +# +# Copyright (c) 2006 Jakub Jermar +# All rights reserved. +# +# Redistribution and use in source and binary forms, with or without +# modification, are permitted provided that the following conditions +# are met: +# +# - Redistributions of source code must retain the above copyright +# notice, this list of conditions and the following disclaimer. +# - Redistributions in binary form must reproduce the above copyright +# notice, this list of conditions and the following disclaimer in the +# documentation and/or other materials provided with the distribution. +# - The name of the author may not be used to endorse or promote products +# derived from this software without specific prior written permission. +# +# THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR +# IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES +# OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. +# IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, +# INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT +# NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF +# THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +# + +/** + * @file + * @brief MMU trap handlers that do not fit into the trap table. + */ + +.register %g2, #scratch +.register %g3, #scratch + +.text + +#include +#include +#include + +/* + * Install mapping for the kernel. The mapping obeys this formula: + * virtual address = real address + start of physical memory + * + * The routine expects the following values of registers: + * %g1 virtual address that has caused the miss + */ +.global install_identity_mapping +install_identity_mapping: + + /* output registers mustn't be clobbered during the hypercall, SAVE is too risky */ + mov %o0, %g3 + mov %o1, %g4 + mov %o2, %g5 + mov %o3, %g6 + + /* install mapping for kernel */ + mov %g1, %o0 + set 0, %o1 ! set context + setx kernel_8k_tlb_data_template, %g1, %g2 ! g2 <= template of TTE Data + ldx [%g2], %g2 ! read the TTE Data template + add %g2, %o0, %o2 ! template + VA = TTE Data entry + set MMU_FLAG_DTLB, %o3 ! map in DTLB only + ta MMU_MAP_ADDR + + /* restore output registers */ + mov %g6, %o3 + mov %g5, %o2 + mov %g4, %o1 + mov %g3, %o0 + + retry