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  • kernel/arch/ia32/src/smp/apic.c

    r0f17bff r5e4f22b  
    4242#include <interrupt.h>
    4343#include <arch/interrupt.h>
    44 #include <log.h>
     44#include <print.h>
    4545#include <arch/asm.h>
    4646#include <arch.h>
     
    7272 *
    7373 */
    74 volatile uint32_t *l_apic = (uint32_t *) L_APIC_BASE;
    75 volatile uint32_t *io_apic = (uint32_t *) IO_APIC_BASE;
     74volatile uint32_t *l_apic = (uint32_t *) UINT32_C(0xfee00000);
     75volatile uint32_t *io_apic = (uint32_t *) UINT32_C(0xfec00000);
    7676
    7777uint32_t apic_id_mask = 0;
     
    135135{
    136136#ifdef CONFIG_DEBUG
    137         log(LF_ARCH, LVL_DEBUG, "cpu%u: APIC spurious interrupt", CPU->id);
     137        printf("cpu%u: APIC spurious interrupt\n", CPU->id);
    138138#endif
    139139}
     
    241241        esr.value = l_apic[ESR];
    242242       
    243         if (esr.err_bitmap) {
    244                 log_begin(LF_ARCH, LVL_ERROR);
    245                 log_printf("APIC errors detected:");
    246                 if (esr.send_checksum_error)
    247                         log_printf("\nSend Checksum Error");
    248                 if (esr.receive_checksum_error)
    249                         log_printf("\nReceive Checksum Error");
    250                 if (esr.send_accept_error)
    251                         log_printf("\nSend Accept Error");
    252                 if (esr.receive_accept_error)
    253                         log_printf("\nReceive Accept Error");
    254                 if (esr.send_illegal_vector)
    255                         log_printf("\nSend Illegal Vector");
    256                 if (esr.received_illegal_vector)
    257                         log_printf("\nReceived Illegal Vector");
    258                 if (esr.illegal_register_address)
    259                         log_printf("\nIllegal Register Address");
    260                 log_end();
    261         }
     243        if (esr.send_checksum_error)
     244                printf("Send Checksum Error\n");
     245        if (esr.receive_checksum_error)
     246                printf("Receive Checksum Error\n");
     247        if (esr.send_accept_error)
     248                printf("Send Accept Error\n");
     249        if (esr.receive_accept_error)
     250                printf("Receive Accept Error\n");
     251        if (esr.send_illegal_vector)
     252                printf("Send Illegal Vector\n");
     253        if (esr.received_illegal_vector)
     254                printf("Received Illegal Vector\n");
     255        if (esr.illegal_register_address)
     256                printf("Illegal Register Address\n");
    262257       
    263258        return !esr.err_bitmap;
    264259}
    265260
    266 /* Waits for the destination cpu to accept the previous ipi. */
     261#define DELIVS_PENDING_SILENT_RETRIES   4       
     262
    267263static void l_apic_wait_for_delivery(void)
    268264{
    269265        icr_t icr;
    270        
     266        unsigned retries = 0;
     267
    271268        do {
     269                if (retries++ > DELIVS_PENDING_SILENT_RETRIES) {
     270                        retries = 0;
     271#ifdef CONFIG_DEBUG
     272                        printf("IPI is pending.\n");
     273#endif
     274                        delay(20);
     275                }
    272276                icr.lo = l_apic[ICRlo];
    273         } while (icr.delivs != DELIVS_IDLE);
    274 }
    275 
    276 /** Send one CPU an IPI vector.
    277  *
    278  * @param apicid Physical APIC ID of the destination CPU.
     277        } while (icr.delivs == DELIVS_PENDING);
     278       
     279}
     280
     281/** Send all CPUs excluding CPU IPI vector.
     282 *
    279283 * @param vector Interrupt vector to be sent.
    280284 *
    281285 * @return 0 on failure, 1 on success.
    282  */
    283 int l_apic_send_custom_ipi(uint8_t apicid, uint8_t vector)
     286 *
     287 */
     288int l_apic_broadcast_custom_ipi(uint8_t vector)
    284289{
    285290        icr_t icr;
    286 
    287         /* Wait for a destination cpu to accept our previous ipi. */
    288         l_apic_wait_for_delivery();
    289        
    290         icr.lo = l_apic[ICRlo];
    291         icr.hi = l_apic[ICRhi];
    292        
    293         icr.delmod = DELMOD_FIXED;
    294         icr.destmod = DESTMOD_PHYS;
    295         icr.level = LEVEL_ASSERT;
    296         icr.shorthand = SHORTHAND_NONE;
    297         icr.trigger_mode = TRIGMOD_LEVEL;
    298         icr.vector = vector;
    299         icr.dest = apicid;
    300 
    301         /* Send the IPI by writing to l_apic[ICRlo]. */
    302         l_apic[ICRhi] = icr.hi;
    303         l_apic[ICRlo] = icr.lo;
    304        
    305         return apic_poll_errors();
    306 }
    307 
    308 /** Send all CPUs excluding CPU IPI vector.
    309  *
    310  * @param vector Interrupt vector to be sent.
    311  *
    312  * @return 0 on failure, 1 on success.
    313  *
    314  */
    315 int l_apic_broadcast_custom_ipi(uint8_t vector)
    316 {
    317         icr_t icr;
    318 
    319         /* Wait for a destination cpu to accept our previous ipi. */
    320         l_apic_wait_for_delivery();
    321291       
    322292        icr.lo = l_apic[ICRlo];
     
    329299       
    330300        l_apic[ICRlo] = icr.lo;
     301
     302        l_apic_wait_for_delivery();
    331303       
    332304        return apic_poll_errors();
     
    517489{
    518490#ifdef LAPIC_VERBOSE
    519         log_begin(LF_ARCH, LVL_DEBUG);
    520         log_printf("LVT on cpu%u, LAPIC ID: %" PRIu8 "\n",
     491        printf("LVT on cpu%u, LAPIC ID: %" PRIu8 "\n",
    521492            CPU->id, l_apic_id());
    522493       
    523494        lvt_tm_t tm;
    524495        tm.value = l_apic[LVT_Tm];
    525         log_printf("LVT Tm: vector=%" PRIu8 ", %s, %s, %s\n",
     496        printf("LVT Tm: vector=%" PRIu8 ", %s, %s, %s\n",
    526497            tm.vector, delivs_str[tm.delivs], mask_str[tm.masked],
    527498            tm_mode_str[tm.mode]);
     
    529500        lvt_lint_t lint;
    530501        lint.value = l_apic[LVT_LINT0];
    531         log_printf("LVT LINT0: vector=%" PRIu8 ", %s, %s, %s, irr=%u, %s, %s\n",
     502        printf("LVT LINT0: vector=%" PRIu8 ", %s, %s, %s, irr=%u, %s, %s\n",
    532503            tm.vector, delmod_str[lint.delmod], delivs_str[lint.delivs],
    533504            intpol_str[lint.intpol], lint.irr, trigmod_str[lint.trigger_mode],
     
    535506       
    536507        lint.value = l_apic[LVT_LINT1];
    537         log_printf("LVT LINT1: vector=%" PRIu8 ", %s, %s, %s, irr=%u, %s, %s\n",
     508        printf("LVT LINT1: vector=%" PRIu8 ", %s, %s, %s, irr=%u, %s, %s\n",
    538509            tm.vector, delmod_str[lint.delmod], delivs_str[lint.delivs],
    539510            intpol_str[lint.intpol], lint.irr, trigmod_str[lint.trigger_mode],
     
    542513        lvt_error_t error;
    543514        error.value = l_apic[LVT_Err];
    544         log_printf("LVT Err: vector=%" PRIu8 ", %s, %s\n", error.vector,
     515        printf("LVT Err: vector=%" PRIu8 ", %s, %s\n", error.vector,
    545516            delivs_str[error.delivs], mask_str[error.masked]);
    546         log_end();
    547517#endif
    548518}
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