Index: kernel/arch/arm32/src/cpu/cpu.c
===================================================================
--- kernel/arch/arm32/src/cpu/cpu.c	(revision 1a1b05bd95528eeb35ae526ba2e10c299b164273)
+++ kernel/arch/arm32/src/cpu/cpu.c	(revision 5de9ff964287f115bb9ba55fd07d1136ba9ec2d7)
@@ -97,5 +97,5 @@
 }
 
-/** Does nothing on ARM. */
+/** Enables unaligned access and caching for armv6+ */
 void cpu_arch_init(void)
 {
@@ -107,13 +107,26 @@
 	);
 	
-	/* Turn off tex remap */
+	/* Turn off tex remap, RAZ ignores writes prior to armv7 */
 	control_reg &= ~CP15_R1_TEX_REMAP_EN;
-	/* Turn off accessed flag */
+	/* Turn off accessed flag, RAZ ignores writes prior to armv7 */
 	control_reg &= ~(CP15_R1_ACCESS_FLAG_EN | CP15_R1_HW_ACCESS_FLAG_EN);
-	/* Enable unaligned access (U bit is armv6 only) */
+	/* Enable unaligned access, RAZ ignores writes prior to armv6
+	 * switchable on armv6, RAO ignores writes on armv7,
+	 * see ARM Architecture Reference Manual ARMv7-A and ARMv7-R edition
+	 * L.3.1 (p. 2456) */
 	control_reg |= CP15_R1_UNALIGNED_EN;
-	/* Disable alignment checks */
+	/* Disable alignment checks, this turns unaligned access to undefined,
+	 * unless U bit is set. */
 	control_reg &= ~CP15_R1_ALIGN_CHECK_EN;
-	/* Enable caching */
+	/* Enable caching, On arm prior to armv7 there is only one level
+	 * of caches. Data cache is coherent.
+	 * "This means that the behavior of accesses from the same observer to
+	 * different VAs, that are translated to the same PA
+	 * with the same memory attributes, is fully coherent."
+	 *    ARM Architecture Reference Manual ARMv7-A and ARMv7-R Edition
+	 *    B3.11.1 (p. 1383)
+	 * ICache coherency is elaborate on in barrier.h.
+	 * We are safe to turn these on.
+	 */
 	control_reg |= CP15_R1_CACHE_EN | CP15_R1_INST_CACHE_EN;