Index: kernel/arch/amd64/src/cpu/cpu.c
===================================================================
--- kernel/arch/amd64/src/cpu/cpu.c	(revision 20b8bf334fc016662c4e0addb183ae37eb75ed58)
+++ kernel/arch/amd64/src/cpu/cpu.c	(revision 5d8d71ebf89df6dbc2bd7f5a55aa3d4c73a286cd)
@@ -78,19 +78,17 @@
 {
 	asm volatile (
-		"movq %%cr0, %%rax;"
-		"btsq $1, %%rax;" /* cr0.mp */
-		"btrq $2, %%rax;"  /* cr0.em */
-		"movq %%rax, %%cr0;"
-
-		"movq %%cr4, %%rax;"
-		"bts $9, %%rax;" /* cr4.osfxsr */
-		"movq %%rax, %%cr4;"
-		:
-		:
-		:"%rax"
-		);
+		"movq %%cr0, %%rax\n"
+		"btsq $1, %%rax\n"  /* cr0.mp */
+		"btrq $2, %%rax\n"  /* cr0.em */
+		"movq %%rax, %%cr0\n"
+		
+		"movq %%cr4, %%rax\n"
+		"bts $9, %%rax\n"   /* cr4.osfxsr */
+		"movq %%rax, %%cr4\n"
+		::: "%rax"
+	);
 }
 
-/** Set the TS flag to 1. 
+/** Set the TS flag to 1.
  *
  * If a thread accesses coprocessor, exception is run, which 
@@ -100,24 +98,20 @@
 void fpu_disable(void)
 {
-	asm	volatile (
-		"mov %%cr0,%%rax;"
-		"bts $3,%%rax;"
-		"mov %%rax,%%cr0;"
-		:
-		:
-		:"%rax"
-		);
+	asm volatile (
+		"mov %%cr0, %%rax\n"
+		"bts $3, %%rax\n"
+		"mov %%rax, %%cr0\n"
+		::: "%rax"
+	);
 }
 
 void fpu_enable(void)
 {
-	asm	volatile (
-		"mov %%cr0,%%rax;"
-		"btr $3,%%rax;"
-		"mov %%rax,%%cr0;"
-		:
-		:
-		:"%rax"
-		);	
+	asm volatile (
+		"mov %%cr0, %%rax\n"
+		"btr $3, %%rax\n"
+		"mov %%rax, %%cr0\n"
+		::: "%rax"
+	);
 }