Index: kernel/arch/abs32le/include/asm.h =================================================================== --- kernel/arch/abs32le/include/asm.h (revision dabdd1aaada964f4510bd352506e4f47c078c88d) +++ kernel/arch/abs32le/include/asm.h (revision 5d618d8f43ac89327c401d395ec9b4fdf6d9c0a9) @@ -40,12 +40,7 @@ #include -extern void interrupt_handlers(void); - -extern void enable_l_apic_in_msr(void); - - -extern void asm_delay_loop(uint32_t); -extern void asm_fake_loop(uint32_t); - +static inline void asm_delay_loop(uint32_t usec) +{ +} static inline __attribute__((noreturn)) void cpu_halt(void) Index: kernel/arch/abs32le/include/atomic.h =================================================================== --- kernel/arch/abs32le/include/atomic.h (revision dabdd1aaada964f4510bd352506e4f47c078c88d) +++ kernel/arch/abs32le/include/atomic.h (revision 5d618d8f43ac89327c401d395ec9b4fdf6d9c0a9) @@ -81,39 +81,16 @@ #define atomic_predec(val) (atomic_postdec(val) - 1) -static inline uint32_t test_and_set(atomic_t *val) { - uint32_t v; - - asm volatile ( - "movl $1, %[v]\n" - "xchgl %[v], %[count]\n" - : [v] "=r" (v), [count] "+m" (val->count) - ); - - return v; +static inline uint32_t test_and_set(atomic_t *val) +{ + uint32_t prev = val->count; + val->count = 1; + return prev; } -/** ia32 specific fast spinlock */ static inline void atomic_lock_arch(atomic_t *val) { - uint32_t tmp; - - preemption_disable(); - asm volatile ( - "0:\n" - "pause\n" /* Pentium 4's HT love this instruction */ - "mov %[count], %[tmp]\n" - "testl %[tmp], %[tmp]\n" - "jnz 0b\n" /* lightweight looping on locked spinlock */ - - "incl %[tmp]\n" /* now use the atomic operation */ - "xchgl %[count], %[tmp]\n" - "testl %[tmp], %[tmp]\n" - "jnz 0b\n" - : [count] "+m" (val->count), [tmp] "=&r" (tmp) - ); - /* - * Prevent critical section code from bleeding out this way up. - */ - CS_ENTER_BARRIER(); + do { + while (val->count); + } while (test_and_set(val)); } Index: kernel/arch/abs32le/include/barrier.h =================================================================== --- kernel/arch/abs32le/include/barrier.h (revision dabdd1aaada964f4510bd352506e4f47c078c88d) +++ kernel/arch/abs32le/include/barrier.h (revision 5d618d8f43ac89327c401d395ec9b4fdf6d9c0a9) @@ -27,5 +27,5 @@ */ -/** @addtogroup ia32 +/** @addtogroup abs32le * @{ */ @@ -33,13 +33,6 @@ */ -#ifndef KERN_ia32_BARRIER_H_ -#define KERN_ia32_BARRIER_H_ - -/* - * NOTE: - * No barriers for critical section (i.e. spinlock) on IA-32 are needed: - * - spinlock_lock() and spinlock_trylock() use serializing XCHG instruction - * - writes cannot pass reads on IA-32 => spinlock_unlock() needs no barriers - */ +#ifndef KERN_abs32le_BARRIER_H_ +#define KERN_abs32le_BARRIER_H_ /* @@ -47,50 +40,13 @@ */ -#define CS_ENTER_BARRIER() asm volatile ("" ::: "memory") -#define CS_LEAVE_BARRIER() asm volatile ("" ::: "memory") +#define CS_ENTER_BARRIER() +#define CS_LEAVE_BARRIER() -static inline void cpuid_serialization(void) -{ - asm volatile ( - "xorl %%eax, %%eax\n" - "cpuid\n" - ::: "eax", "ebx", "ecx", "edx", "memory" - ); -} +#define memory_barrier() +#define read_barrier() +#define write_barrier() -#if defined(CONFIG_FENCES_P4) - #define memory_barrier() asm volatile ("mfence\n" ::: "memory") - #define read_barrier() asm volatile ("lfence\n" ::: "memory") - #ifdef CONFIG_WEAK_MEMORY - #define write_barrier() asm volatile ("sfence\n" ::: "memory") - #else - #define write_barrier() asm volatile ("" ::: "memory"); - #endif -#elif defined(CONFIG_FENCES_P3) - #define memory_barrier() cpuid_serialization() - #define read_barrier() cpuid_serialization() - #ifdef CONFIG_WEAK_MEMORY - #define write_barrier() asm volatile ("sfence\n" ::: "memory") - #else - #define write_barrier() asm volatile ("" ::: "memory"); - #endif -#else - #define memory_barrier() cpuid_serialization() - #define read_barrier() cpuid_serialization() - #ifdef CONFIG_WEAK_MEMORY - #define write_barrier() cpuid_serialization() - #else - #define write_barrier() asm volatile ("" ::: "memory"); - #endif -#endif - -/* - * On ia32, the hardware takes care about instruction and data cache coherence, - * even on SMP systems. We issue a write barrier to be sure that writes - * queueing in the store buffer drain to the memory (even though it would be - * sufficient for them to drain to the D-cache). - */ -#define smc_coherence(a) write_barrier() -#define smc_coherence_block(a, l) write_barrier() +#define smc_coherence(addr) +#define smc_coherence_block(addr, size) #endif Index: kernel/arch/abs32le/include/context.h =================================================================== --- kernel/arch/abs32le/include/context.h (revision dabdd1aaada964f4510bd352506e4f47c078c88d) +++ kernel/arch/abs32le/include/context.h (revision 5d618d8f43ac89327c401d395ec9b4fdf6d9c0a9) @@ -40,5 +40,5 @@ #define context_set(ctx, pc, stack, size) \ - context_set_generic(ctx, pc, stack, size) + context_set_generic(ctx, pc, stack, size) /* Index: kernel/arch/abs32le/include/context_offset.h =================================================================== --- kernel/arch/abs32le/include/context_offset.h (revision dabdd1aaada964f4510bd352506e4f47c078c88d) +++ kernel/arch/abs32le/include/context_offset.h (revision 5d618d8f43ac89327c401d395ec9b4fdf6d9c0a9) @@ -37,10 +37,5 @@ #define OFFSET_PC 0x00 - -#ifdef KERNEL - #define OFFSET_IPL 0x04 -#else - #define OFFSET_TLS 0x04 -#endif +#define OFFSET_IPL 0x04 #endif Index: kernel/arch/abs32le/include/mm/frame.h =================================================================== --- kernel/arch/abs32le/include/mm/frame.h (revision dabdd1aaada964f4510bd352506e4f47c078c88d) +++ kernel/arch/abs32le/include/mm/frame.h (revision 5d618d8f43ac89327c401d395ec9b4fdf6d9c0a9) @@ -40,5 +40,4 @@ #ifdef KERNEL -#ifndef __ASM__ #include @@ -47,5 +46,4 @@ extern void physmem_print(void); -#endif /* __ASM__ */ #endif /* KERNEL */ Index: kernel/arch/abs32le/include/mm/page.h =================================================================== --- kernel/arch/abs32le/include/mm/page.h (revision dabdd1aaada964f4510bd352506e4f47c078c88d) +++ kernel/arch/abs32le/include/mm/page.h (revision 5d618d8f43ac89327c401d395ec9b4fdf6d9c0a9) @@ -43,11 +43,6 @@ #ifdef KERNEL -#ifndef __ASM__ - #define KA2PA(x) (((uintptr_t) (x)) - 0x80000000) - #define PA2KA(x) (((uintptr_t) (x)) + 0x80000000) -#else - #define KA2PA(x) ((x) - 0x80000000) - #define PA2KA(x) ((x) + 0x80000000) -#endif +#define KA2PA(x) (((uintptr_t) (x)) - 0x80000000) +#define PA2KA(x) (((uintptr_t) (x)) + 0x80000000) /* @@ -122,6 +117,4 @@ #define PTE_EXECUTABLE_ARCH(p) 1 -#ifndef __ASM__ - #include #include @@ -129,35 +122,21 @@ #include -/* Page fault error codes. */ - -/** When bit on this position is 0, the page fault was caused by a not-present - * page. - */ -#define PFERR_CODE_P (1 << 0) - -/** When bit on this position is 1, the page fault was caused by a write. */ -#define PFERR_CODE_RW (1 << 1) - -/** When bit on this position is 1, the page fault was caused in user mode. */ -#define PFERR_CODE_US (1 << 2) - -/** When bit on this position is 1, a reserved bit was set in page directory. */ -#define PFERR_CODE_RSVD (1 << 3) - /** Page Table Entry. */ typedef struct { - unsigned present : 1; - unsigned writeable : 1; - unsigned uaccessible : 1; - unsigned page_write_through : 1; - unsigned page_cache_disable : 1; - unsigned accessed : 1; - unsigned dirty : 1; - unsigned pat : 1; - unsigned global : 1; - unsigned soft_valid : 1; /**< Valid content even if the present bit is not set. */ - unsigned avl : 2; - unsigned frame_address : 20; -} __attribute__ ((packed)) pte_t; + unsigned int present : 1; + unsigned int writeable : 1; + unsigned int uaccessible : 1; + unsigned int page_write_through : 1; + unsigned int page_cache_disable : 1; + unsigned int accessed : 1; + unsigned int dirty : 1; + unsigned int pat : 1; + unsigned int global : 1; + + /** Valid content even if the present bit is not set. */ + unsigned int soft_valid : 1; + unsigned int avl : 2; + unsigned int frame_address : 20; +} __attribute__((packed)) pte_t; static inline unsigned int get_pt_flags(pte_t *pt, size_t i) @@ -192,7 +171,5 @@ extern void page_arch_init(void); -extern void page_fault(int n, istate_t *istate); - -#endif /* __ASM__ */ +extern void page_fault(int, istate_t *); #endif /* KERNEL */