Index: uspace/drv/bus/usb/xhci/Makefile =================================================================== --- uspace/drv/bus/usb/xhci/Makefile (revision f4eb6c93ea5a3c62c72e15223a8225f4496177dc) +++ uspace/drv/bus/usb/xhci/Makefile (revision 5cbccd4acbdbb068412b7105503d09315968f2a2) @@ -30,4 +30,5 @@ LIBS = \ + $(LIBUSBHOST_PREFIX)/libusbhost.a \ $(LIBUSB_PREFIX)/libusb.a \ $(LIBDRV_PREFIX)/libdrv.a @@ -35,4 +36,5 @@ EXTRA_CFLAGS += \ -I$(LIBUSB_PREFIX)/include \ + -I$(LIBUSBHOST_PREFIX)/include \ -I$(LIBDRV_PREFIX)/include @@ -40,4 +42,6 @@ SOURCES = \ + hc.c \ + debug.c \ trb_ring.c \ main.c Index: uspace/drv/bus/usb/xhci/debug.c =================================================================== --- uspace/drv/bus/usb/xhci/debug.c (revision 5cbccd4acbdbb068412b7105503d09315968f2a2) +++ uspace/drv/bus/usb/xhci/debug.c (revision 5cbccd4acbdbb068412b7105503d09315968f2a2) @@ -0,0 +1,96 @@ +/* + * Copyright (c) 2017 Ondrej Hlavaty + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * - Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * - Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * - The name of the author may not be used to endorse or promote products + * derived from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR + * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES + * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. + * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT + * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF + * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +/** @addtogroup drvusbxhci + * @{ + */ +/** @file + * Memory-mapped register structures of the xHC. + */ + +#include +#include + +#include "debug.h" + +#define DUMP_REG_FIELD(ptr, title, size, ...) \ + usb_log_debug2(title "%" PRIu##size, XHCI_REG_RD_FIELD(ptr, size, ##__VA_ARGS__)) + +#define DUMP_REG_RANGE(ptr, title, size, ...) \ + usb_log_debug2(title "%" PRIu##size, XHCI_REG_RD_RANGE(ptr, size, ##__VA_ARGS__)) + +#define DUMP_REG_FLAG(ptr, title, size, ...) \ + usb_log_debug2(title "%s", XHCI_REG_RD_FLAG(ptr, size, ##__VA_ARGS__) ? "true" : "false") + +#define DUMP_REG_INNER(set, title, field, size, type, ...) \ + DUMP_REG_##type(&(set)->field, title, size, ##__VA_ARGS__) + +#define DUMP_REG(set, c) DUMP_REG_INNER(set, "\t" #c ": ", c) + +/** + * Dumps all capability registers. + */ +void xhci_dump_cap_regs(xhci_cap_regs_t *cap) +{ + usb_log_debug2("Capabilities:"); + + DUMP_REG(cap, XHCI_CAP_LENGTH); + DUMP_REG(cap, XHCI_CAP_VERSION); + DUMP_REG(cap, XHCI_CAP_MAX_SLOTS); + DUMP_REG(cap, XHCI_CAP_IST); + DUMP_REG(cap, XHCI_CAP_ERST_MAX); + DUMP_REG(cap, XHCI_CAP_SPR); + DUMP_REG(cap, XHCI_CAP_U1EL); + DUMP_REG(cap, XHCI_CAP_U2EL); + DUMP_REG(cap, XHCI_CAP_AC64); + DUMP_REG(cap, XHCI_CAP_BNC); + DUMP_REG(cap, XHCI_CAP_CSZ); + DUMP_REG(cap, XHCI_CAP_PPC); + DUMP_REG(cap, XHCI_CAP_PIND); + DUMP_REG(cap, XHCI_CAP_C); + DUMP_REG(cap, XHCI_CAP_LTC); + DUMP_REG(cap, XHCI_CAP_NSS); + DUMP_REG(cap, XHCI_CAP_PAE); + DUMP_REG(cap, XHCI_CAP_SPC); + DUMP_REG(cap, XHCI_CAP_SEC); + DUMP_REG(cap, XHCI_CAP_CFC); + DUMP_REG(cap, XHCI_CAP_MAX_PSA_SIZE); + DUMP_REG(cap, XHCI_CAP_XECP); + DUMP_REG(cap, XHCI_CAP_DBOFF); + DUMP_REG(cap, XHCI_CAP_RTSOFF); + DUMP_REG(cap, XHCI_CAP_U3C); + DUMP_REG(cap, XHCI_CAP_CMC); + DUMP_REG(cap, XHCI_CAP_FSC); + DUMP_REG(cap, XHCI_CAP_CTC); + DUMP_REG(cap, XHCI_CAP_LEC); + DUMP_REG(cap, XHCI_CAP_CIC); +} + +/** + * @} + */ Index: uspace/drv/bus/usb/xhci/debug.h =================================================================== --- uspace/drv/bus/usb/xhci/debug.h (revision 5cbccd4acbdbb068412b7105503d09315968f2a2) +++ uspace/drv/bus/usb/xhci/debug.h (revision 5cbccd4acbdbb068412b7105503d09315968f2a2) @@ -0,0 +1,47 @@ +/* + * Copyright (c) 2017 Ondrej Hlavaty + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * - Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * - Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * - The name of the author may not be used to endorse or promote products + * derived from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR + * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES + * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. + * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT + * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF + * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +/** @addtogroup drvusbxhci + * @{ + */ +/** @file + * + * Utility functions for debugging and logging purposes. + */ + +#ifndef XHCI_DEBUG_H +#define XHCI_DEBUG_H + +#include "hw_struct/regs.h" + +void xhci_dump_cap_regs(xhci_cap_regs_t *); + +#endif +/** + * @} + */ Index: uspace/drv/bus/usb/xhci/hc.c =================================================================== --- uspace/drv/bus/usb/xhci/hc.c (revision 5cbccd4acbdbb068412b7105503d09315968f2a2) +++ uspace/drv/bus/usb/xhci/hc.c (revision 5cbccd4acbdbb068412b7105503d09315968f2a2) @@ -0,0 +1,103 @@ +/* + * Copyright (c) 2017 Ondrej Hlavaty + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * - Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * - Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * - The name of the author may not be used to endorse or promote products + * derived from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR + * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES + * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. + * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT + * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF + * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +/** @addtogroup drvusbxhci + * @{ + */ +/** @file + * @brief The host controller data bookkeeping. + */ + +#include +#include +#include "debug.h" +#include "hc.h" + +int xhci_hc_gen_irq_code(irq_code_t *code, const hw_res_list_parsed_t *hw_res) +{ + assert(code); + assert(hw_res); + + usb_log_debug("Gen IRQ code, got %zu IRQs, %zu DMA chs, %zu mem rngs, %zu IO rngs", + hw_res->irqs.count, + hw_res->dma_channels.count, + hw_res->mem_ranges.count, + hw_res->io_ranges.count); + + if (hw_res->irqs.count != 1 + || hw_res->dma_channels.count != 0 + || hw_res->mem_ranges.count != 1 + || hw_res->io_ranges.count != 0) { + usb_log_debug("Unexpected HW resources, bailing out."); + return EINVAL; + } + + addr_range_t mmio_range = hw_res->mem_ranges.ranges[0]; + + usb_log_debug("Memory mapped regs at %p (size %zu), IRQ %d.\n", + RNGABSPTR(mmio_range), RNGSZ(mmio_range), hw_res->irqs.irqs[0]); + + xhci_cap_regs_t *cap_regs = NULL; + int ret = pio_enable_range(&mmio_range, (void **)&cap_regs); + if (ret != EOK) + return ret; + + xhci_dump_cap_regs(cap_regs); + + /* + * XHCI uses an Interrupter mechanism. Possibly, we want to set it up here. + */ + code->rangecount = 0; + code->ranges = NULL; + code->cmdcount = 0; + code->cmds = NULL; + + return EOK; +} + +int xhci_hc_status(hcd_t *hcd, uint32_t *status) +{ + usb_log_info("status"); + return ENOTSUP; +} + +int xhci_hc_schedule(hcd_t *hcd, usb_transfer_batch_t *batch) +{ + usb_log_info("schedule"); + return ENOTSUP; +} + +void xhci_hc_interrupt(hcd_t *hcd, uint32_t status) +{ + usb_log_info("Interrupted!"); +} + + +/** + * @} + */ Index: uspace/drv/bus/usb/xhci/hc.h =================================================================== --- uspace/drv/bus/usb/xhci/hc.h (revision 5cbccd4acbdbb068412b7105503d09315968f2a2) +++ uspace/drv/bus/usb/xhci/hc.h (revision 5cbccd4acbdbb068412b7105503d09315968f2a2) @@ -0,0 +1,52 @@ +/* + * Copyright (c) 2017 Ondrej Hlavaty + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * - Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * - Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * - The name of the author may not be used to endorse or promote products + * derived from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR + * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES + * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. + * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT + * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF + * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +/** @addtogroup drvusbxhci + * @{ + */ +/** @file + * @brief The host controller data bookkeeping. + */ + +#include +#include "hw_struct/regs.h" + +typedef struct xhci_hc { + xhci_cap_regs_t *cap_regs; + xhci_op_regs_t *op_regs; +} xhci_hc_t; + +int xhci_hc_gen_irq_code(irq_code_t *, const hw_res_list_parsed_t *); +int xhci_hc_status(hcd_t *, uint32_t *); +int xhci_hc_schedule(hcd_t *, usb_transfer_batch_t *); +void xhci_hc_interrupt(hcd_t *, uint32_t); + + +/** + * @} + */ Index: uspace/drv/bus/usb/xhci/hw_struct/context.h =================================================================== --- uspace/drv/bus/usb/xhci/hw_struct/context.h (revision f4eb6c93ea5a3c62c72e15223a8225f4496177dc) +++ uspace/drv/bus/usb/xhci/hw_struct/context.h (revision 5cbccd4acbdbb068412b7105503d09315968f2a2) @@ -67,5 +67,5 @@ #define XHCI_EP_TR_DPTR(ctx) XHCI_DWORD_EXTRACT((ctx).data[2], 63, 4) -} ep_ctx_t; +} ep_ctx_t __attribute__((packed)); /** @@ -93,5 +93,5 @@ #define XHCI_SLOT_SLOT_STATE(ctx) XHCI_DWORD_EXTRACT((ctx).data[3], 31, 27) -} xhci_slot_ctx_t; +} xhci_slot_ctx_t __attribute__((packed)); /** @@ -108,5 +108,5 @@ typedef struct xhci_stream_ctx { uint64_t data [2]; -} xhci_stream_ctx_t; +} xhci_stream_ctx_t __attribute__((packed)); #endif Index: uspace/drv/bus/usb/xhci/hw_struct/regs.h =================================================================== --- uspace/drv/bus/usb/xhci/hw_struct/regs.h (revision 5cbccd4acbdbb068412b7105503d09315968f2a2) +++ uspace/drv/bus/usb/xhci/hw_struct/regs.h (revision 5cbccd4acbdbb068412b7105503d09315968f2a2) @@ -0,0 +1,343 @@ +/* + * Copyright (c) 2017 Ondrej Hlavaty + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * - Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * - Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * - The name of the author may not be used to endorse or promote products + * derived from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR + * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES + * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. + * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT + * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF + * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +/** @addtogroup drvusbxhci + * @{ + */ +/** @file + * Memory-mapped register structures of the xHC. + */ + +#ifndef XHCI_REGS_H +#define XHCI_REGS_H + +#include +#include +#include "common.h" + +/* + * The macros XHCI_REG_* might seem a bit magic. It is the most compact way to + * provide flexible interface abstracting from the real storage of given + * register, but to avoid having to specify several constants per register. + * + * The key thing here is the order of macro expansion, expanding one argument + * as more arguments (comma delimited) for another macro. + */ + +#define host2xhci(size, val) host2uint##size##_t_le((val)) +#define xhci2host(size, val) uint##size##_t_le2host((val)) + +#define XHCI_REG_RD_FIELD(ptr, size) \ + xhci2host(size, pio_read_##size((ptr))) + +#define XHCI_REG_RD_RANGE(ptr, size, hi, lo) \ + BIT_RANGE_EXTRACT(uint##size##_t, hi, lo, XHCI_REG_RD_FIELD((ptr), size)) + +#define XHCI_REG_RD_FLAG(ptr, size, offset) \ + XHCI_REG_RD_RANGE((ptr), size, offset, offset) + +#define XHCI_REG_RD_INNER(reg_set, field, size, type, ...) \ + XHCI_REG_RD_##type(&((reg_set)->field), size, ##__VA_ARGS__) + +#define XHCI_REG_RD(reg_set, reg_spec) XHCI_REG_RD_INNER(reg_set, reg_spec) + +#define XHCI_REG_SET_FIELD(ptr, value, size) \ + pio_write_##size((ptr), host2xhci(size, value)) + +#define XHCI_REG_SET_RANGE(ptr, value, size, hi, lo) \ + pio_change_##size((ptr), host2xhci(size, (value) << (lo)), host2xhci(size, BIT_RANGE(uint##size##_t, hi, lo)), 5); + +#define XHCI_REG_SET_FLAG(ptr, value, size, offset) \ + XHCI_REG_SET_RANGE(ptr, value, size, offset, offset) + +#define XHCI_REG_SET_INNER(reg_set, value, field, size, type, ...) \ + XHCI_REG_SET_##type(&(reg_set)->field, value, size, ##__VA_ARGS__) + +#define XHCI_REG_SET(reg_set, reg_spec) XHCI_REG_SET_INNER(reg_set, value, reg_spec) + +/* + * The register specifiers are to be used as the reg_spec argument. + * + * The values are field, bitsize, type, (type specific args) + * When the type is RANGE: hi, lo + */ +#define XHCI_CAP_LENGTH caplength, 8, FIELD +#define XHCI_CAP_VERSION hciversion, 16, FIELD +#define XHCI_CAP_MAX_SLOTS hcsparams1, 32, RANGE, 7, 0 +#define XHCI_CAP_MAX_INTRS hcsparams1, 32, RANGE, 18, 8 +#define XHCI_CAP_MAX_PORTS hcsparams1, 32, RANGE, 31, 24 +#define XHCI_CAP_IST hcsparams2, 32, RANGE, 3, 0 +#define XHCI_CAP_ERST_MAX hcsparams2, 32, RANGE, 7, 4 +#define XHCI_CAP_SPR hcsparams2, 32, RANGE, 26, 26 +#define XHCI_CAP_U1EL hcsparams3, 32, RANGE, 7, 0 +#define XHCI_CAP_U2EL hcsparams3, 32, RANGE, 31, 16 +#define XHCI_CAP_AC64 hccparams1, 32, FLAG, 0 +#define XHCI_CAP_BNC hccparams1, 32, FLAG, 1 +#define XHCI_CAP_CSZ hccparams1, 32, FLAG, 2 +#define XHCI_CAP_PPC hccparams1, 32, FLAG, 3 +#define XHCI_CAP_PIND hccparams1, 32, FLAG, 4 +#define XHCI_CAP_C hccparams1, 32, FLAG, 5 +#define XHCI_CAP_LTC hccparams1, 32, FLAG, 6 +#define XHCI_CAP_NSS hccparams1, 32, FLAG, 7 +#define XHCI_CAP_PAE hccparams1, 32, FLAG, 8 +#define XHCI_CAP_SPC hccparams1, 32, FLAG, 9 +#define XHCI_CAP_SEC hccparams1, 32, FLAG, 10 +#define XHCI_CAP_CFC hccparams1, 32, FLAG, 11 +#define XHCI_CAP_MAX_PSA_SIZE hccparams1, 32, FLAG, 12 +#define XHCI_CAP_XECP hccparams1, 32, FLAG, 13 +#define XHCI_CAP_DBOFF dboff, 32, FIELD +#define XHCI_CAP_RTSOFF rtsoff, 32, FIELD +#define XHCI_CAP_U3C hccparams2, 32, FLAG, 0 +#define XHCI_CAP_CMC hccparams2, 32, FLAG, 1 +#define XHCI_CAP_FSC hccparams2, 32, FLAG, 2 +#define XHCI_CAP_CTC hccparams2, 32, FLAG, 3 +#define XHCI_CAP_LEC hccparams2, 32, FLAG, 4 +#define XHCI_CAP_CIC hccparams2, 32, FLAG, 5 + +/** HC capability registers: section 5.3 */ +typedef const struct xhci_cap_regs { + + /* Size of this structure, offset for the operation registers */ + const ioport8_t caplength; + + const PADD8; + + /* BCD of specification version */ + const ioport16_t hciversion; + + /* + * 7:0 - MaxSlots + * 18:8 - MaxIntrs + * 31:24 - MaxPorts + */ + const ioport32_t hcsparams1; + + /* + * 0:3 - IST + * 7:4 - ERST Max + * 21:25 - Max Scratchpad Bufs Hi + * 26 - SPR + * 31:27 - Max Scratchpad Bufs Lo + */ + const ioport32_t hcsparams2; + + /* + * 7:0 - U1 Device Exit Latency + * 31:16 - U2 Device Exit Latency + */ + const ioport32_t hcsparams3; + + /* + * 11 10 9 8 7 6 5 4 3 2 1 0 + * 11:0 - CFC SEC SPC PAE NSS LTC C PIND PPC CSZ BNC AC64 + * 15:12 - MaxPSASize + * 31:16 - xECP + */ + const ioport32_t hccparams1; + + /* + * 31:2 - Doorbell Array Offset + */ + const ioport32_t dboff; + + /* + * 31:5 - Runtime Register Space Offset + */ + const ioport32_t rtsoff; + + /* + * 5 4 3 2 1 0 + * 5:0 - Flags: CIC LEC CTC FSC CMC U3C + */ + const ioport32_t hccparams2; + + // the rest to operational registers is reserved +} xhci_cap_regs_t; + + +/** + * XHCI Port Register Set: section 5.4, table 32 + */ +typedef struct xhci_port_regs { + /* + * 4 3 2 1 0 + * 4:0 - PR OCA Z PED CCS + * 8:5 - PLS + * 9 - PP + * 13:10 - Port Speed + * 15:14 - PIC + * 27 26 25 24 23 22 21 20 19 18 17 16 + * 27:16 - WOE WDE WCE CAS CEC PLC PRC OCC WRC PEC CSC LWS + * 30 - DR + * 31 - WPR + */ + ioport32_t portsc; + + /* + * Contents of this fields depends on the protocol supported by the port. + * USB3: + * 7:0 - U1 Timeout + * 15:8 - U2 Timeout + * 16 - Force Link PM Accept + * USB2: + * 0:2 - L1S + * 3 - RWE + * 7:4 - BESL + * 15:8 - L1 Device Slot + * 16 - HLE + * 31:28 - Test Mode + */ + ioport32_t portpmsc; + + /* + * This field is valid only for USB3 ports. + * 15:0 - Link Error Count + * 19:16 - RLC + * 23:20 - TLC + */ + ioport32_t portli; + + /* + * This field is valid only for USB2 ports. + * 1:0 - HIRDM + * 9:2 - L1 Timeout + * 13:10 - BESLD + */ + ioport32_t porthlpmc; +} xhci_port_regs_t; + +/** + * XHCI Operational Registers: section 5.4 + */ +typedef struct xhci_op_regs { + + /* + * 3 2 1 0 + * 3:0 - HSE INTE HCRST R/S + * + * 11 10 9 8 7 + * 11:7 - EU3S EWE CRS CSS LHCRST + * 13 - CME + */ + ioport32_t usbcmd; + + /* + * 4 3 2 1 0 + * 4:0 - PCD EINT HSE _ HCH + * + * 12 11 10 9 8 + * 12:8 - CE CNR SRE RSS SSS + */ + ioport32_t usbsts; + + /* + * Bitmask of page sizes supported: 128M .. 4K + */ + ioport32_t pagesize; + + PADD32[2]; + + /* + * 15:0 - Notification enable + */ + ioport32_t dnctrl; + + /* 3 2 1 0 + * 3:0 - CRR CA CS RCS + * 64:6 - Command Ring Pointer + */ + ioport32_t crcr_lo; + ioport32_t crcr_hi; + + PADD32[4]; + + ioport32_t dcbaap_lo; + ioport32_t dcbaap_hi; + + /* + * 7:0 - MaxSlotsEn + * 8 - U3E + * 9 - CIE + */ + ioport32_t config; + + PADD32[36 * 4 + 1]; + + /* + * Individual ports register sets + */ + xhci_port_regs_t portrs[256]; +} xhci_op_regs_t; + +/** + * Interrupter Register Set: section 5.5.2 + */ +typedef struct xhci_interrupter_regs { + /* + * 0 - Interrupt Pending + * 1 - Interrupt Enable + */ + ioport32_t iman; + + /* + * 15:0 - Interrupt Moderation Interval + * 31:16 - Interrupt Moderation Counter + */ + ioport32_t imod; + + ioport32_t erstsz; + + PADD32; + + ioport32_t erstba_lo; + ioport32_t erstba_hi; + + /* + * 2:0 - Dequeue ERST Segment Index + * 3 - Event Handler Busy + * 63:4 - Event Ring Dequeue Pointer + */ + ioport32_t erdp_lo; + ioport32_t erdp_hi; +} xhci_interrupter_regs_t; + +/** + * XHCI Runtime registers: section 5.5 + */ +typedef struct xhci_rt_regs { + ioport32_t mfindex; + + PADD32 [5]; + + xhci_interrupter_regs_t ir[1024]; +} xhci_rt_regs_t; + +#endif +/** + * @} + */ Index: uspace/drv/bus/usb/xhci/main.c =================================================================== --- uspace/drv/bus/usb/xhci/main.c (revision f4eb6c93ea5a3c62c72e15223a8225f4496177dc) +++ uspace/drv/bus/usb/xhci/main.c (revision 5cbccd4acbdbb068412b7105503d09315968f2a2) @@ -39,7 +39,37 @@ #include #include +#include + +#include "hc.h" #define NAME "xhci" +static int xhci_driver_init(hcd_t *, const hw_res_list_parsed_t *, bool); +static void xhci_driver_fini(hcd_t *); + +static const ddf_hc_driver_t xhci_ddf_hc_driver = { + .hc_speed = USB_SPEED_SUPER, + .irq_code_gen = xhci_hc_gen_irq_code, + .init = xhci_driver_init, + .fini = xhci_driver_fini, + .name = "XHCI-PCI", + .ops = { + .schedule = xhci_hc_schedule, + .irq_hook = xhci_hc_interrupt, + .status_hook = xhci_hc_status, + } +}; + +static int xhci_driver_init(hcd_t *hcd, const hw_res_list_parsed_t *res, bool irq) +{ + usb_log_info("Initializing"); + return ENOTSUP; +} + +static void xhci_driver_fini(hcd_t *hcd) +{ + usb_log_info("Finishing"); + assert(hcd); +} /** Initializes a new ddf driver instance of XHCI hcd. @@ -50,6 +80,6 @@ static int xhci_dev_add(ddf_dev_t *device) { - usb_log_info("Requested to add device %s", ddf_dev_get_name(device)); - return ENOTSUP; + usb_log_info("Adding device %s", ddf_dev_get_name(device)); + return hcd_ddf_add_hc(device, &xhci_ddf_hc_driver); } @@ -76,5 +106,5 @@ { log_init(NAME); - logctl_set_log_level(NAME, LVL_DEBUG); + logctl_set_log_level(NAME, LVL_DEBUG2); return ddf_driver_main(&xhci_driver); }