Index: kernel/arch/ia64/include/asm.h
===================================================================
--- kernel/arch/ia64/include/asm.h	(revision e86a849a744c5d659718b8d55becc3bbee6655ac)
+++ kernel/arch/ia64/include/asm.h	(revision 5bda2f3ec5d347e6cd33782ee9f7583f6d3aeda4)
@@ -27,5 +27,5 @@
  */
 
-/** @addtogroup ia64	
+/** @addtogroup ia64
  * @{
  */
@@ -41,14 +41,17 @@
 #include <arch/register.h>
 
-#define IA64_IOSPACE_ADDRESS 0xE001000000000000ULL
+#define IA64_IOSPACE_ADDRESS  0xE001000000000000ULL
 
 static inline void pio_write_8(ioport8_t *port, uint8_t v)
 {
 	uintptr_t prt = (uintptr_t) port;
-
-	*((ioport8_t *)(IA64_IOSPACE_ADDRESS +
+	
+	*((ioport8_t *) (IA64_IOSPACE_ADDRESS +
 	    ((prt & 0xfff) | ((prt >> 2) << 12)))) = v;
-
-	asm volatile ("mf\n" ::: "memory");
+	
+	asm volatile (
+		"mf\n"
+		::: "memory"
+	);
 }
 
@@ -56,9 +59,12 @@
 {
 	uintptr_t prt = (uintptr_t) port;
-
-	*((ioport16_t *)(IA64_IOSPACE_ADDRESS +
+	
+	*((ioport16_t *) (IA64_IOSPACE_ADDRESS +
 	    ((prt & 0xfff) | ((prt >> 2) << 12)))) = v;
-
-	asm volatile ("mf\n" ::: "memory");
+	
+	asm volatile (
+		"mf\n"
+		::: "memory"
+	);
 }
 
@@ -66,9 +72,12 @@
 {
 	uintptr_t prt = (uintptr_t) port;
-
-	*((ioport32_t *)(IA64_IOSPACE_ADDRESS +
+	
+	*((ioport32_t *) (IA64_IOSPACE_ADDRESS +
 	    ((prt & 0xfff) | ((prt >> 2) << 12)))) = v;
-
-	asm volatile ("mf\n" ::: "memory");
+	
+	asm volatile (
+		"mf\n"
+		::: "memory"
+	);
 }
 
@@ -76,8 +85,11 @@
 {
 	uintptr_t prt = (uintptr_t) port;
-
-	asm volatile ("mf\n" ::: "memory");
-
-	return *((ioport8_t *)(IA64_IOSPACE_ADDRESS +
+	
+	asm volatile (
+		"mf\n"
+		::: "memory"
+	);
+	
+	return *((ioport8_t *) (IA64_IOSPACE_ADDRESS +
 	    ((prt & 0xfff) | ((prt >> 2) << 12))));
 }
@@ -86,8 +98,11 @@
 {
 	uintptr_t prt = (uintptr_t) port;
-
-	asm volatile ("mf\n" ::: "memory");
-
-	return *((ioport16_t *)(IA64_IOSPACE_ADDRESS +
+	
+	asm volatile (
+		"mf\n"
+		::: "memory"
+	);
+	
+	return *((ioport16_t *) (IA64_IOSPACE_ADDRESS +
 	    ((prt & 0xfff) | ((prt >> 2) << 12))));
 }
@@ -96,8 +111,11 @@
 {
 	uintptr_t prt = (uintptr_t) port;
-
-	asm volatile ("mf\n" ::: "memory");
-
-	return *((ioport32_t *)(IA64_IOSPACE_ADDRESS +
+	
+	asm volatile (
+		"mf\n"
+		::: "memory"
+	);
+	
+	return *((ioport32_t *) (IA64_IOSPACE_ADDRESS +
 	    ((prt & 0xfff) | ((prt >> 2) << 12))));
 }
@@ -112,13 +130,24 @@
 {
 	uint64_t v;
-
-	//I'm not sure why but this code bad inlines in scheduler, 
-	//so THE shifts about 16B and causes kernel panic
-	//asm volatile ("and %0 = %1, r12" : "=r" (v) : "r" (~(STACK_SIZE-1)));
-	//return v;
-	
-	//this code have the same meaning but inlines well
-	asm volatile ("mov %0 = r12" : "=r" (v)  );
-	return v & (~(STACK_SIZE-1));
+	
+	/* I'm not sure why but this code bad inlines in scheduler,
+	   so THE shifts about 16B and causes kernel panic
+	   
+	   asm volatile (
+	       "and %[value] = %[mask], r12"
+	       : [value] "=r" (v)
+	       : [mask] "r" (~(STACK_SIZE - 1))
+	   );
+	   return v;
+	   
+	   This code have the same meaning but inlines well.
+	*/
+	
+	asm volatile (
+		"mov %[value] = r12"
+		: [value] "=r" (v)
+	);
+	
+	return (v & (~(STACK_SIZE - 1)));
 }
 
@@ -131,5 +160,8 @@
 	uint64_t v;
 	
-	asm volatile ("mov %0 = psr\n" : "=r" (v));
+	asm volatile (
+		"mov %[value] = psr\n"
+		: [value] "=r" (v)
+	);
 	
 	return v;
@@ -144,5 +176,8 @@
 	uint64_t v;
 	
-	asm volatile ("mov %0 = cr.iva\n" : "=r" (v));
+	asm volatile (
+		"mov %[value] = cr.iva\n"
+		: [value] "=r" (v)
+	);
 	
 	return v;
@@ -155,5 +190,8 @@
 static inline void iva_write(uint64_t v)
 {
-	asm volatile ("mov cr.iva = %0\n" : : "r" (v));
+	asm volatile (
+		"mov cr.iva = %[value]\n"
+		:: [value] "r" (v)
+	);
 }
 
@@ -167,5 +205,8 @@
 	uint64_t v;
 	
-	asm volatile ("mov %0 = cr.ivr\n" : "=r" (v));
+	asm volatile (
+		"mov %[value] = cr.ivr\n"
+		: [value] "=r" (v)
+	);
 	
 	return v;
@@ -176,5 +217,8 @@
 	uint64_t v;
 	
-	asm volatile ("mov %0 = cr64\n" : "=r" (v));
+	asm volatile (
+		"mov %[value] = cr64\n"
+		: [value] "=r" (v)
+	);
 	
 	return v;
@@ -188,5 +232,8 @@
 static inline void itc_write(uint64_t v)
 {
-	asm volatile ("mov ar.itc = %0\n" : : "r" (v));
+	asm volatile (
+		"mov ar.itc = %[value]\n"
+		:: [value] "r" (v)
+	);
 }
 
@@ -199,5 +246,8 @@
 	uint64_t v;
 	
-	asm volatile ("mov %0 = ar.itc\n" : "=r" (v));
+	asm volatile (
+		"mov %[value] = ar.itc\n"
+		: [value] "=r" (v)
+	);
 	
 	return v;
@@ -210,5 +260,8 @@
 static inline void itm_write(uint64_t v)
 {
-	asm volatile ("mov cr.itm = %0\n" : : "r" (v));
+	asm volatile (
+		"mov cr.itm = %[value]\n"
+		:: [value] "r" (v)
+	);
 }
 
@@ -221,5 +274,8 @@
 	uint64_t v;
 	
-	asm volatile ("mov %0 = cr.itm\n" : "=r" (v));
+	asm volatile (
+		"mov %[value] = cr.itm\n"
+		: [value] "=r" (v)
+	);
 	
 	return v;
@@ -234,5 +290,8 @@
 	uint64_t v;
 	
-	asm volatile ("mov %0 = cr.itv\n" : "=r" (v));
+	asm volatile (
+		"mov %[value] = cr.itv\n"
+		: [value] "=r" (v)
+	);
 	
 	return v;
@@ -245,5 +304,8 @@
 static inline void itv_write(uint64_t v)
 {
-	asm volatile ("mov cr.itv = %0\n" : : "r" (v));
+	asm volatile (
+		"mov cr.itv = %[value]\n"
+		:: [value] "r" (v)
+	);
 }
 
@@ -254,5 +316,8 @@
 static inline void eoi_write(uint64_t v)
 {
-	asm volatile ("mov cr.eoi = %0\n" : : "r" (v));
+	asm volatile (
+		"mov cr.eoi = %[value]\n"
+		:: [value] "r" (v)
+	);
 }
 
@@ -264,6 +329,9 @@
 {
 	uint64_t v;
-
-	asm volatile ("mov %0 = cr.tpr\n"  : "=r" (v));
+	
+	asm volatile (
+		"mov %[value] = cr.tpr\n"
+		: [value] "=r" (v)
+	);
 	
 	return v;
@@ -276,5 +344,8 @@
 static inline void tpr_write(uint64_t v)
 {
-	asm volatile ("mov cr.tpr = %0\n" : : "r" (v));
+	asm volatile (
+		"mov cr.tpr = %[value]\n"
+		:: [value] "r" (v)
+	);
 }
 
@@ -291,8 +362,8 @@
 	
 	asm volatile (
-		"mov %0 = psr\n"
-		"rsm %1\n"
-		: "=r" (v)
-		: "i" (PSR_I_MASK)
+		"mov %[value] = psr\n"
+		"rsm %[mask]\n"
+		: [value] "=r" (v)
+		: [mask] "i" (PSR_I_MASK)
 	);
 	
@@ -312,10 +383,10 @@
 	
 	asm volatile (
-		"mov %0 = psr\n"
-		"ssm %1\n"
+		"mov %[value] = psr\n"
+		"ssm %[mask]\n"
 		";;\n"
 		"srlz.d\n"
-		: "=r" (v)
-		: "i" (PSR_I_MASK)
+		: [value] "=r" (v)
+		: [mask] "i" (PSR_I_MASK)
 	);
 	
@@ -349,5 +420,8 @@
 static inline void pk_disable(void)
 {
-	asm volatile ("rsm %0\n" : : "i" (PSR_PK_MASK));
+	asm volatile (
+		"rsm %[mask]\n"
+		:: [mask] "i" (PSR_PK_MASK)
+	);
 }
 
Index: kernel/arch/ia64/include/interrupt.h
===================================================================
--- kernel/arch/ia64/include/interrupt.h	(revision e86a849a744c5d659718b8d55becc3bbee6655ac)
+++ kernel/arch/ia64/include/interrupt.h	(revision 5bda2f3ec5d347e6cd33782ee9f7583f6d3aeda4)
@@ -40,5 +40,5 @@
 
 /** ia64 has 256 INRs. */
-#define INR_COUNT	256
+#define INR_COUNT  256
 
 /*
@@ -47,25 +47,28 @@
  * to genarch.
  */
-#define IVT_ITEMS       0
-#define IVT_FIRST       0
+#define IVT_ITEMS  0
+#define IVT_FIRST  0
 
 /** External Interrupt vectors. */
 
-#define VECTOR_TLB_SHOOTDOWN_IPI 0xf0
-#define INTERRUPT_TIMER		255
-#define IRQ_KBD			(0x01 + LEGACY_INTERRUPT_BASE)
-#define IRQ_MOUSE		(0x0c + LEGACY_INTERRUPT_BASE)
-#define INTERRUPT_SPURIOUS	15
-#define LEGACY_INTERRUPT_BASE	0x20
+#define VECTOR_TLB_SHOOTDOWN_IPI  0xf0
+
+#define INTERRUPT_SPURIOUS  15
+#define INTERRUPT_TIMER     255
+
+#define LEGACY_INTERRUPT_BASE  0x20
+
+#define IRQ_KBD    (0x01 + LEGACY_INTERRUPT_BASE)
+#define IRQ_MOUSE  (0x0c + LEGACY_INTERRUPT_BASE)
 
 /** General Exception codes. */
-#define GE_ILLEGALOP		0
-#define GE_PRIVOP		1
-#define GE_PRIVREG		2
-#define GE_RESREGFLD		3
-#define GE_DISBLDISTRAN		4
-#define GE_ILLEGALDEP		8
+#define GE_ILLEGALOP     0
+#define GE_PRIVOP        1
+#define GE_PRIVREG       2
+#define GE_RESREGFLD     3
+#define GE_DISBLDISTRAN  4
+#define GE_ILLEGALDEP    8
 
-#define EOI	0		/**< The actual value doesn't matter. */
+#define EOI  0  /**< The actual value doesn't matter. */
 
 typedef struct {
@@ -100,5 +103,5 @@
 	uint128_t f30;
 	uint128_t f31;
-		
+	
 	uintptr_t ar_bsp;
 	uintptr_t ar_bspstore;
@@ -132,5 +135,5 @@
 {
 	istate->cr_iip = retaddr;
-	istate->cr_ipsr.ri = 0;		/* return to instruction slot #0 */
+	istate->cr_ipsr.ri = 0;    /* return to instruction slot #0 */
 }
 
Index: kernel/arch/ia64/include/mm/as.h
===================================================================
--- kernel/arch/ia64/include/mm/as.h	(revision e86a849a744c5d659718b8d55becc3bbee6655ac)
+++ kernel/arch/ia64/include/mm/as.h	(revision 5bda2f3ec5d347e6cd33782ee9f7583f6d3aeda4)
@@ -27,5 +27,5 @@
  */
 
-/** @addtogroup ia64mm	
+/** @addtogroup ia64mm
  * @{
  */
@@ -36,12 +36,12 @@
 #define KERN_ia64_AS_H_
 
-#define KERNEL_ADDRESS_SPACE_SHADOWED_ARCH	0
+#define KERNEL_ADDRESS_SPACE_SHADOWED_ARCH  0
 
-#define KERNEL_ADDRESS_SPACE_START_ARCH		(unsigned long) 0xe000000000000000ULL
-#define KERNEL_ADDRESS_SPACE_END_ARCH		(unsigned long) 0xffffffffffffffffULL
-#define USER_ADDRESS_SPACE_START_ARCH		(unsigned long) 0x0000000000000000ULL
-#define USER_ADDRESS_SPACE_END_ARCH		(unsigned long) 0xdfffffffffffffffULL
+#define KERNEL_ADDRESS_SPACE_START_ARCH  ((unsigned long) 0xe000000000000000ULL)
+#define KERNEL_ADDRESS_SPACE_END_ARCH    ((unsigned long) 0xffffffffffffffffULL)
+#define USER_ADDRESS_SPACE_START_ARCH    ((unsigned long) 0x0000000000000000ULL)
+#define USER_ADDRESS_SPACE_END_ARCH      ((unsigned long) 0xdfffffffffffffffULL)
 
-#define USTACK_ADDRESS_ARCH	0x0000000ff0000000ULL
+#define USTACK_ADDRESS_ARCH  0x0000000ff0000000ULL
 
 typedef struct {
@@ -50,7 +50,7 @@
 #include <genarch/mm/as_ht.h>
 
-#define as_constructor_arch(as, flags)		(as != as)
-#define as_destructor_arch(as)			(as != as)
-#define as_create_arch(as, flags)		(as != as)
+#define as_constructor_arch(as, flags)  (as != as)
+#define as_destructor_arch(as)          (as != as)
+#define as_create_arch(as, flags)       (as != as)
 #define as_deinstall_arch(as)
 #define as_invalidate_translation_cache(as, page, cnt)
Index: kernel/arch/ia64/include/mm/page.h
===================================================================
--- kernel/arch/ia64/include/mm/page.h	(revision e86a849a744c5d659718b8d55becc3bbee6655ac)
+++ kernel/arch/ia64/include/mm/page.h	(revision 5bda2f3ec5d347e6cd33782ee9f7583f6d3aeda4)
@@ -28,5 +28,5 @@
  */
 
-/** @addtogroup ia64mm	
+/** @addtogroup ia64mm
  * @{
  */
@@ -39,15 +39,15 @@
 #include <arch/mm/frame.h>
 
-#define PAGE_SIZE	FRAME_SIZE
-#define PAGE_WIDTH	FRAME_WIDTH
+#define PAGE_SIZE   FRAME_SIZE
+#define PAGE_WIDTH  FRAME_WIDTH
 
 #ifdef KERNEL
 
 /** Bit width of the TLB-locked portion of kernel address space. */
-#define KERNEL_PAGE_WIDTH		28	/* 256M */
-#define IO_PAGE_WIDTH			26	/* 64M */
-#define FW_PAGE_WIDTH			28	/* 256M */
-
-#define USPACE_IO_PAGE_WIDTH		12	/* 4K */
+#define KERNEL_PAGE_WIDTH  28  /* 256M */
+#define IO_PAGE_WIDTH      26  /* 64M */
+#define FW_PAGE_WIDTH      28  /* 256M */
+
+#define USPACE_IO_PAGE_WIDTH  12  /* 4K */
 
 
@@ -59,45 +59,45 @@
 
 /* Firmware area (bellow 4GB in phys mem) */
-#define FW_OFFSET             0x00000000F0000000
+#define FW_OFFSET   0x00000000F0000000
 /* Legacy IO space */
-#define IO_OFFSET             0x0001000000000000
+#define IO_OFFSET   0x0001000000000000
 /* Videoram - now mapped to 0 as VGA text mode vram on 0xb8000 */
-#define VIO_OFFSET            0x0002000000000000
-
-
-#define PPN_SHIFT			12
-
-#define VRN_SHIFT			61
-#define VRN_MASK			(7LL << VRN_SHIFT)
-#define VA2VRN(va)			((va)>>VRN_SHIFT)
+#define VIO_OFFSET  0x0002000000000000
+
+
+#define PPN_SHIFT  12
+
+#define VRN_SHIFT   61
+#define VRN_MASK    (7ULL << VRN_SHIFT)
+#define VA2VRN(va)  ((va) >> VRN_SHIFT)
 
 #ifdef __ASM__
-#define VRN_KERNEL	 		7
+	#define VRN_KERNEL  7
 #else
-#define VRN_KERNEL	 		7LL
+	#define VRN_KERNEL  7ULL
 #endif
 
-#define REGION_REGISTERS 		8
-
-#define KA2PA(x)	((uintptr_t) (x - (VRN_KERNEL << VRN_SHIFT)))
-#define PA2KA(x)	((uintptr_t) (x + (VRN_KERNEL << VRN_SHIFT)))
-
-#define VHPT_WIDTH 			20	/* 1M */
-#define VHPT_SIZE 			(1 << VHPT_WIDTH)
-
-#define PTA_BASE_SHIFT			15
+#define REGION_REGISTERS  8
+
+#define KA2PA(x)  ((uintptr_t) ((x) - (VRN_KERNEL << VRN_SHIFT)))
+#define PA2KA(x)  ((uintptr_t) ((x) + (VRN_KERNEL << VRN_SHIFT)))
+
+#define VHPT_WIDTH  20  /* 1M */
+#define VHPT_SIZE   (1 << VHPT_WIDTH)
+
+#define PTA_BASE_SHIFT  15
 
 /** Memory Attributes. */
-#define MA_WRITEBACK	0x0
-#define MA_UNCACHEABLE	0x4
+#define MA_WRITEBACK    0x00
+#define MA_UNCACHEABLE  0x04
 
 /** Privilege Levels. Only the most and the least privileged ones are ever used. */
-#define PL_KERNEL	0x0
-#define PL_USER		0x3
+#define PL_KERNEL  0x00
+#define PL_USER    0x03
 
 /* Access Rigths. Only certain combinations are used by the kernel. */
-#define AR_READ		0x0
-#define AR_EXECUTE	0x1
-#define AR_WRITE	0x2
+#define AR_READ     0x00
+#define AR_EXECUTE  0x01
+#define AR_WRITE    0x02
 
 #ifndef __ASM__
@@ -113,5 +113,5 @@
 struct vhpt_tag_info {
 	unsigned long long tag : 63;
-	unsigned ti : 1;
+	unsigned int ti : 1;
 } __attribute__ ((packed));
 
@@ -123,26 +123,26 @@
 struct vhpt_entry_present {
 	/* Word 0 */
-	unsigned p : 1;
-	unsigned : 1;
-	unsigned ma : 3;
-	unsigned a : 1;
-	unsigned d : 1;
-	unsigned pl : 2;
-	unsigned ar : 3;
+	unsigned int p : 1;
+	unsigned int : 1;
+	unsigned int ma : 3;
+	unsigned int a : 1;
+	unsigned int d : 1;
+	unsigned int pl : 2;
+	unsigned int ar : 3;
 	unsigned long long ppn : 38;
-	unsigned : 2;
-	unsigned ed : 1;
-	unsigned ig1 : 11;
+	unsigned int : 2;
+	unsigned int ed : 1;
+	unsigned int ig1 : 11;
 	
 	/* Word 1 */
-	unsigned : 2;
-	unsigned ps : 6;
-	unsigned key : 24;
-	unsigned : 32;
+	unsigned int : 2;
+	unsigned int ps : 6;
+	unsigned int key : 24;
+	unsigned int : 32;
 	
 	/* Word 2 */
 	union vhpt_tag tag;
 	
-	/* Word 3 */													
+	/* Word 3 */
 	uint64_t ig3 : 64;
 } __attribute__ ((packed));
@@ -150,21 +150,21 @@
 struct vhpt_entry_not_present {
 	/* Word 0 */
-	unsigned p : 1;
+	unsigned int p : 1;
 	unsigned long long ig0 : 52;
-	unsigned ig1 : 11;
+	unsigned int ig1 : 11;
 	
 	/* Word 1 */
-	unsigned : 2;
-	unsigned ps : 6;
+	unsigned int : 2;
+	unsigned int ps : 6;
 	unsigned long long ig2 : 56;
-
+	
 	/* Word 2 */
 	union vhpt_tag tag;
 	
-	/* Word 3 */													
+	/* Word 3 */
 	uint64_t ig3 : 64;
 } __attribute__ ((packed));
 
-typedef union vhpt_entry {
+typedef union {
 	struct vhpt_entry_present present;
 	struct vhpt_entry_not_present not_present;
@@ -173,22 +173,22 @@
 
 struct region_register_map {
-	unsigned ve : 1;
-	unsigned : 1;
-	unsigned ps : 6;
-	unsigned rid : 24;
-	unsigned : 32;
-} __attribute__ ((packed));
-
-typedef union region_register {
+	unsigned int ve : 1;
+	unsigned int : 1;
+	unsigned int ps : 6;
+	unsigned int rid : 24;
+	unsigned int : 32;
+} __attribute__ ((packed));
+
+typedef union {
 	struct region_register_map map;
 	unsigned long long word;
-} region_register;
+} region_register_t;
 
 struct pta_register_map {
-	unsigned ve : 1;
-	unsigned : 1;
-	unsigned size : 6;
-	unsigned vf : 1;
-	unsigned : 6;
+	unsigned int ve : 1;
+	unsigned int : 1;
+	unsigned int size : 6;
+	unsigned int vf : 1;
+	unsigned int : 6;
 	unsigned long long base : 49;
 } __attribute__ ((packed));
@@ -197,5 +197,5 @@
 	struct pta_register_map map;
 	uint64_t word;
-} pta_register;
+} pta_register_t;
 
 /** Return Translation Hashed Entry Address.
@@ -211,7 +211,11 @@
 {
 	uint64_t ret;
-
-	asm volatile ("thash %0 = %1\n" : "=r" (ret) : "r" (va));
-
+	
+	asm volatile (
+		"thash %[ret] = %[va]\n"
+		: [ret] "=r" (ret)
+		: [va] "r" (va)
+	);
+	
 	return ret;
 }
@@ -229,7 +233,11 @@
 {
 	uint64_t ret;
-
-	asm volatile ("ttag %0 = %1\n" : "=r" (ret) : "r" (va));
-
+	
+	asm volatile (
+		"ttag %[ret] = %[va]\n"
+		: [ret] "=r" (ret)
+		: [va] "r" (va)
+	);
+	
 	return ret;
 }
@@ -244,6 +252,13 @@
 {
 	uint64_t ret;
+	
 	ASSERT(i < REGION_REGISTERS);
-	asm volatile ("mov %0 = rr[%1]\n" : "=r" (ret) : "r" (i << VRN_SHIFT));
+	
+	asm volatile (
+		"mov %[ret] = rr[%[index]]\n"
+		: [ret] "=r" (ret)
+		: [index] "r" (i << VRN_SHIFT)
+	);
+	
 	return ret;
 }
@@ -257,11 +272,12 @@
 {
 	ASSERT(i < REGION_REGISTERS);
-	asm volatile (
-		"mov rr[%0] = %1\n" 
-		: 
-		: "r" (i << VRN_SHIFT), "r" (v)
-	);
-}
- 
+	
+	asm volatile (
+		"mov rr[%[index]] = %[value]\n"
+		:: [index] "r" (i << VRN_SHIFT),
+		   [value] "r" (v)
+	);
+}
+
 /** Read Page Table Register.
  *
@@ -272,5 +288,8 @@
 	uint64_t ret;
 	
-	asm volatile ("mov %0 = cr.pta\n" : "=r" (ret));
+	asm volatile (
+		"mov %[ret] = cr.pta\n"
+		: [ret] "=r" (ret)
+	);
 	
 	return ret;
@@ -283,5 +302,8 @@
 static inline void pta_write(uint64_t v)
 {
-	asm volatile ("mov cr.pta = %0\n" : : "r" (v));
+	asm volatile (
+		"mov cr.pta = %[value]\n"
+		:: [value] "r" (v)
+	);
 }
 
Index: kernel/arch/ia64/include/mm/tlb.h
===================================================================
--- kernel/arch/ia64/include/mm/tlb.h	(revision e86a849a744c5d659718b8d55becc3bbee6655ac)
+++ kernel/arch/ia64/include/mm/tlb.h	(revision 5bda2f3ec5d347e6cd33782ee9f7583f6d3aeda4)
@@ -27,5 +27,5 @@
  */
 
-/** @addtogroup ia64mm	
+/** @addtogroup ia64mm
  * @{
  */
@@ -42,34 +42,33 @@
 
 /** Data and instruction Translation Register indices. */
-#define DTR_KERNEL	0
-#define ITR_KERNEL	0
-#define DTR_KSTACK1	4
-#define DTR_KSTACK2	5
+#define DTR_KERNEL   0
+#define ITR_KERNEL   0
+#define DTR_KSTACK1  4
+#define DTR_KSTACK2  5
 
 /** Portion of TLB insertion format data structure. */
-union tlb_entry {
+typedef union {
 	uint64_t word[2];
 	struct {
 		/* Word 0 */
-		unsigned p : 1;			/**< Present. */
-		unsigned : 1;
-		unsigned ma : 3;		/**< Memory attribute. */
-		unsigned a : 1;			/**< Accessed. */
-		unsigned d : 1;			/**< Dirty. */
-		unsigned pl : 2;		/**< Privilege level. */
-		unsigned ar : 3;		/**< Access rights. */
-		unsigned long long ppn : 38;	/**< Physical Page Number, a.k.a. PFN. */
-		unsigned : 2;
-		unsigned ed : 1;
-		unsigned ig1 : 11;
-
+		unsigned int p : 1;           /**< Present. */
+		unsigned int : 1;
+		unsigned int ma : 3;          /**< Memory attribute. */
+		unsigned int a : 1;           /**< Accessed. */
+		unsigned int d : 1;           /**< Dirty. */
+		unsigned int pl : 2;          /**< Privilege level. */
+		unsigned int ar : 3;          /**< Access rights. */
+		unsigned long long ppn : 38;  /**< Physical Page Number, a.k.a. PFN. */
+		unsigned int : 2;
+		unsigned int ed : 1;
+		unsigned int ig1 : 11;
+		
 		/* Word 1 */
-		unsigned : 2;
-		unsigned ps : 6;		/**< Page size will be 2^ps. */
-		unsigned key : 24;		/**< Protection key, unused. */
-		unsigned : 32;
+		unsigned int : 2;
+		unsigned int ps : 6;    /**< Page size will be 2^ps. */
+		unsigned int key : 24;  /**< Protection key, unused. */
+		unsigned int : 32;
 	} __attribute__ ((packed));
-} __attribute__ ((packed));
-typedef union tlb_entry tlb_entry_t;
+} __attribute__ ((packed)) tlb_entry_t;
 
 extern void tc_mapping_insert(uintptr_t va, asid_t asid, tlb_entry_t entry, bool dtc);
Index: kernel/arch/ia64/include/register.h
===================================================================
--- kernel/arch/ia64/include/register.h	(revision e86a849a744c5d659718b8d55becc3bbee6655ac)
+++ kernel/arch/ia64/include/register.h	(revision 5bda2f3ec5d347e6cd33782ee9f7583f6d3aeda4)
@@ -27,5 +27,5 @@
  */
 
-/** @addtogroup ia64	
+/** @addtogroup ia64
  * @{
  */
@@ -36,98 +36,107 @@
 #define KERN_ia64_REGISTER_H_
 
-#define CR_IVR_MASK	0xf
-#define PSR_IC_MASK	0x2000
-#define PSR_I_MASK	0x4000
-#define PSR_PK_MASK	0x8000
-
-#define PSR_DT_MASK	(1 << 17)
-#define PSR_RT_MASK	(1 << 27)
-
-#define PSR_DFL_MASK	(1 << 18)
-#define PSR_DFH_MASK	(1 << 19)
-
-#define PSR_IT_MASK	0x0000001000000000
-
-#define PSR_CPL_SHIFT		32
-#define PSR_CPL_MASK_SHIFTED	3
-
-#define PFM_MASK        (~0x3fffffffff)
-
-#define RSC_MODE_MASK	3
-#define RSC_PL_MASK	12
+#define DCR_PP_MASK  (1 << 0)
+#define DCR_BE_MASK  (1 << 1)
+#define DCR_LC_MASK  (1 << 2)
+#define DCR_DM_MASK  (1 << 8)
+#define DCR_DP_MASK  (1 << 9)
+#define DCR_DK_MASK  (1 << 10)
+#define DCR_DX_MASK  (1 << 11)
+#define DCR_DR_MASK  (1 << 12)
+#define DCR_DA_MASK  (1 << 13)
+#define DCR_DD_MASK  (1 << 14)
+
+#define CR_IVR_MASK  0x0f
+
+#define PSR_IC_MASK   (1 << 13)
+#define PSR_I_MASK    (1 << 14)
+#define PSR_PK_MASK   (1 << 15)
+#define PSR_DT_MASK   (1 << 17)
+#define PSR_DFL_MASK  (1 << 18)
+#define PSR_DFH_MASK  (1 << 19)
+#define PSR_RT_MASK   (1 << 27)
+#define PSR_IT_MASK   (1 << 36)
+
+#define PSR_CPL_SHIFT         32
+#define PSR_CPL_MASK_SHIFTED  3
+
+#define PFM_MASK  (~0x3fffffffff)
+
+#define RSC_MODE_MASK   3
+#define RSC_PL_MASK     12
 
 /** Application registers. */
-#define AR_KR0		0
-#define AR_KR1		1
-#define AR_KR2		2
-#define AR_KR3		3
-#define AR_KR4		4
-#define AR_KR5		5
-#define AR_KR6		6
-#define AR_KR7		7
-/* AR 8-15 reserved */
-#define AR_RSC		16
-#define AR_BSP		17
-#define AR_BSPSTORE	18
-#define AR_RNAT		19
-/* AR 20 reserved */
-#define AR_FCR		21
-/* AR 22-23 reserved */
-#define AR_EFLAG	24
-#define AR_CSD		25
-#define AR_SSD		26
-#define AR_CFLG		27
-#define AR_FSR		28
-#define AR_FIR		29
-#define AR_FDR		30
-/* AR 31 reserved */
-#define AR_CCV		32
-/* AR 33-35 reserved */
-#define AR_UNAT		36
-/* AR 37-39 reserved */
-#define AR_FPSR		40
-/* AR 41-43 reserved */
-#define AR_ITC		44
-/* AR 45-47 reserved */
-/* AR 48-63 ignored */
-#define AR_PFS		64
-#define AR_LC		65
-#define AR_EC		66
-/* AR 67-111 reserved */
-/* AR 112-127 ignored */
+#define AR_KR0       0
+#define AR_KR1       1
+#define AR_KR2       2
+#define AR_KR3       3
+#define AR_KR4       4
+#define AR_KR5       5
+#define AR_KR6       6
+#define AR_KR7       7
+/* ARs 8-15 are reserved */
+#define AR_RSC       16
+#define AR_BSP       17
+#define AR_BSPSTORE  18
+#define AR_RNAT      19
+/* AR 20 is reserved */
+#define AR_FCR       21
+/* ARs 22-23 are reserved */
+#define AR_EFLAG     24
+#define AR_CSD       25
+#define AR_SSD       26
+#define AR_CFLG      27
+#define AR_FSR       28
+#define AR_FIR       29
+#define AR_FDR       30
+/* AR 31 is reserved */
+#define AR_CCV       32
+/* ARs 33-35 are reserved */
+#define AR_UNAT      36
+/* ARs 37-39 are reserved */
+#define AR_FPSR      40
+/* ARs 41-43 are reserved */
+#define AR_ITC       44
+/* ARs 45-47 are reserved */
+/* ARs 48-63 are ignored */
+#define AR_PFS       64
+#define AR_LC        65
+#define AR_EC        66
+/* ARs 67-111 are reserved */
+/* ARs 112-127 are ignored */
 
 /** Control registers. */
-#define CR_DCR		0
-#define CR_ITM		1
-#define CR_IVA		2
-/* CR3-CR7 reserved */
-#define CR_PTA		8
-/* CR9-CR15 reserved */
-#define CR_IPSR		16
-#define CR_ISR		17
-/* CR18 reserved */
-#define CR_IIP		19
-#define CR_IFA		20
-#define CR_ITIR		21
-#define CR_IIPA		22
-#define CR_IFS		23
-#define CR_IIM		24
-#define CR_IHA		25
-/* CR26-CR63 reserved */
-#define CR_LID		64
-#define CR_IVR		65
-#define CR_TPR		66
-#define CR_EOI		67
-#define CR_IRR0		68
-#define CR_IRR1		69
-#define CR_IRR2		70
-#define CR_IRR3		71
-#define CR_ITV		72
-#define CR_PMV		73
-#define CR_CMCV		74
-/* CR75-CR79 reserved */
-#define CR_LRR0		80
-#define CR_LRR1		81
-/* CR82-CR127 reserved */
+#define CR_DCR   0
+#define CR_ITM   1
+#define CR_IVA   2
+/* CR3-CR7 are reserved */
+#define CR_PTA   8
+/* CR9-CR15 are reserved */
+#define CR_IPSR  16
+#define CR_ISR   17
+/* CR18 is reserved */
+#define CR_IIP   19
+#define CR_IFA   20
+#define CR_ITIR  21
+#define CR_IIPA  22
+#define CR_IFS   23
+#define CR_IIM   24
+#define CR_IHA   25
+/* CR26-CR63 are reserved */
+#define CR_LID   64
+#define CR_IVR   65
+#define CR_TPR   66
+#define CR_EOI   67
+#define CR_IRR0  68
+#define CR_IRR1  69
+#define CR_IRR2  70
+#define CR_IRR3  71
+#define CR_ITV   72
+#define CR_PMV   73
+#define CR_CMCV  74
+/* CR75-CR79 are reserved */
+#define CR_LRR0  80
+#define CR_LRR1  81
+/* CR82-CR127 are reserved */
 
 #ifndef __ASM__
@@ -136,127 +145,118 @@
 
 /** Processor Status Register. */
-union psr {
-	uint64_t value;
-	struct {
-		unsigned : 1;
-		unsigned be : 1;	/**< Big-Endian data accesses. */
-		unsigned up : 1;	/**< User Performance monitor enable. */
-		unsigned ac : 1;	/**< Alignment Check. */
-		unsigned mfl : 1;	/**< Lower floating-point register written. */
-		unsigned mfh : 1;	/**< Upper floating-point register written. */
-		unsigned : 7;
-		unsigned ic : 1;	/**< Interruption Collection. */
-		unsigned i : 1;		/**< Interrupt Bit. */
-		unsigned pk : 1;	/**< Protection Key enable. */
-		unsigned : 1;
-		unsigned dt : 1;	/**< Data address Translation. */
-		unsigned dfl : 1;	/**< Disabled Floating-point Low register set. */
-		unsigned dfh : 1;	/**< Disabled Floating-point High register set. */
-		unsigned sp : 1;	/**< Secure Performance monitors. */
-		unsigned pp : 1;	/**< Privileged Performance monitor enable. */
-		unsigned di : 1;	/**< Disable Instruction set transition. */
-		unsigned si : 1;	/**< Secure Interval timer. */
-		unsigned db : 1;	/**< Debug Breakpoint fault. */
-		unsigned lp : 1;	/**< Lower Privilege transfer trap. */
-		unsigned tb : 1;	/**< Taken Branch trap. */
-		unsigned rt : 1;	/**< Register Stack Translation. */
-		unsigned : 4;
-		unsigned cpl : 2;	/**< Current Privilege Level. */
-		unsigned is : 1;	/**< Instruction Set. */
-		unsigned mc : 1;	/**< Machine Check abort mask. */
-		unsigned it : 1;	/**< Instruction address Translation. */
-		unsigned id : 1;	/**< Instruction Debug fault disable. */
-		unsigned da : 1;	/**< Disable Data Access and Dirty-bit faults. */
-		unsigned dd : 1;	/**< Data Debug fault disable. */
-		unsigned ss : 1;	/**< Single Step enable. */
-		unsigned ri : 2;	/**< Restart Instruction. */
-		unsigned ed : 1;	/**< Exception Deferral. */
-		unsigned bn : 1;	/**< Register Bank. */
-		unsigned ia : 1;	/**< Disable Instruction Access-bit faults. */
-	} __attribute__ ((packed));
-};
-typedef union psr psr_t;
+typedef union {
+	uint64_t value;
+	struct {
+		unsigned int : 1;
+		unsigned int be : 1;   /**< Big-Endian data accesses. */
+		unsigned int up : 1;   /**< User Performance monitor enable. */
+		unsigned int ac : 1;   /**< Alignment Check. */
+		unsigned int mfl : 1;  /**< Lower floating-point register written. */
+		unsigned int mfh : 1;  /**< Upper floating-point register written. */
+		unsigned int : 7;
+		unsigned int ic : 1;   /**< Interruption Collection. */
+		unsigned int i : 1;    /**< Interrupt Bit. */
+		unsigned int pk : 1;   /**< Protection Key enable. */
+		unsigned int : 1;
+		unsigned int dt : 1;   /**< Data address Translation. */
+		unsigned int dfl : 1;  /**< Disabled Floating-point Low register set. */
+		unsigned int dfh : 1;  /**< Disabled Floating-point High register set. */
+		unsigned int sp : 1;   /**< Secure Performance monitors. */
+		unsigned int pp : 1;   /**< Privileged Performance monitor enable. */
+		unsigned int di : 1;   /**< Disable Instruction set transition. */
+		unsigned int si : 1;   /**< Secure Interval timer. */
+		unsigned int db : 1;   /**< Debug Breakpoint fault. */
+		unsigned int lp : 1;   /**< Lower Privilege transfer trap. */
+		unsigned int tb : 1;   /**< Taken Branch trap. */
+		unsigned int rt : 1;   /**< Register Stack Translation. */
+		unsigned int : 4;
+		unsigned int cpl : 2;  /**< Current Privilege Level. */
+		unsigned int is : 1;   /**< Instruction Set. */
+		unsigned int mc : 1;   /**< Machine Check abort mask. */
+		unsigned int it : 1;   /**< Instruction address Translation. */
+		unsigned int id : 1;   /**< Instruction Debug fault disable. */
+		unsigned int da : 1;   /**< Disable Data Access and Dirty-bit faults. */
+		unsigned int dd : 1;   /**< Data Debug fault disable. */
+		unsigned int ss : 1;   /**< Single Step enable. */
+		unsigned int ri : 2;   /**< Restart Instruction. */
+		unsigned int ed : 1;   /**< Exception Deferral. */
+		unsigned int bn : 1;   /**< Register Bank. */
+		unsigned int ia : 1;   /**< Disable Instruction Access-bit faults. */
+	} __attribute__ ((packed));
+} psr_t;
 
 /** Register Stack Configuration Register */
-union rsc {
-	uint64_t value;
-	struct {
-		unsigned mode : 2;
-		unsigned pl : 2;	/**< Privilege Level. */
-		unsigned be : 1;	/**< Big-endian. */
-		unsigned : 11;
-		unsigned loadrs : 14;
-	} __attribute__ ((packed));
-};
-typedef union rsc rsc_t;
+typedef union {
+	uint64_t value;
+	struct {
+		unsigned int mode : 2;
+		unsigned int pl : 2;    /**< Privilege Level. */
+		unsigned int be : 1;    /**< Big-endian. */
+		unsigned int : 11;
+		unsigned int loadrs : 14;
+	} __attribute__ ((packed));
+} rsc_t;
 
 /** External Interrupt Vector Register */
-union cr_ivr {
-	uint8_t  vector;
-	uint64_t value;
-};
-
-typedef union cr_ivr cr_ivr_t;
+typedef union {
+	uint8_t vector;
+	uint64_t value;
+} cr_ivr_t;
 
 /** Task Priority Register */
-union cr_tpr {
-	struct {
-		unsigned : 4;
-		unsigned mic: 4;		/**< Mask Interrupt Class. */
-		unsigned : 8;
-		unsigned mmi: 1;		/**< Mask Maskable Interrupts. */
-	} __attribute__ ((packed));
-	uint64_t value;
-};
-
-typedef union cr_tpr cr_tpr_t;
+typedef union {
+	uint64_t value;
+	struct {
+		unsigned int : 4;
+		unsigned int mic: 4;  /**< Mask Interrupt Class. */
+		unsigned int : 8;
+		unsigned int mmi: 1;  /**< Mask Maskable Interrupts. */
+	} __attribute__ ((packed));
+} cr_tpr_t;
 
 /** Interval Timer Vector */
-union cr_itv {
-	struct {
-		unsigned vector : 8;
-		unsigned : 4;
-		unsigned : 1;
-		unsigned : 3;
-		unsigned m : 1;			/**< Mask. */
-	} __attribute__ ((packed));
-	uint64_t value;
-};
-
-typedef union cr_itv cr_itv_t;
+typedef union {
+	uint64_t value;
+	struct {
+		unsigned int vector : 8;
+		unsigned int : 4;
+		unsigned int : 1;
+		unsigned int : 3;
+		unsigned int m : 1;       /**< Mask. */
+	} __attribute__ ((packed));
+} cr_itv_t;
 
 /** Interruption Status Register */
-union cr_isr {
+typedef union {
+	uint64_t value;
 	struct {
 		union {
 			/** General Exception code field structuring. */
+			uint16_t code;
 			struct {
-				unsigned ge_na : 4;
-				unsigned ge_code : 4;
+				unsigned int ge_na : 4;
+				unsigned int ge_code : 4;
 			} __attribute__ ((packed));
-			uint16_t code;
 		};
 		uint8_t vector;
-		unsigned : 8;
-		unsigned x : 1;			/**< Execute exception. */
-		unsigned w : 1;			/**< Write exception. */
-		unsigned r : 1;			/**< Read exception. */
-		unsigned na : 1;		/**< Non-access exception. */
-		unsigned sp : 1;		/**< Speculative load exception. */
-		unsigned rs : 1;		/**< Register stack. */
-		unsigned ir : 1;		/**< Incomplete Register frame. */
-		unsigned ni : 1;		/**< Nested Interruption. */
-		unsigned so : 1;		/**< IA-32 Supervisor Override. */
-		unsigned ei : 2;		/**< Excepting Instruction. */
-		unsigned ed : 1;		/**< Exception Deferral. */
-		unsigned : 20;
-	} __attribute__ ((packed));
-	uint64_t value;
-};
-
-typedef union cr_isr cr_isr_t;
+		unsigned int : 8;
+		unsigned int x : 1;   /**< Execute exception. */
+		unsigned int w : 1;   /**< Write exception. */
+		unsigned int r : 1;   /**< Read exception. */
+		unsigned int na : 1;  /**< Non-access exception. */
+		unsigned int sp : 1;  /**< Speculative load exception. */
+		unsigned int rs : 1;  /**< Register stack. */
+		unsigned int ir : 1;  /**< Incomplete Register frame. */
+		unsigned int ni : 1;  /**< Nested Interruption. */
+		unsigned int so : 1;  /**< IA-32 Supervisor Override. */
+		unsigned int ei : 2;  /**< Excepting Instruction. */
+		unsigned int ed : 1;  /**< Exception Deferral. */
+		unsigned int : 20;
+	} __attribute__ ((packed));
+} cr_isr_t;
 
 /** CPUID Register 3 */
-union cpuid3 {
+typedef union {
+	uint64_t value;
 	struct {
 		uint8_t number;
@@ -266,8 +266,5 @@
 		uint8_t archrev;
 	} __attribute__ ((packed));
-	uint64_t value;
-};
-
-typedef union cpuid3 cpuid3_t;
+} cpuid3_t;
 
 #endif /* !__ASM__ */
Index: kernel/arch/ia64/src/mm/as.c
===================================================================
--- kernel/arch/ia64/src/mm/as.c	(revision e86a849a744c5d659718b8d55becc3bbee6655ac)
+++ kernel/arch/ia64/src/mm/as.c	(revision 5bda2f3ec5d347e6cd33782ee9f7583f6d3aeda4)
@@ -55,5 +55,5 @@
 void as_install_arch(as_t *as)
 {
-	region_register rr;
+	region_register_t rr;
 	int i;
 	
Index: kernel/arch/ia64/src/mm/page.c
===================================================================
--- kernel/arch/ia64/src/mm/page.c	(revision e86a849a744c5d659718b8d55becc3bbee6655ac)
+++ kernel/arch/ia64/src/mm/page.c	(revision 5bda2f3ec5d347e6cd33782ee9f7583f6d3aeda4)
@@ -63,6 +63,6 @@
 void set_environment(void)
 {
-	region_register rr;
-	pta_register pta;
+	region_register_t rr;
+	pta_register_t pta;
 	int i;
 #ifdef CONFIG_VHPT
@@ -131,5 +131,5 @@
 vhpt_entry_t *vhpt_hash(uintptr_t page, asid_t asid)
 {
-	region_register rr_save, rr;
+	region_register_t rr_save, rr;
 	size_t vrn;
 	rid_t rid;
@@ -176,5 +176,5 @@
 bool vhpt_compare(uintptr_t page, asid_t asid, vhpt_entry_t *v)
 {
-	region_register rr_save, rr;	
+	region_register_t rr_save, rr;
 	size_t vrn;
 	rid_t rid;
@@ -223,5 +223,5 @@
     int flags)
 {
-	region_register rr_save, rr;	
+	region_register_t rr_save, rr;
 	size_t vrn;
 	rid_t rid;
@@ -257,11 +257,11 @@
 	v->present.ma = (flags & PAGE_CACHEABLE) ?
 	    MA_WRITEBACK : MA_UNCACHEABLE;
-	v->present.a = false;	/* not accessed */
-	v->present.d = false;	/* not dirty */
+	v->present.a = false;  /* not accessed */
+	v->present.d = false;  /* not dirty */
 	v->present.pl = (flags & PAGE_USER) ? PL_USER : PL_KERNEL;
 	v->present.ar = (flags & PAGE_WRITE) ? AR_WRITE : AR_READ;
 	v->present.ar |= (flags & PAGE_EXEC) ? AR_EXECUTE : 0; 
 	v->present.ppn = frame >> PPN_SHIFT;
-	v->present.ed = false;	/* exception not deffered */
+	v->present.ed = false;  /* exception not deffered */
 	v->present.ps = PAGE_WIDTH;
 	v->present.key = 0;
Index: kernel/arch/ia64/src/mm/tlb.c
===================================================================
--- kernel/arch/ia64/src/mm/tlb.c	(revision e86a849a744c5d659718b8d55becc3bbee6655ac)
+++ kernel/arch/ia64/src/mm/tlb.c	(revision 5bda2f3ec5d347e6cd33782ee9f7583f6d3aeda4)
@@ -27,5 +27,5 @@
  */
 
-/** @addtogroup ia64mm	
+/** @addtogroup ia64mm
  * @{
  */
@@ -53,4 +53,6 @@
 #include <interrupt.h>
 
+#define IO_FRAME_BASE 0xFFFFC000000
+
 /** Invalidate all TLB entries. */
 void tlb_invalidate_all(void)
@@ -59,7 +61,7 @@
 	uintptr_t adr;
 	uint32_t count1, count2, stride1, stride2;
-		
+	
 	unsigned int i, j;
-		
+	
 	adr = PAL_PTCE_INFO_BASE();
 	count1 = PAL_PTCE_INFO_COUNT1();
@@ -67,13 +69,12 @@
 	stride1 = PAL_PTCE_INFO_STRIDE1();
 	stride2 = PAL_PTCE_INFO_STRIDE2();
-		
+	
 	ipl = interrupts_disable();
-
+	
 	for (i = 0; i < count1; i++) {
 		for (j = 0; j < count2; j++) {
 			asm volatile (
-				"ptc.e %0 ;;"
-				:
-				: "r" (adr)
+				"ptc.e %[adr] ;;"
+				:: [adr] "r" (adr)
 			);
 			adr += stride2;
@@ -81,17 +82,19 @@
 		adr += stride1;
 	}
-
+	
 	interrupts_restore(ipl);
-
+	
 	srlz_d();
 	srlz_i();
+	
 #ifdef CONFIG_VHPT
 	vhpt_invalidate_all();
-#endif	
+#endif
 }
 
 /** Invalidate entries belonging to an address space.
  *
- * @param asid		Address space identifier.
+ * @param asid Address space identifier.
+ *
  */
 void tlb_invalidate_asid(asid_t asid)
@@ -103,12 +106,12 @@
 void tlb_invalidate_pages(asid_t asid, uintptr_t page, size_t cnt)
 {
-	region_register rr;
+	region_register_t rr;
 	bool restore_rr = false;
 	int b = 0;
 	int c = cnt;
-
+	
 	uintptr_t va;
 	va = page;
-
+	
 	rr.word = rr_read(VA2VRN(va));
 	if ((restore_rr = (rr.map.rid != ASID2RID(asid, VA2VRN(va))))) {
@@ -117,6 +120,6 @@
 		 * Save the old content of the register and replace the RID.
 		 */
-		region_register rr0;
-
+		region_register_t rr0;
+		
 		rr0 = rr;
 		rr0.map.rid = ASID2RID(asid, VA2VRN(va));
@@ -126,5 +129,5 @@
 	}
 	
-	while(c >>= 1)
+	while (c >>= 1)
 		b++;
 	b >>= 1;
@@ -169,6 +172,12 @@
 		break;
 	}
-	for(; va < (page + cnt * PAGE_SIZE); va += (1 << ps))
-		asm volatile ("ptc.l %0, %1;;" :: "r" (va), "r" (ps << 2));
+	
+	for (; va < (page + cnt * PAGE_SIZE); va += (1 << ps))
+		asm volatile (
+			"ptc.l %[va], %[ps] ;;"
+			:: [va]"r" (va),
+			   [ps] "r" (ps << 2)
+		);
+	
 	srlz_d();
 	srlz_i();
@@ -183,8 +192,9 @@
 /** Insert data into data translation cache.
  *
- * @param va		Virtual page address.
- * @param asid		Address space identifier.
- * @param entry		The rest of TLB entry as required by TLB insertion
- * 			format.
+ * @param va    Virtual page address.
+ * @param asid  Address space identifier.
+ * @param entry The rest of TLB entry as required by TLB insertion
+ *              format.
+ *
  */
 void dtc_mapping_insert(uintptr_t va, asid_t asid, tlb_entry_t entry)
@@ -195,8 +205,8 @@
 /** Insert data into instruction translation cache.
  *
- * @param va		Virtual page address.
- * @param asid		Address space identifier.
- * @param entry		The rest of TLB entry as required by TLB insertion
- * 			format.
+ * @param va    Virtual page address.
+ * @param asid  Address space identifier.
+ * @param entry The rest of TLB entry as required by TLB insertion
+ *              format.
  */
 void itc_mapping_insert(uintptr_t va, asid_t asid, tlb_entry_t entry)
@@ -207,16 +217,17 @@
 /** Insert data into instruction or data translation cache.
  *
- * @param va		Virtual page address.
- * @param asid		Address space identifier.
- * @param entry		The rest of TLB entry as required by TLB insertion
- * 			format.
- * @param dtc		If true, insert into data translation cache, use
- * 			instruction translation cache otherwise.
+ * @param va    Virtual page address.
+ * @param asid  Address space identifier.
+ * @param entry The rest of TLB entry as required by TLB insertion
+ *              format.
+ * @param dtc   If true, insert into data translation cache, use
+ *              instruction translation cache otherwise.
+ *
  */
 void tc_mapping_insert(uintptr_t va, asid_t asid, tlb_entry_t entry, bool dtc)
 {
-	region_register rr;
+	region_register_t rr;
 	bool restore_rr = false;
-
+	
 	rr.word = rr_read(VA2VRN(va));
 	if ((restore_rr = (rr.map.rid != ASID2RID(asid, VA2VRN(va))))) {
@@ -225,6 +236,6 @@
 		 * Save the old content of the register and replace the RID.
 		 */
-		region_register rr0;
-
+		region_register_t rr0;
+		
 		rr0 = rr;
 		rr0.map.rid = ASID2RID(asid, VA2VRN(va));
@@ -235,18 +246,20 @@
 	
 	asm volatile (
-		"mov r8 = psr;;\n"
-		"rsm %0;;\n"   			/* PSR_IC_MASK */
-		"srlz.d;;\n"
-		"srlz.i;;\n"
-		"mov cr.ifa = %1\n"		/* va */
-		"mov cr.itir = %2;;\n"		/* entry.word[1] */
-		"cmp.eq p6,p7 = %4,r0;;\n"	/* decide between itc and dtc */
-		"(p6) itc.i %3;;\n"
-		"(p7) itc.d %3;;\n"
-		"mov psr.l = r8;;\n"
-		"srlz.d;;\n"
-		:
-		: "i" (PSR_IC_MASK), "r" (va), "r" (entry.word[1]),
-		    "r" (entry.word[0]), "r" (dtc)
+		"mov r8 = psr ;;\n"
+		"rsm %[mask] ;;\n"                 /* PSR_IC_MASK */
+		"srlz.d ;;\n"
+		"srlz.i ;;\n"
+		"mov cr.ifa = %[va]\n"             /* va */
+		"mov cr.itir = %[word1] ;;\n"      /* entry.word[1] */
+		"cmp.eq p6, p7 = %[dtc], r0 ;;\n"  /* decide between itc and dtc */
+		"(p6) itc.i %[word0] ;;\n"
+		"(p7) itc.d %[word0] ;;\n"
+		"mov psr.l = r8 ;;\n"
+		"srlz.d ;;\n"
+		:: [mask] "i" (PSR_IC_MASK),
+		   [va] "r" (va),
+		   [word0] "r" (entry.word[0]),
+		   [word1] "r" (entry.word[1]),
+		   [dtc] "r" (dtc)
 		: "p6", "p7", "r8"
 	);
@@ -261,12 +274,12 @@
 /** Insert data into instruction translation register.
  *
- * @param va		Virtual page address.
- * @param asid		Address space identifier.
- * @param entry		The rest of TLB entry as required by TLB insertion
- * 			format.
- * @param tr		Translation register.
- */
-void
-itr_mapping_insert(uintptr_t va, asid_t asid, tlb_entry_t entry, size_t tr)
+ * @param va    Virtual page address.
+ * @param asid  Address space identifier.
+ * @param entry The rest of TLB entry as required by TLB insertion
+ *              format.
+ * @param tr    Translation register.
+ *
+ */
+void itr_mapping_insert(uintptr_t va, asid_t asid, tlb_entry_t entry, size_t tr)
 {
 	tr_mapping_insert(va, asid, entry, false, tr);
@@ -275,12 +288,12 @@
 /** Insert data into data translation register.
  *
- * @param va		Virtual page address.
- * @param asid		Address space identifier.
- * @param entry		The rest of TLB entry as required by TLB insertion
- * 			format.
- * @param tr		Translation register.
- */
-void
-dtr_mapping_insert(uintptr_t va, asid_t asid, tlb_entry_t entry, size_t tr)
+ * @param va    Virtual page address.
+ * @param asid  Address space identifier.
+ * @param entry The rest of TLB entry as required by TLB insertion
+ *              format.
+ * @param tr    Translation register.
+ *
+ */
+void dtr_mapping_insert(uintptr_t va, asid_t asid, tlb_entry_t entry, size_t tr)
 {
 	tr_mapping_insert(va, asid, entry, true, tr);
@@ -289,19 +302,19 @@
 /** Insert data into instruction or data translation register.
  *
- * @param va		Virtual page address.
- * @param asid		Address space identifier.
- * @param entry		The rest of TLB entry as required by TLB insertion
- * 			format.
- * @param dtr		If true, insert into data translation register, use
- * 			instruction translation register otherwise.
- * @param tr		Translation register.
- */
-void
-tr_mapping_insert(uintptr_t va, asid_t asid, tlb_entry_t entry, bool dtr,
+ * @param va    Virtual page address.
+ * @param asid  Address space identifier.
+ * @param entry The rest of TLB entry as required by TLB insertion
+ *              format.
+ * @param dtr   If true, insert into data translation register, use
+ *              instruction translation register otherwise.
+ * @param tr    Translation register.
+ *
+ */
+void tr_mapping_insert(uintptr_t va, asid_t asid, tlb_entry_t entry, bool dtr,
     size_t tr)
 {
-	region_register rr;
+	region_register_t rr;
 	bool restore_rr = false;
-
+	
 	rr.word = rr_read(VA2VRN(va));
 	if ((restore_rr = (rr.map.rid != ASID2RID(asid, VA2VRN(va))))) {
@@ -310,6 +323,6 @@
 		 * Save the old content of the register and replace the RID.
 		 */
-		region_register rr0;
-
+		region_register_t rr0;
+		
 		rr0 = rr;
 		rr0.map.rid = ASID2RID(asid, VA2VRN(va));
@@ -318,20 +331,23 @@
 		srlz_i();
 	}
-
+	
 	asm volatile (
-		"mov r8 = psr;;\n"
-		"rsm %0;;\n"			/* PSR_IC_MASK */
-		"srlz.d;;\n"
-		"srlz.i;;\n"
-		"mov cr.ifa = %1\n"        	/* va */		 
-		"mov cr.itir = %2;;\n"		/* entry.word[1] */ 
-		"cmp.eq p6,p7 = %5,r0;;\n"	/* decide between itr and dtr */
-		"(p6) itr.i itr[%4] = %3;;\n"
-		"(p7) itr.d dtr[%4] = %3;;\n"
-		"mov psr.l = r8;;\n"
-		"srlz.d;;\n"
-		:
-		: "i" (PSR_IC_MASK), "r" (va), "r" (entry.word[1]),
-		    "r" (entry.word[0]), "r" (tr), "r" (dtr)
+		"mov r8 = psr ;;\n"
+		"rsm %[mask] ;;\n"                       /* PSR_IC_MASK */
+		"srlz.d ;;\n"
+		"srlz.i ;;\n"
+		"mov cr.ifa = %[va]\n"                   /* va */
+		"mov cr.itir = %[word1] ;;\n"            /* entry.word[1] */
+		"cmp.eq p6, p7 = %[dtr], r0 ;;\n"        /* decide between itr and dtr */
+		"(p6) itr.i itr[%[tr]] = %[word0] ;;\n"
+		"(p7) itr.d dtr[%[tr]] = %[word0] ;;\n"
+		"mov psr.l = r8 ;;\n"
+		"srlz.d ;;\n"
+		:: [mask] "i" (PSR_IC_MASK),
+		   [va] "r" (va),
+		   [word1] "r" (entry.word[1]),
+		   [word0] "r" (entry.word[0]),
+		   [tr] "r" (tr),
+		   [dtr] "r" (dtr)
 		: "p6", "p7", "r8"
 	);
@@ -346,12 +362,12 @@
 /** Insert data into DTLB.
  *
- * @param page		Virtual page address including VRN bits.
- * @param frame		Physical frame address.
- * @param dtr		If true, insert into data translation register, use data
- * 			translation cache otherwise.
- * @param tr		Translation register if dtr is true, ignored otherwise.
- */
-void
-dtlb_kernel_mapping_insert(uintptr_t page, uintptr_t frame, bool dtr,
+ * @param page  Virtual page address including VRN bits.
+ * @param frame Physical frame address.
+ * @param dtr   If true, insert into data translation register, use data
+ *              translation cache otherwise.
+ * @param tr    Translation register if dtr is true, ignored otherwise.
+ *
+ */
+void dtlb_kernel_mapping_insert(uintptr_t page, uintptr_t frame, bool dtr,
     size_t tr)
 {
@@ -361,8 +377,8 @@
 	entry.word[1] = 0;
 	
-	entry.p = true;			/* present */
+	entry.p = true;           /* present */
 	entry.ma = MA_WRITEBACK;
-	entry.a = true;			/* already accessed */
-	entry.d = true;			/* already dirty */
+	entry.a = true;           /* already accessed */
+	entry.d = true;           /* already dirty */
 	entry.pl = PL_KERNEL;
 	entry.ar = AR_READ | AR_WRITE;
@@ -380,10 +396,15 @@
  * Purge DTR entries used by the kernel.
  *
- * @param page		Virtual page address including VRN bits.
- * @param width		Width of the purge in bits.
+ * @param page  Virtual page address including VRN bits.
+ * @param width Width of the purge in bits.
+ *
  */
 void dtr_purge(uintptr_t page, size_t width)
 {
-	asm volatile ("ptr.d %0, %1\n" : : "r" (page), "r" (width << 2));
+	asm volatile (
+		"ptr.d %[page], %[width]\n"
+		:: [page] "r" (page),
+		   [width] "r" (width << 2)
+	);
 }
 
@@ -391,10 +412,11 @@
 /** Copy content of PTE into data translation cache.
  *
- * @param t		PTE.
+ * @param t PTE.
+ *
  */
 void dtc_pte_copy(pte_t *t)
 {
 	tlb_entry_t entry;
-
+	
 	entry.word[0] = 0;
 	entry.word[1] = 0;
@@ -410,17 +432,19 @@
 	
 	dtc_mapping_insert(t->page, t->as->asid, entry);
+	
 #ifdef CONFIG_VHPT
 	vhpt_mapping_insert(t->page, t->as->asid, entry);
-#endif	
+#endif
 }
 
 /** Copy content of PTE into instruction translation cache.
  *
- * @param t		PTE.
+ * @param t PTE.
+ *
  */
 void itc_pte_copy(pte_t *t)
 {
 	tlb_entry_t entry;
-
+	
 	entry.word[0] = 0;
 	entry.word[1] = 0;
@@ -437,25 +461,27 @@
 	
 	itc_mapping_insert(t->page, t->as->asid, entry);
+	
 #ifdef CONFIG_VHPT
 	vhpt_mapping_insert(t->page, t->as->asid, entry);
-#endif	
+#endif
 }
 
 /** Instruction TLB fault handler for faults with VHPT turned off.
  *
- * @param vector		Interruption vector.
- * @param istate		Structure with saved interruption state.
+ * @param vector Interruption vector.
+ * @param istate Structure with saved interruption state.
+ *
  */
 void alternate_instruction_tlb_fault(uint64_t vector, istate_t *istate)
 {
-	region_register rr;
+	region_register_t rr;
 	rid_t rid;
 	uintptr_t va;
 	pte_t *t;
 	
-	va = istate->cr_ifa;	/* faulting address */
+	va = istate->cr_ifa; /* faulting address */
 	rr.word = rr_read(VA2VRN(va));
 	rid = rr.map.rid;
-
+	
 	page_table_lock(AS, true);
 	t = page_mapping_find(AS, va);
@@ -473,5 +499,5 @@
 		page_table_unlock(AS, true);
 		if (as_page_fault(va, PF_ACCESS_EXEC, istate) == AS_PF_FAULT) {
-			fault_if_from_uspace(istate,"Page fault at %p.",va);
+			fault_if_from_uspace(istate, "Page fault at %p.", va);
 			panic("%s: va=%p, rid=%d, iip=%p.", __func__, va, rid,
 			    istate->cr_iip);
@@ -488,14 +514,13 @@
 }
 
-#define IO_FRAME_BASE 0xFFFFC000000
-
 /**
  * There is special handling of memory mapped legacy io, because of 4KB sized
  * access for userspace.
  *
- * @param va		Virtual address of page fault.
- * @param istate	Structure with saved interruption state.
- *
- * @return		One on success, zero on failure.
+ * @param va     Virtual address of page fault.
+ * @param istate Structure with saved interruption state.
+ *
+ * @return One on success, zero on failure.
+ *
  */
 static int try_memmap_io_insertion(uintptr_t va, istate_t *istate)
@@ -505,27 +530,27 @@
 			uint64_t io_page = (va & ((1 << IO_PAGE_WIDTH) - 1)) >>
 			    USPACE_IO_PAGE_WIDTH;
-
+			
 			if (is_io_page_accessible(io_page)) {
 				uint64_t page, frame;
-
+				
 				page = IO_OFFSET +
 				    (1 << USPACE_IO_PAGE_WIDTH) * io_page;
 				frame = IO_FRAME_BASE +
 				    (1 << USPACE_IO_PAGE_WIDTH) * io_page;
-
+				
 				tlb_entry_t entry;
-	
+				
 				entry.word[0] = 0;
 				entry.word[1] = 0;
-	
-				entry.p = true;		/* present */
-				entry.ma = MA_UNCACHEABLE;		
-				entry.a = true;		/* already accessed */
-				entry.d = true;		/* already dirty */
+				
+				entry.p = true;             /* present */
+				entry.ma = MA_UNCACHEABLE;
+				entry.a = true;             /* already accessed */
+				entry.d = true;             /* already dirty */
 				entry.pl = PL_USER;
 				entry.ar = AR_READ | AR_WRITE;
 				entry.ppn = frame >> PPN_SHIFT;
 				entry.ps = USPACE_IO_PAGE_WIDTH;
-	
+				
 				dtc_mapping_insert(page, TASK->as->asid, entry);
 				return 1;
@@ -536,5 +561,5 @@
 		}
 	}
-		
+	
 	return 0;
 }
@@ -542,17 +567,15 @@
 /** Data TLB fault handler for faults with VHPT turned off.
  *
- * @param vector	Interruption vector.
- * @param istate	Structure with saved interruption state.
+ * @param vector Interruption vector.
+ * @param istate Structure with saved interruption state.
+ *
  */
 void alternate_data_tlb_fault(uint64_t vector, istate_t *istate)
 {
-	region_register rr;
-	rid_t rid;
-	uintptr_t va;
-	pte_t *t;
-	
-	va = istate->cr_ifa;	/* faulting address */
-	rr.word = rr_read(VA2VRN(va));
-	rid = rr.map.rid;
+	uintptr_t va = istate->cr_ifa;  /* faulting address */
+	
+	region_register_t rr;
+	rr.word = rr_read(VA2VRN(va));
+	rid_t rid = rr.map.rid;
 	if (RID2ASID(rid) == ASID_KERNEL) {
 		if (VA2VRN(va) == VRN_KERNEL) {
@@ -565,13 +588,14 @@
 		}
 	}
-
+	
+	
 	page_table_lock(AS, true);
-	t = page_mapping_find(AS, va);
-	if (t) {
+	pte_t *entry = page_mapping_find(AS, va);
+	if (entry) {
 		/*
 		 * The mapping was found in the software page hash table.
 		 * Insert it into data translation cache.
 		 */
-		dtc_pte_copy(t);
+		dtc_pte_copy(entry);
 		page_table_unlock(AS, true);
 	} else {
@@ -579,10 +603,11 @@
 		if (try_memmap_io_insertion(va, istate))
 			return;
-		/*
-		 * Forward the page fault to the address space page fault 
+		
+		/*
+		 * Forward the page fault to the address space page fault
 		 * handler.
 		 */
 		if (as_page_fault(va, PF_ACCESS_READ, istate) == AS_PF_FAULT) {
-			fault_if_from_uspace(istate,"Page fault at %p.",va);
+			fault_if_from_uspace(istate, "Page fault at %p.", va);
 			panic("%s: va=%p, rid=%d, iip=%p.", __func__, va, rid,
 			    istate->cr_iip);
@@ -595,32 +620,34 @@
  * This fault should not occur.
  *
- * @param vector	Interruption vector.
- * @param istate	Structure with saved interruption state.
+ * @param vector Interruption vector.
+ * @param istate Structure with saved interruption state.
+ *
  */
 void data_nested_tlb_fault(uint64_t vector, istate_t *istate)
 {
-	panic("%s.", __func__);
+	ASSERT(false);
 }
 
 /** Data Dirty bit fault handler.
  *
- * @param vector	Interruption vector.
- * @param istate	Structure with saved interruption state.
+ * @param vector Interruption vector.
+ * @param istate Structure with saved interruption state.
+ *
  */
 void data_dirty_bit_fault(uint64_t vector, istate_t *istate)
 {
-	region_register rr;
+	region_register_t rr;
 	rid_t rid;
 	uintptr_t va;
 	pte_t *t;
 	
-	va = istate->cr_ifa;	/* faulting address */
+	va = istate->cr_ifa;  /* faulting address */
 	rr.word = rr_read(VA2VRN(va));
 	rid = rr.map.rid;
-
+	
 	page_table_lock(AS, true);
 	t = page_mapping_find(AS, va);
-	ASSERT(t && t->p);
-	if (t && t->p && t->w) {
+	ASSERT((t) && (t->p));
+	if ((t) && (t->p) && (t->w)) {
 		/*
 		 * Update the Dirty bit in page tables and reinsert
@@ -631,5 +658,5 @@
 	} else {
 		if (as_page_fault(va, PF_ACCESS_WRITE, istate) == AS_PF_FAULT) {
-			fault_if_from_uspace(istate,"Page fault at %p.",va);
+			fault_if_from_uspace(istate, "Page fault at %p.", va);
 			panic("%s: va=%p, rid=%d, iip=%p.", __func__, va, rid,
 			    istate->cr_iip);
@@ -641,22 +668,23 @@
 /** Instruction access bit fault handler.
  *
- * @param vector	Interruption vector.
- * @param istate	Structure with saved interruption state.
+ * @param vector Interruption vector.
+ * @param istate Structure with saved interruption state.
+ *
  */
 void instruction_access_bit_fault(uint64_t vector, istate_t *istate)
 {
-	region_register rr;
+	region_register_t rr;
 	rid_t rid;
 	uintptr_t va;
-	pte_t *t;	
-
-	va = istate->cr_ifa;	/* faulting address */
+	pte_t *t;
+	
+	va = istate->cr_ifa;  /* faulting address */
 	rr.word = rr_read(VA2VRN(va));
 	rid = rr.map.rid;
-
+	
 	page_table_lock(AS, true);
 	t = page_mapping_find(AS, va);
-	ASSERT(t && t->p);
-	if (t && t->p && t->x) {
+	ASSERT((t) && (t->p));
+	if ((t) && (t->p) && (t->x)) {
 		/*
 		 * Update the Accessed bit in page tables and reinsert
@@ -679,20 +707,21 @@
  * @param vector Interruption vector.
  * @param istate Structure with saved interruption state.
+ *
  */
 void data_access_bit_fault(uint64_t vector, istate_t *istate)
 {
-	region_register rr;
+	region_register_t rr;
 	rid_t rid;
 	uintptr_t va;
 	pte_t *t;
-
-	va = istate->cr_ifa;	/* faulting address */
+	
+	va = istate->cr_ifa;  /* faulting address */
 	rr.word = rr_read(VA2VRN(va));
 	rid = rr.map.rid;
-
+	
 	page_table_lock(AS, true);
 	t = page_mapping_find(AS, va);
-	ASSERT(t && t->p);
-	if (t && t->p) {
+	ASSERT((t) && (t->p));
+	if ((t) && (t->p)) {
 		/*
 		 * Update the Accessed bit in page tables and reinsert
@@ -715,16 +744,17 @@
  * @param vector Interruption vector.
  * @param istate Structure with saved interruption state.
+ *
  */
 void data_access_rights_fault(uint64_t vector, istate_t *istate)
 {
-	region_register rr;
+	region_register_t rr;
 	rid_t rid;
 	uintptr_t va;
 	pte_t *t;
-
-	va = istate->cr_ifa;	/* faulting address */
+	
+	va = istate->cr_ifa;  /* faulting address */
 	rr.word = rr_read(VA2VRN(va));
 	rid = rr.map.rid;
-
+	
 	/*
 	 * Assume a write to a read-only page.
@@ -732,5 +762,5 @@
 	page_table_lock(AS, true);
 	t = page_mapping_find(AS, va);
-	ASSERT(t && t->p);
+	ASSERT((t) && (t->p));
 	ASSERT(!t->w);
 	if (as_page_fault(va, PF_ACCESS_WRITE, istate) == AS_PF_FAULT) {
@@ -746,16 +776,17 @@
  * @param vector Interruption vector.
  * @param istate Structure with saved interruption state.
+ *
  */
 void page_not_present(uint64_t vector, istate_t *istate)
 {
-	region_register rr;
+	region_register_t rr;
 	rid_t rid;
 	uintptr_t va;
 	pte_t *t;
 	
-	va = istate->cr_ifa;	/* faulting address */
+	va = istate->cr_ifa;  /* faulting address */
 	rr.word = rr_read(VA2VRN(va));
 	rid = rr.map.rid;
-
+	
 	page_table_lock(AS, true);
 	t = page_mapping_find(AS, va);
Index: kernel/arch/ia64/src/mm/vhpt.c
===================================================================
--- kernel/arch/ia64/src/mm/vhpt.c	(revision e86a849a744c5d659718b8d55becc3bbee6655ac)
+++ kernel/arch/ia64/src/mm/vhpt.c	(revision 5bda2f3ec5d347e6cd33782ee9f7583f6d3aeda4)
@@ -27,5 +27,5 @@
  */
 
-/** @addtogroup ia64mm	
+/** @addtogroup ia64mm
  * @{
  */
@@ -44,5 +44,5 @@
 	vhpt_base = frame_alloc(VHPT_WIDTH - FRAME_WIDTH,
 	    FRAME_KA | FRAME_ATOMIC);
-	if (!vhpt_base) 
+	if (!vhpt_base)
 		panic("Kernel configured with VHPT but no memory for table.");
 	vhpt_invalidate_all();
@@ -53,15 +53,14 @@
 void vhpt_mapping_insert(uintptr_t va, asid_t asid, tlb_entry_t entry)
 {
-	region_register rr_save, rr;
+	region_register_t rr_save, rr;
 	size_t vrn;
 	rid_t rid;
 	uint64_t tag;
-
+	
 	vhpt_entry_t *ventry;
-
-
+	
 	vrn = va >> VRN_SHIFT;
 	rid = ASID2RID(asid, vrn);
-																												
+	
 	rr_save.word = rr_read(vrn);
 	rr.word = rr_save.word;
@@ -75,5 +74,5 @@
 	srlz_i();
 	srlz_d();
-
+	
 	ventry->word[0] = entry.word[0];
 	ventry->word[1] = entry.word[1];
Index: kernel/arch/ia64/src/start.S
===================================================================
--- kernel/arch/ia64/src/start.S	(revision e86a849a744c5d659718b8d55becc3bbee6655ac)
+++ kernel/arch/ia64/src/start.S	(revision 5bda2f3ec5d347e6cd33782ee9f7583f6d3aeda4)
@@ -32,13 +32,13 @@
 #include <mm/asid.h>
 
-#define RR_MASK (0xFFFFFFFF00000002)
-#define RID_SHIFT	8
-#define PS_SHIFT	2
-
-#define KERNEL_TRANSLATION_I	0x0010000000000661
-#define KERNEL_TRANSLATION_D	0x0010000000000661
-#define KERNEL_TRANSLATION_VIO	0x0010000000000671
-#define KERNEL_TRANSLATION_IO	0x00100FFFFC000671 
-#define KERNEL_TRANSLATION_FW	0x00100000F0000671 
+#define RR_MASK    (0xFFFFFFFF00000002)
+#define RID_SHIFT  8
+#define PS_SHIFT   2
+
+#define KERNEL_TRANSLATION_I    0x0010000000000661
+#define KERNEL_TRANSLATION_D    0x0010000000000661
+#define KERNEL_TRANSLATION_VIO  0x0010000000000671
+#define KERNEL_TRANSLATION_IO   0x00100FFFFC000671
+#define KERNEL_TRANSLATION_FW   0x00100000F0000671
 
 .section K_TEXT_START, "ax"
@@ -49,8 +49,8 @@
 kernel_image_start:
 	.auto
-
+	
 #ifdef CONFIG_SMP
 	# Identify self(CPU) in OS structures by ID / EID
-
+	
 	mov r9 = cr64
 	mov r10 = 1
@@ -62,34 +62,34 @@
 	st1 [r8] = r10
 #endif
-
+	
 	mov psr.l = r0
 	srlz.i
 	srlz.d
-
+	
 	# Fill TR.i and TR.d using Region Register #VRN_KERNEL
-
+	
 	movl r8 = (VRN_KERNEL << VRN_SHIFT)
 	mov r9 = rr[r8]
-
+	
 	movl r10 = (RR_MASK)
 	and r9 = r10, r9
 	movl r10 = ((RID_KERNEL << RID_SHIFT) | (KERNEL_PAGE_WIDTH << PS_SHIFT))
-	or  r9 = r10, r9
-
+	or r9 = r10, r9
+	
 	mov rr[r8] = r9
-
+	
 	movl r8 = (VRN_KERNEL << VRN_SHIFT)
 	mov cr.ifa = r8
-
+	
 	mov r11 = cr.itir
 	movl r10 = (KERNEL_PAGE_WIDTH << PS_SHIFT)
 	or r10 = r10, r11
 	mov cr.itir = r10
-
+	
 	movl r10 = (KERNEL_TRANSLATION_I)
 	itr.i itr[r0] = r10
 	movl r10 = (KERNEL_TRANSLATION_D)
 	itr.d dtr[r0] = r10
-
+	
 	movl r7 = 1
 	movl r8 = (VRN_KERNEL << VRN_SHIFT) | VIO_OFFSET
@@ -97,5 +97,5 @@
 	movl r10 = (KERNEL_TRANSLATION_VIO)
 	itr.d dtr[r7] = r10
-
+	
 	mov r11 = cr.itir
 	movl r10 = ~0xfc
@@ -104,5 +104,5 @@
 	or r10 = r10, r11
 	mov cr.itir = r10
-
+	
 	movl r7 = 2
 	movl r8 = (VRN_KERNEL << VRN_SHIFT) | IO_OFFSET
@@ -110,7 +110,7 @@
 	movl r10 = (KERNEL_TRANSLATION_IO)
 	itr.d dtr[r7] = r10
-
-	# Setup mapping for fimware arrea (also SAPIC)
-
+	
+	# Setup mapping for firmware area (also SAPIC)
+	
 	mov r11 = cr.itir
 	movl r10 = ~0xfc
@@ -119,5 +119,5 @@
 	or r10 = r10, r11
 	mov cr.itir = r10
-
+	
 	movl r7 = 3
 	movl r8 = (VRN_KERNEL << VRN_SHIFT) | FW_OFFSET
@@ -125,10 +125,10 @@
 	movl r10 = (KERNEL_TRANSLATION_FW)
 	itr.d dtr[r7] = r10
-
+	
 	# Initialize PSR
-
+	
 	movl r10 = (PSR_DT_MASK | PSR_RT_MASK | PSR_IT_MASK | PSR_IC_MASK)  /* Enable paging */
 	mov r9 = psr
-
+	
 	or r10 = r10, r9
 	mov cr.ipsr = r10
@@ -138,7 +138,7 @@
 	srlz.d
 	srlz.i
-
+	
 	.explicit
-
+	
 	/*
 	 * Return From Interrupt is the only way to
@@ -147,15 +147,14 @@
 	rfi ;;
 
-
 .global paging_start
 paging_start:
-
+	
 	/*
 	 * Now we are paging.
 	 */
-
+	
 	# Switch to register bank 1
 	bsw.1
-
+	
 #ifdef CONFIG_SMP
 	# Am I BSP or AP?
@@ -164,6 +163,6 @@
 	cmp.eq p3, p2 = r20, r0 ;;
 #else
-	cmp.eq p3, p2 = r0, r0 ;;	/* you are BSP */
-#endif	/* CONFIG_SMP */
+	cmp.eq p3, p2 = r0, r0 ;;  /* you are BSP */
+#endif  /* CONFIG_SMP */
 	
 	# Initialize register stack
@@ -172,12 +171,12 @@
 	mov ar.bspstore = r8
 	loadrs
-
+	
 	# Initialize memory stack to some sane value
 	movl r12 = stack0 ;;
-	add r12 = -16, r12	/* allocate a scratch area on the stack */
-
+	add r12 = -16, r12  /* allocate a scratch area on the stack */
+	
 	# Initialize gp (Global Pointer) register
-	movl r20 = (VRN_KERNEL << VRN_SHIFT);;
-	or r20 = r20,r1;;
+	movl r20 = (VRN_KERNEL << VRN_SHIFT) ;;
+	or r20 = r20, r1 ;;
 	movl r1 = _hardcoded_load_address
 	
@@ -192,27 +191,28 @@
 (p3)	addl r19 = @gprel(hardcoded_load_address), gp
 (p3)	addl r21 = @gprel(bootinfo), gp
-	;;
+		;;
 (p3)	st8 [r17] = r14
 (p3)	st8 [r18] = r15
 (p3)	st8 [r19] = r16
 (p3)	st8 [r21] = r20
-
+	
 	ssm (1 << 19) ;; /* Disable f32 - f127 */
 	srlz.i
 	srlz.d ;;
-
+	
 #ifdef CONFIG_SMP
 (p2)	movl r18 = main_ap ;;
-(p2)   	mov b1 = r18 ;;
+(p2)	mov b1 = r18 ;;
 (p2)	br.call.sptk.many b0 = b1
-
+	
 	# Mark that BSP is on
+	
 	mov r20 = 1 ;;
 	movl r21 = bsp_started ;;
 	st8 [r21] = r20 ;;
 #endif
-
+	
 	br.call.sptk.many b0 = arch_pre_main
-
+	
 	movl r18 = main_bsp ;;
 	mov b1 = r18 ;;
@@ -227,7 +227,7 @@
 kernel_image_ap_start:
 	.auto
-
+	
 	# Identify self(CPU) in OS structures by ID / EID
-
+	
 	mov r9 = cr64
 	mov r10 = 1
@@ -240,18 +240,18 @@
 	
 	# Wait for wakeup synchro signal (#3 in cpu_by_id_eid_list)
-	
+
 kernel_image_ap_start_loop:
 	movl r11 = kernel_image_ap_start_loop
 	and r11 = r11, r12
-   	mov b1 = r11 
-
-	ld1 r20 = [r8] ;;
-	movl r21 = 3 ;;
-	cmp.eq p2, p3 = r20, r21 ;;
+	mov b1 = r11
+	
+	ld1 r20 = [r8]
+	movl r21 = 3
+	cmp.eq p2, p3 = r20, r21
 (p3)	br.call.sptk.many b0 = b1
-
+	
 	movl r11 = kernel_image_start
 	and r11 = r11, r12
-	mov b1 = r11 
+	mov b1 = r11
 	br.call.sptk.many b0 = b1
 
@@ -259,10 +259,10 @@
 .global bsp_started
 bsp_started:
-.space 8
+	.space 8
 
 .align 4096
 .global cpu_by_id_eid_list
 cpu_by_id_eid_list:
-.space 65536
-
-#endif	/* CONFIG_SMP */
+	.space 65536
+
+#endif  /* CONFIG_SMP */