Index: kernel/arch/ppc32/include/arch/asm.h
===================================================================
--- kernel/arch/ppc32/include/arch/asm.h	(revision 3da166f05b0e0513fe18f82b34f75ef99bef955a)
+++ kernel/arch/ppc32/include/arch/asm.h	(revision 5a42886138d4aab0bf370134954892eb9896554a)
@@ -58,4 +58,5 @@
 	asm volatile (
 		"mtmsr %[msr]\n"
+		"isync\n"
 		:: [msr] "r" (msr)
 	);
@@ -66,4 +67,6 @@
 	asm volatile (
 		"mtsrin %[value], %[sr]\n"
+		"sync\n"
+		"isync\n"
 		:: [value] "r" ((flags << 16) + (asid << 4) + sr),
 		   [sr] "r" (sr << 28)
Index: kernel/arch/ppc32/src/asm.S
===================================================================
--- kernel/arch/ppc32/src/asm.S	(revision 3da166f05b0e0513fe18f82b34f75ef99bef955a)
+++ kernel/arch/ppc32/src/asm.S	(revision 5a42886138d4aab0bf370134954892eb9896554a)
@@ -55,4 +55,5 @@
 	rlwinm r31, r31, 0, 17, 15
 	mtmsr r31
+	isync
 	
 	/* Set entry point */
@@ -85,4 +86,5 @@
 	rlwinm r31, r31, 0, 17, 15
 	mtmsr r31
+	isync
 	
 	lwz r0, ISTATE_OFFSET_R0(sp)
@@ -152,4 +154,5 @@
 	rlwinm r31, r31, 0, 17, 15
 	mtmsr r31
+	isync
 	
 	lwz r0, ISTATE_OFFSET_R0(sp)
Index: kernel/arch/ppc32/src/fpu_context.S
===================================================================
--- kernel/arch/ppc32/src/fpu_context.S	(revision 3da166f05b0e0513fe18f82b34f75ef99bef955a)
+++ kernel/arch/ppc32/src/fpu_context.S	(revision 5a42886138d4aab0bf370134954892eb9896554a)
@@ -119,6 +119,6 @@
 fpu_context_restore:
 	lfd fr0, FPU_CONTEXT_OFFSET_FPSCR(r3)
-	mtfsf 7, fr0
-
+	mtfsf 0xff, fr0
+	
 	FPU_CONTEXT_LOAD r3
 	
@@ -128,10 +128,12 @@
 	mfmsr r0
 	ori r0, r0, MSR_FP
-
+	
 	# Disable FPU exceptions
 	li r3, MSR_FE0 | MSR_FE1
 	andc r0, r0, r3
-
+	
 	mtmsr r0
+	isync
+	
 	blr
 
@@ -140,4 +142,5 @@
 	ori r0, r0, MSR_FP
 	mtmsr r0
+	isync
 	blr
 
@@ -147,4 +150,4 @@
 	andc r0, r0, r3
 	mtmsr r0
+	isync
 	blr
-