Index: kernel/arch/sparc64/src/mm/sun4v/tlb.c
===================================================================
--- kernel/arch/sparc64/src/mm/sun4v/tlb.c	(revision 5e53e02708b7fe7afa7635c8ea1a0738d1329937)
+++ kernel/arch/sparc64/src/mm/sun4v/tlb.c	(revision 58d5803d422309587aa1e5c37ec90f119d64af5d)
@@ -34,5 +34,4 @@
  */
 
-#include <arch/mm/tlb.h>
 #include <mm/tlb.h>
 #include <mm/as.h>
@@ -60,9 +59,9 @@
 #endif
 
-void dtlb_pte_copy(pte_t *t, bool ro);
 static void itlb_pte_copy(pte_t *);
+static void dtlb_pte_copy(pte_t *, bool);
 static void do_fast_instruction_access_mmu_miss_fault(istate_t *, const char *);
-void do_fast_data_access_mmu_miss_fault(istate_t *istate,
-    uint64_t page_and_ctx, const char *str);
+static void do_fast_data_access_mmu_miss_fault(istate_t *, uint64_t,
+    const char *);
 static void do_fast_data_access_protection_fault(istate_t *,
     uint64_t, const char *);
@@ -83,21 +82,36 @@
 #define DMISS_CONTEXT(page_and_ctx)	((page_and_ctx) & 0x1fff)
 
-char *context_encoding[] = {
-	"Primary",
-	"Secondary",
-	"Nucleus",
-	"Reserved"
-};
-
-/** Invalidate all unlocked ITLB and DTLB entries. */
-void tlb_invalidate_all(void)
-{
-	uint64_t errno =  __hypercall_fast3(MMU_DEMAP_ALL, 0, 0,
-		MMU_FLAG_DTLB | MMU_FLAG_ITLB);
-	if (errno != EOK) {
-		panic("Error code = %d.\n", errno);
-	}
-}
-
+/**
+ * Descriptions of fault types from the MMU Fault status area.
+ *
+ * fault_type[i] contains description of error for which the IFT or DFT
+ * field of the MMU fault status area is i.
+ */
+char *fault_types[] = {
+	"unknown",
+	"fast miss",
+	"fast protection",
+	"MMU miss",
+	"invalid RA",
+	"privileged violation",
+	"protection violation",
+	"NFO access",
+	"so page/NFO side effect",
+	"invalid VA",
+	"invalid ASI",
+	"nc atomic",
+	"privileged action",
+	"unknown",
+	"unaligned access",
+	"invalid page size"
+	};
+	
+
+/** Array of MMU fault status areas. */
+extern mmu_fault_status_area_t mmu_fsas[MAX_NUM_STRANDS];
+
+/*
+ * Invalidate all non-locked DTLB and ITLB entries.
+ */
 void tlb_arch_init(void)
 {
@@ -116,33 +130,29 @@
     bool locked, bool cacheable)
 {
-#if 0
-	tlb_tag_access_reg_t tag;
-	tlb_data_t data;
-	page_address_t pg;
-	frame_address_t fr;
-
-	pg.address = page;
-	fr.address = frame;
-
-	tag.context = ASID_KERNEL;
-	tag.vpn = pg.vpn;
-
-	dtlb_tag_access_write(tag.value);
-
+	tte_data_t data;
+	
 	data.value = 0;
 	data.v = true;
-	data.size = pagesize;
-	data.pfn = fr.pfn;
-	data.l = locked;
+	data.nfo = false;
+	data.ra = frame >> FRAME_WIDTH;
+	data.ie = false;
+	data.e = false;
 	data.cp = cacheable;
 #ifdef CONFIG_VIRT_IDX_DCACHE
 	data.cv = cacheable;
-#endif /* CONFIG_VIRT_IDX_DCACHE */
+#endif
 	data.p = true;
+	data.x = false;
 	data.w = true;
-	data.g = false;
-
-	dtlb_data_in_write(data.value);
-#endif
+	data.size = pagesize;
+	
+	if (locked) {
+		__hypercall_fast4(
+			MMU_MAP_PERM_ADDR, page, 0, data.value, MMU_FLAG_DTLB);
+	} else {
+		__hypercall_hyperfast(
+			page, ASID_KERNEL, data.value, MMU_FLAG_DTLB, 0,
+			MMU_MAP_ADDR);
+	}
 }
 
@@ -175,5 +185,4 @@
 		t->page, t->as->asid, data.value, MMU_FLAG_DTLB, 0, MMU_MAP_ADDR);
 }
-
 
 /** Copy PTE to ITLB.
@@ -288,5 +297,4 @@
 		}
 	}
-	asm volatile ("sethi 0x41941, %g0");
 }
 
@@ -336,13 +344,8 @@
 }
 
-
-/** Print TLB entry (for debugging purposes).
- *
- * The diag field has been left out in order to make this function more generic
- * (there is no diag field in US3 architeture). 
- *
- * @param i		TLB entry number 
- * @param t		TLB entry tag
- * @param d		TLB entry data 
+/*
+ * On Niagara this function does not work, as supervisor software is isolated
+ * from the TLB by the hypervisor and has no chance to investigate the TLB
+ * entries.
  */
 void tlb_print(void)
@@ -388,5 +391,4 @@
 void describe_dmmu_fault(void)
 {
-#if 0
 	uint64_t myid;
 	__hypercall_fast_ret1(0, 0, 0, 0, 0, CPU_MYID, &myid);
@@ -406,5 +408,4 @@
 		panic("Error code = %d.\n", errno);
 	}
-#endif
 }
 
@@ -418,4 +419,5 @@
 	/* switch to nucleus because we are mapped by the primary context */
 	nucleus_enter();
+
 	__hypercall_fast4(MMU_DEMAP_CTX, 0, 0, asid,
 		MMU_FLAG_ITLB | MMU_FLAG_DTLB);