Ignore:
Timestamp:
2015-03-16T16:07:21Z (10 years ago)
Author:
Jan Vesely <jano.vesely@…>
Branches:
lfn, master, serial, ticket/834-toolchain-update, topic/msim-upgrade, topic/simplify-dev-export
Children:
2003739
Parents:
6069061 (diff), 795e2bf (diff)
Note: this is a merge changeset, the changes displayed below correspond to the merge itself.
Use the (diff) links above to see all the changes relative to each parent.
Message:

Mainline changes

File:
1 edited

Legend:

Unmodified
Added
Removed

  • kernel/arch/sparc64/include/arch/trap/sun4u/mmu.h

    r6069061 r58775d30  
    74740:
    7575        wrpr %g0, PSTATE_PRIV_BIT | PSTATE_AG_BIT, %pstate
    76         PREEMPTIBLE_HANDLER fast_instruction_access_mmu_miss
     76        mov TT_FAST_INSTRUCTION_ACCESS_MMU_MISS, %g2
     77        mov VA_IMMU_TAG_ACCESS, %g5
     78        ldxa [%g5] ASI_IMMU, %g5                        ! read the faulting Context and VPN
     79        PREEMPTIBLE_HANDLER exc_dispatch
    7780.endm
    7881
    … …  
    107110        wr %g0, ASI_DMMU, %asi
    108111        ldxa [VA_DMMU_TAG_ACCESS] %asi, %g1             ! read the faulting Context and VPN
    109         set TLB_TAG_ACCESS_CONTEXT_MASK, %g2
     112        ldx [%g7 + %lo(tlb_tag_access_context_mask)], %g2
    110113        andcc %g1, %g2, %g3                             ! get Context
    111114        bnz %xcc, 0f                                    ! Context is non-zero
    … …  
    138141        wrpr %g0, PSTATE_PRIV_BIT | PSTATE_AG_BIT, %pstate
    139142
    140         /*
    141          * Read the Tag Access register for the higher-level handler.
    142          * This is necessary to survive nested DTLB misses.
    143          */     
    144         ldxa [VA_DMMU_TAG_ACCESS] %asi, %g2
    145 
    146         /*
    147          * g2 will be passed as an argument to fast_data_access_mmu_miss().
    148          */
    149         PREEMPTIBLE_HANDLER fast_data_access_mmu_miss
     143        mov TT_FAST_DATA_ACCESS_MMU_MISS, %g2
     144        ldxa [VA_DMMU_TAG_ACCESS] %asi, %g5             ! read the faulting Context and VPN
     145        PREEMPTIBLE_HANDLER exc_dispatch
    150146.endm
    151147
    … …  
    164160        wrpr %g0, PSTATE_PRIV_BIT | PSTATE_AG_BIT, %pstate
    165161
    166         /*
    167          * Read the Tag Access register for the higher-level handler.
    168          * This is necessary to survive nested DTLB misses.
    169          */     
    170         mov VA_DMMU_TAG_ACCESS, %g2
    171         ldxa [%g2] ASI_DMMU, %g2
    172 
    173         /*
    174          * g2 will be passed as an argument to fast_data_access_mmu_miss().
    175          */
    176         PREEMPTIBLE_HANDLER fast_data_access_protection
     162        mov TT_FAST_DATA_ACCESS_PROTECTION, %g2
     163        mov VA_DMMU_TAG_ACCESS, %g5
     164        ldxa [%g5] ASI_DMMU, %g5                        ! read the faulting Context and VPN
     165        PREEMPTIBLE_HANDLER exc_dispatch
    177166.endm
    178167
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