Index: kernel/arch/amd64/include/arch/cpu.h
===================================================================
--- kernel/arch/amd64/include/arch/cpu.h	(revision 811770c99b96760cdbd8d7f79f5e5bcb969a353e)
+++ kernel/arch/amd64/include/arch/cpu.h	(revision 57c2a87b03a0b6c08cef4f64f0cf52a7d8b38b62)
@@ -50,4 +50,5 @@
 #define RFLAGS_ID	(1 << 21)
 
+#define CR0_PE		(1 << 0)
 #define CR0_MP		(1 << 1)
 #define CR0_EM		(1 << 2)
Index: kernel/arch/amd64/src/smp/ap.S
===================================================================
--- kernel/arch/amd64/src/smp/ap.S	(revision 811770c99b96760cdbd8d7f79f5e5bcb969a353e)
+++ kernel/arch/amd64/src/smp/ap.S	(revision 57c2a87b03a0b6c08cef4f64f0cf52a7d8b38b62)
@@ -58,5 +58,5 @@
 	
 	movl %cr0, %eax
-	orl $1, %eax
+	orl $CR0_PE, %eax
 	movl %eax, %cr0     # switch to protected mode
 	jmpl $GDT_SELECTOR(KTEXT32_DES), $jump_to_kernel - BOOT_OFFSET + AP_BOOT_OFFSET
Index: kernel/arch/ia32/include/arch/cpu.h
===================================================================
--- kernel/arch/ia32/include/arch/cpu.h	(revision 811770c99b96760cdbd8d7f79f5e5bcb969a353e)
+++ kernel/arch/ia32/include/arch/cpu.h	(revision 57c2a87b03a0b6c08cef4f64f0cf52a7d8b38b62)
@@ -41,5 +41,8 @@
 #define EFLAGS_NT	(1 << 14)
 #define EFLAGS_RF	(1 << 16)
+#define EFLAGS_ID	(1 << 21)
 
+#define CR0_PE		(1 << 0) 
+#define CR0_TS		(1 << 3)
 #define CR0_AM		(1 << 18)
 #define CR0_NW		(1 << 29)
@@ -47,6 +50,8 @@
 #define CR0_PG		(1 << 31)
 
-#define CR4_OSFXSR_MASK		(1 << 9)
-#define CR4_OSXMMEXCPT_MASK	(1 << 10)
+#define CR4_PSE		(1 << 4)
+#define CR4_PAE		(1 << 5)
+#define CR4_OSFXSR	(1 << 9)
+#define CR4_OSXMMEXCPT	(1 << 10)
 
 #define IA32_APIC_BASE_GE	(1 << 11)
Index: kernel/arch/ia32/include/arch/cpuid.h
===================================================================
--- kernel/arch/ia32/include/arch/cpuid.h	(revision 811770c99b96760cdbd8d7f79f5e5bcb969a353e)
+++ kernel/arch/ia32/include/arch/cpuid.h	(revision 57c2a87b03a0b6c08cef4f64f0cf52a7d8b38b62)
@@ -44,4 +44,5 @@
 
 #include <typedefs.h>
+#include <arch/cpu.h>
 
 typedef struct {
@@ -84,19 +85,20 @@
 	
 	asm volatile (
-		"pushf\n"                    /* read flags */
+		"pushf\n"			/* read flags */
 		"popl %[ret]\n"
 		"movl %[ret], %[val]\n"
 		
-		"btcl $21, %[val]\n"         /* swap the ID bit */
+		"xorl %[eflags_id], %[val]\n"	/* swap the ID bit */
 		
-		"pushl %[val]\n"             /* propagate the change into flags */
+		"pushl %[val]\n"		/* propagate the change into flags */
 		"popf\n"
 		"pushf\n"
 		"popl %[val]\n"
 		
-		"andl $(1 << 21), %[ret]\n"  /* interrested only in ID bit */
-		"andl $(1 << 21), %[val]\n"
+		"andl %[eflags_id], %[ret]\n"	/* interrested only in ID bit */
+		"andl %[eflags_id], %[val]\n"
 		"xorl %[val], %[ret]\n"
 		: [ret] "=r" (ret), [val] "=r" (val)
+		: [eflags_id] "i" (EFLAGS_ID)
 	);
 	
Index: kernel/arch/ia32/src/boot/multiboot.S
===================================================================
--- kernel/arch/ia32/src/boot/multiboot.S	(revision 811770c99b96760cdbd8d7f79f5e5bcb969a353e)
+++ kernel/arch/ia32/src/boot/multiboot.S	(revision 57c2a87b03a0b6c08cef4f64f0cf52a7d8b38b62)
@@ -35,4 +35,5 @@
 #include <genarch/multiboot/multiboot.h>
 #include <arch/cpuid.h>
+#include <arch/cpu.h>
 
 #define START_STACK  (BOOT_OFFSET - BOOT_STACK_SIZE)
@@ -166,6 +167,6 @@
 	/* Paging features */
 	movl %cr4, %ecx
-	orl $(1 << 4), %ecx      /* PSE on */
-	andl $(~(1 << 5)), %ecx  /* PAE off */
+	orl $CR4_PSE, %ecx	/* PSE on */
+	andl $~CR4_PAE, %ecx	/* PAE off */
 	movl %ecx, %cr4
 	
@@ -191,5 +192,5 @@
 	
 	movl %cr0, %ebx
-	orl $(1 << 31), %ebx  /* paging on */
+	orl $CR0_PG, %ebx	/* paging on */
 	movl %ebx, %cr0
 	ret
@@ -205,5 +206,5 @@
 	/* Paging features */
 	movl %cr4, %ecx
-	andl $(~(1 << 5)), %ecx  /* PAE off */
+	andl $~CR4_PAE, %ecx  /* PAE off */
 	movl %ecx, %cr4
 	
@@ -277,5 +278,5 @@
 		
 		movl %cr0, %ebx
-		orl $(1 << 31), %ebx  /* paging on */
+		orl $CR0_PG, %ebx  /* paging on */
 		movl %ebx, %cr0
 		
Index: kernel/arch/ia32/src/boot/vesa_real.inc
===================================================================
--- kernel/arch/ia32/src/boot/vesa_real.inc	(revision 811770c99b96760cdbd8d7f79f5e5bcb969a353e)
+++ kernel/arch/ia32/src/boot/vesa_real.inc	(revision 57c2a87b03a0b6c08cef4f64f0cf52a7d8b38b62)
@@ -49,5 +49,5 @@
 vesa_init_real:
 	mov %cr0, %eax
-	and $~1, %eax
+	and $~CR0_PE, %eax
 	mov %eax, %cr0
 	
@@ -352,5 +352,5 @@
 		
 			mov %cr0, %ecx
-			or $1, %ecx
+			or $CR0_PE, %ecx
 			mov %ecx, %cr0
 			
Index: kernel/arch/ia32/src/cpu/cpu.c
===================================================================
--- kernel/arch/ia32/src/cpu/cpu.c	(revision 811770c99b96760cdbd8d7f79f5e5bcb969a353e)
+++ kernel/arch/ia32/src/cpu/cpu.c	(revision 57c2a87b03a0b6c08cef4f64f0cf52a7d8b38b62)
@@ -72,20 +72,10 @@
 void fpu_disable(void)
 {
-	asm volatile (
-		"mov %%cr0, %%eax\n"
-		"or $8, %%eax\n"
-		"mov %%eax, %%cr0\n"
-		::: "%eax"
-	);
+	write_cr0(read_cr0() & ~CR0_TS); 
 }
 
 void fpu_enable(void)
 {
-	asm volatile (
-		"mov %%cr0, %%eax\n"
-		"and $0xffFFffF7, %%eax\n"
-		"mov %%eax,%%cr0\n"
-		::: "%eax"
-	);
+	write_cr0(read_cr0() | CR0_TS); 
 }
 
@@ -115,5 +105,5 @@
 			"mov %[help], %%cr4\n"
 			: [help] "+r" (help)
-			: [mask] "i" (CR4_OSFXSR_MASK | CR4_OSXMMEXCPT_MASK)
+			: [mask] "i" (CR4_OSFXSR | CR4_OSXMMEXCPT)
 		);
 	}
Index: kernel/arch/ia32/src/smp/ap.S
===================================================================
--- kernel/arch/ia32/src/smp/ap.S	(revision 811770c99b96760cdbd8d7f79f5e5bcb969a353e)
+++ kernel/arch/ia32/src/smp/ap.S	(revision 57c2a87b03a0b6c08cef4f64f0cf52a7d8b38b62)
@@ -37,4 +37,5 @@
 #include <arch/mm/page.h>
 #include <arch/pm.h>
+#include <arch/cpu.h>
 
 .section K_TEXT_START, "ax"
@@ -63,5 +64,5 @@
 	/* switch to protected mode */
 	movl %cr0, %eax
-	orl $1, %eax
+	orl $CR0_PE, %eax
 	movl %eax, %cr0
 	jmpl $KTEXT, $jump_to_kernel - BOOT_OFFSET + AP_BOOT_OFFSET