Index: kernel/arch/ia32/src/fpu_context.c
===================================================================
--- kernel/arch/ia32/src/fpu_context.c	(revision fd57745cd4811832fa23ba1cef7638038244f2b5)
+++ kernel/arch/ia32/src/fpu_context.c	(revision 5754c31e4e22b3ba9c461583e759f5fed5d44704)
@@ -71,6 +71,6 @@
 {
 	asm volatile (
-		"fnsave %[fctx]"
-		: [fctx] "=m" (fctx->fpu)
+	    "fnsave %[fctx]"
+	    : [fctx] "=m" (fctx->fpu)
 	);
 }
@@ -79,6 +79,6 @@
 {
 	asm volatile (
-		"frstor %[fctx]"
-		: [fctx] "=m" (fctx->fpu)
+	    "frstor %[fctx]"
+	    : [fctx] "=m" (fctx->fpu)
 	);
 }
@@ -87,6 +87,6 @@
 {
 	asm volatile (
-		"fxsave %[fctx]"
-		: [fctx] "=m" (fctx->fpu)
+	    "fxsave %[fctx]"
+	    : [fctx] "=m" (fctx->fpu)
 	);
 }
@@ -95,6 +95,6 @@
 {
 	asm volatile (
-		"fxrstor %[fctx]"
-		: [fctx] "=m" (fctx->fpu)
+	    "fxrstor %[fctx]"
+	    : [fctx] "=m" (fctx->fpu)
 	);
 }
@@ -131,12 +131,12 @@
 
 	asm volatile (
-		"fninit\n"
-		"stmxcsr %[help0]\n"
-		"mov %[help0], %[help1]\n"
-		"or %[magic], %[help1]\n"
-		"mov %[help1], %[help0]\n"
-		"ldmxcsr %[help0]\n"
-		: [help0] "+m" (help0), [help1] "+r" (help1)
-		: [magic] "i" (X87_ALL_MASK)
+	    "fninit\n"
+	    "stmxcsr %[help0]\n"
+	    "mov %[help0], %[help1]\n"
+	    "or %[magic], %[help1]\n"
+	    "mov %[help1], %[help0]\n"
+	    "ldmxcsr %[help0]\n"
+	    : [help0] "+m" (help0), [help1] "+r" (help1)
+	    : [magic] "i" (X87_ALL_MASK)
 	);
 }
Index: kernel/arch/ia32/src/interrupt.c
===================================================================
--- kernel/arch/ia32/src/interrupt.c	(revision fd57745cd4811832fa23ba1cef7638038244f2b5)
+++ kernel/arch/ia32/src/interrupt.c	(revision 5754c31e4e22b3ba9c461583e759f5fed5d44704)
@@ -62,7 +62,7 @@
  */
 
-void (* disable_irqs_function)(uint16_t irqmask) = NULL;
-void (* enable_irqs_function)(uint16_t irqmask) = NULL;
-void (* eoi_function)(void) = NULL;
+void (*disable_irqs_function)(uint16_t irqmask) = NULL;
+void (*enable_irqs_function)(uint16_t irqmask) = NULL;
+void (*eoi_function)(void) = NULL;
 const char *irqs_info = NULL;
 
@@ -146,6 +146,6 @@
 	uint32_t mxcsr;
 	asm volatile (
-		"stmxcsr %[mxcsr]\n"
-		: [mxcsr] "=m" (mxcsr)
+	    "stmxcsr %[mxcsr]\n"
+	    : [mxcsr] "=m" (mxcsr)
 	);
 
Index: kernel/arch/ia32/src/mm/frame.c
===================================================================
--- kernel/arch/ia32/src/mm/frame.c	(revision fd57745cd4811832fa23ba1cef7638038244f2b5)
+++ kernel/arch/ia32/src/mm/frame.c	(revision 5754c31e4e22b3ba9c461583e759f5fed5d44704)
@@ -142,5 +142,5 @@
 			name = "invalid";
 
-		printf("%#018" PRIx64 " %#018" PRIx64" %s\n", e820table[i].base_address,
+		printf("%#018" PRIx64 " %#018" PRIx64 " %s\n", e820table[i].base_address,
 		    e820table[i].size, name);
 	}
Index: kernel/arch/ia32/src/smp/apic.c
===================================================================
--- kernel/arch/ia32/src/smp/apic.c	(revision fd57745cd4811832fa23ba1cef7638038244f2b5)
+++ kernel/arch/ia32/src/smp/apic.c	(revision 5754c31e4e22b3ba9c461583e759f5fed5d44704)
@@ -482,5 +482,6 @@
 	l_apic[ICRT] = 0xffffffff;
 
-	while (l_apic[CCRT] == t1);
+	while (l_apic[CCRT] == t1)
+		;
 
 	t1 = l_apic[CCRT];
Index: kernel/arch/ia32/src/smp/mps.c
===================================================================
--- kernel/arch/ia32/src/smp/mps.c	(revision fd57745cd4811832fa23ba1cef7638038244f2b5)
+++ kernel/arch/ia32/src/smp/mps.c	(revision 5754c31e4e22b3ba9c461583e759f5fed5d44704)
@@ -257,5 +257,5 @@
 	}
 
-	log_printf(", bus=%" PRIu8 " irq=%" PRIu8 " io_apic=%" PRIu8" pin=%"
+	log_printf(", bus=%" PRIu8 " irq=%" PRIu8 " io_apic=%" PRIu8 " pin=%"
 	    PRIu8, iointr->src_bus_id, iointr->src_bus_irq,
 	    iointr->dst_io_apic_id, iointr->dst_io_apic_pin);
@@ -320,5 +320,5 @@
 	}
 
-	log_printf(", bus=%" PRIu8 " irq=%" PRIu8 " l_apic=%" PRIu8" pin=%"
+	log_printf(", bus=%" PRIu8 " irq=%" PRIu8 " l_apic=%" PRIu8 " pin=%"
 	    PRIu8, lintr->src_bus_id, lintr->src_bus_irq,
 	    lintr->dst_l_apic_id, lintr->dst_l_apic_pin);