Changes in / [5a9f4d7:571addd] in mainline
- Files:
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- 4 added
- 17 edited
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HelenOS.config
r5a9f4d7 r571addd 441 441 ! [(CONFIG_HID_OUT=generic|CONFIG_HID_OUT=serial)&PLATFORM=arm32&MACHINE=gta02] CONFIG_S3C24XX_UART (y/n) 442 442 443 % Support for Samsung S3C24XX on-chip interrupt controller 444 ! [PLATFORM=arm32&MACHINE=gta02] CONFIG_S3C24XX_IRQC (y) 445 443 446 % Support for Z8530 controller 444 447 ! [(CONFIG_HID_IN=generic|CONFIG_HID_IN=keyboard)&PLATFORM=sparc64&MACHINE=generic] CONFIG_Z8530 (y/n) … … 469 472 470 473 % Serial line input module 471 ! [CONFIG_DSRLNIN=y|(PLATFORM= ia64&MACHINE=i460GX&CONFIG_NS16550=y)|(PLATFORM=ia64&MACHINE=ski)|(PLATFORM=sparc64&MACHINE=serengeti&CONFIG_SGCN_KBD=y)|(PLATFORM=sparc64&PROCESSOR=sun4v)] CONFIG_SRLN (y)474 ! [CONFIG_DSRLNIN=y|(PLATFORM=arm32&MACHINE=gta02)|(PLATFORM=ia64&MACHINE=i460GX&CONFIG_NS16550=y)|(PLATFORM=ia64&MACHINE=ski)|(PLATFORM=sparc64&MACHINE=serengeti&CONFIG_SGCN_KBD=y)|(PLATFORM=sparc64&PROCESSOR=sun4v)] CONFIG_SRLN (y) 472 475 473 476 % EGA support -
boot/arch/arm32/Makefile.inc
r5a9f4d7 r571addd 41 41 PAGE_SIZE = 4096 42 42 43 RD_SRVS_ESSENTIAL += 43 RD_SRVS_ESSENTIAL += \ 44 $(USPACE_PATH)/srv/hw/char/s3c24xx_uart/s3c24ser 44 45 45 46 RD_SRVS_NON_ESSENTIAL += \ -
kernel/arch/arm32/include/mach/integratorcp/integratorcp.h
r5a9f4d7 r571addd 105 105 extern void icp_get_memory_extents(uintptr_t *, uintptr_t *); 106 106 extern void icp_frame_init(void); 107 extern size_t icp_get_irq_count(void); 107 108 108 109 extern struct arm_machine_ops icp_machine_ops; -
kernel/arch/arm32/include/mach/testarm/testarm.h
r5a9f4d7 r571addd 73 73 extern void gxemul_get_memory_extents(uintptr_t *, uintptr_t *); 74 74 extern void gxemul_frame_init(void); 75 extern size_t gxemul_get_irq_count(void); 75 76 76 77 extern struct arm_machine_ops gxemul_machine_ops; -
kernel/arch/arm32/include/machine_func.h
r5a9f4d7 r571addd 55 55 void (*machine_output_init)(void); 56 56 void (*machine_input_init)(void); 57 size_t (*machine_get_irq_count)(void); 57 58 }; 58 59 -
kernel/arch/arm32/src/mach/gta02/gta02.c
r5a9f4d7 r571addd 43 43 #include <genarch/drivers/s3c24xx_irqc/s3c24xx_irqc.h> 44 44 #include <genarch/drivers/s3c24xx_timer/s3c24xx_timer.h> 45 #include <genarch/srln/srln.h> 46 #include <sysinfo/sysinfo.h> 45 47 #include <interrupt.h> 46 48 #include <ddi/ddi.h> … … 68 70 static void gta02_output_init(void); 69 71 static void gta02_input_init(void); 72 static size_t gta02_get_irq_count(void); 70 73 71 74 static void gta02_timer_irq_init(void); … … 74 77 static void gta02_timer_irq_handler(irq_t *irq); 75 78 76 static void *gta02_scons_out;77 static s3c24xx_irqc_t *gta02_irqc;79 static outdev_t *gta02_scons_dev; 80 static s3c24xx_irqc_t gta02_irqc; 78 81 static s3c24xx_timer_t *gta02_timer; 79 82 … … 88 91 gta02_frame_init, 89 92 gta02_output_init, 90 gta02_input_init 93 gta02_input_init, 94 gta02_get_irq_count 91 95 }; 92 96 93 97 static void gta02_init(void) 94 98 { 95 gta02_scons_out = (void *) hw_map(GTA02_SCONS_BASE, PAGE_SIZE);96 gta02_irqc = (void *) hw_map(S3C24XX_IRQC_ADDRESS, PAGE_SIZE); 99 s3c24xx_irqc_regs_t *irqc_regs; 100 97 101 gta02_timer = (void *) hw_map(S3C24XX_TIMER_ADDRESS, PAGE_SIZE); 98 99 /* Make all interrupt sources use IRQ mode (not FIQ). */ 100 pio_write_32(>a02_irqc->intmod, 0x00000000); 101 102 /* Disable all interrupt sources. */ 103 pio_write_32(>a02_irqc->intmsk, 0xffffffff); 104 105 /* Disable interrupts from all sub-sources. */ 106 pio_write_32(>a02_irqc->intsubmsk, 0xffffffff); 102 irqc_regs = (void *) hw_map(S3C24XX_IRQC_ADDRESS, PAGE_SIZE); 103 104 /* Initialize interrupt controller. */ 105 s3c24xx_irqc_init(>a02_irqc, irqc_regs); 107 106 } 108 107 … … 132 131 uint32_t inum; 133 132 134 inum = pio_read_32(>a02_irqc->intoffset); 133 /* Determine IRQ number. */ 134 inum = s3c24xx_irqc_inum_get(>a02_irqc); 135 136 /* Clear interrupt condition in the interrupt controller. */ 137 s3c24xx_irqc_clear(>a02_irqc, inum); 135 138 136 139 irq_t *irq = irq_dispatch_and_lock(inum); … … 144 147 CPU->id, inum); 145 148 } 146 147 /* Clear interrupt condition in the interrupt controller. */148 pio_write_32(>a02_irqc->srcpnd, S3C24XX_INT_BIT(inum));149 pio_write_32(>a02_irqc->intpnd, S3C24XX_INT_BIT(inum));150 149 } 151 150 … … 176 175 } 177 176 #endif 178 outdev_t *scons_dev; 179 180 scons_dev = s3c24xx_uart_init((ioport8_t *) gta02_scons_out); 181 if (scons_dev) 182 stdout_wire(scons_dev); 177 178 /* Initialize serial port of the debugging console. */ 179 s3c24xx_uart_io_t *scons_io; 180 181 scons_io = (void *) hw_map(GTA02_SCONS_BASE, PAGE_SIZE); 182 gta02_scons_dev = s3c24xx_uart_init(scons_io, S3C24XX_INT_UART2); 183 184 if (gta02_scons_dev) { 185 /* Create output device. */ 186 stdout_wire(gta02_scons_dev); 187 } 188 189 /* 190 * This is the necessary evil until the userspace driver is entirely 191 * self-sufficient. 192 */ 193 sysinfo_set_item_val("s3c24xx_uart", NULL, true); 194 sysinfo_set_item_val("s3c24xx_uart.inr", NULL, S3C24XX_INT_UART2); 195 sysinfo_set_item_val("s3c24xx_uart.address.physical", NULL, 196 (uintptr_t) GTA02_SCONS_BASE); 197 183 198 } 184 199 185 200 static void gta02_input_init(void) 186 201 { 202 s3c24xx_uart_t *scons_inst; 203 204 if (gta02_scons_dev) { 205 /* Create input device. */ 206 scons_inst = (void *) gta02_scons_dev->data; 207 208 srln_instance_t *srln_instance = srln_init(); 209 if (srln_instance) { 210 indev_t *sink = stdin_wire(); 211 indev_t *srln = srln_wire(srln_instance, sink); 212 s3c24xx_uart_input_wire(scons_inst, srln); 213 214 /* Enable interrupts from UART2 */ 215 s3c24xx_irqc_src_enable(>a02_irqc, 216 S3C24XX_INT_UART2); 217 218 /* Enable interrupts from UART2 RXD */ 219 s3c24xx_irqc_subsrc_enable(>a02_irqc, 220 S3C24XX_SUBINT_RXD2); 221 } 222 } 223 } 224 225 size_t gta02_get_irq_count(void) 226 { 227 return GTA02_IRQ_COUNT; 187 228 } 188 229 … … 248 289 249 290 /* Enable interrupts from timer0 */ 250 pio_write_32(>a02_irqc->intmsk, pio_read_32(>a02_irqc->intmsk) & 251 ~S3C24XX_INT_BIT(S3C24XX_INT_TIMER0)); 291 s3c24xx_irqc_src_enable(>a02_irqc, S3C24XX_INT_TIMER0); 252 292 253 293 /* Load data from tcntb0/tcmpb0 into tcnt0/tcmp0. */ -
kernel/arch/arm32/src/mach/integratorcp/integratorcp.c
r5a9f4d7 r571addd 64 64 icp_frame_init, 65 65 icp_output_init, 66 icp_input_init 66 icp_input_init, 67 icp_get_irq_count 67 68 }; 68 69 … … 336 337 } 337 338 339 size_t icp_get_irq_count(void) 340 { 341 return ICP_IRQ_COUNT; 342 } 338 343 339 344 /** @} -
kernel/arch/arm32/src/mach/testarm/testarm.c
r5a9f4d7 r571addd 64 64 gxemul_frame_init, 65 65 gxemul_output_init, 66 gxemul_input_init 66 gxemul_input_init, 67 gxemul_get_irq_count 67 68 }; 68 69 … … 126 127 } 127 128 129 size_t gxemul_get_irq_count(void) 130 { 131 return GXEMUL_IRQ_COUNT; 132 } 133 128 134 /** Starts gxemul Real Time Clock device, which asserts regular interrupts. 129 135 * -
kernel/arch/arm32/src/machine_func.c
r5a9f4d7 r571addd 128 128 size_t machine_get_irq_count(void) 129 129 { 130 size_t irq_count; 131 132 #if defined(MACHINE_gta02) 133 irq_count = GTA02_IRQ_COUNT; 134 #elif defined(MACHINE_testarm) 135 irq_count = GXEMUL_IRQ_COUNT; 136 #elif defined(MACHINE_integratorcp) 137 irq_count = ICP_IRQ_COUNT; 138 #else 139 #error Machine type not defined. 140 #endif 141 return irq_count; 130 return (machine_ops->machine_get_irq_count)(); 142 131 } 143 132 -
kernel/genarch/Makefile.inc
r5a9f4d7 r571addd 90 90 endif 91 91 92 ifeq ($(CONFIG_S3C24XX_IRQC),y) 93 GENARCH_SOURCES += \ 94 genarch/src/drivers/s3c24xx_irqc/s3c24xx_irqc.c 95 endif 96 92 97 ifeq ($(CONFIG_S3C24XX_UART),y) 93 98 GENARCH_SOURCES += \ -
kernel/genarch/include/drivers/s3c24xx_irqc/s3c24xx_irqc.h
r5a9f4d7 r571addd 53 53 ioport32_t subsrcpnd; /**< Sub source pending */ 54 54 ioport32_t intsubmsk; /** Interrupt sub mask */ 55 } s3c24xx_irqc_ t;55 } s3c24xx_irqc_regs_t; 56 56 57 57 /** S3C24xx Interrupt source numbers. … … 120 120 #define S3C24XX_SUBINT_BIT(subsource) (1 << (subsource)) 121 121 122 typedef struct { 123 s3c24xx_irqc_regs_t *regs; 124 } s3c24xx_irqc_t; 125 126 extern void s3c24xx_irqc_init(s3c24xx_irqc_t *, s3c24xx_irqc_regs_t *); 127 extern unsigned s3c24xx_irqc_inum_get(s3c24xx_irqc_t *); 128 extern void s3c24xx_irqc_clear(s3c24xx_irqc_t *, unsigned); 129 extern void s3c24xx_irqc_src_enable(s3c24xx_irqc_t *, unsigned); 130 extern void s3c24xx_irqc_src_disable(s3c24xx_irqc_t *, unsigned); 131 extern void s3c24xx_irqc_subsrc_enable(s3c24xx_irqc_t *, unsigned); 132 extern void s3c24xx_irqc_subsrc_disable(s3c24xx_irqc_t *, unsigned); 133 122 134 #endif 123 135 -
kernel/genarch/include/drivers/s3c24xx_uart/s3c24xx_uart.h
r5a9f4d7 r571addd 38 38 #define KERN_S3C24XX_UART_H_ 39 39 40 #include <ddi/irq.h> 41 #include <console/chardev.h> 40 42 #include <typedefs.h> 41 #include <console/chardev.h>42 43 43 extern outdev_t *s3c24xx_uart_init(ioport8_t *); 44 /** S3C24xx UART I/O */ 45 typedef struct { 46 uint32_t ulcon; 47 uint32_t ucon; 48 uint32_t ufcon; 49 uint32_t umcon; 50 51 uint32_t utrstat; 52 uint32_t uerstat; 53 uint32_t ufstat; 54 uint32_t umstat; 55 56 uint32_t utxh; 57 uint32_t urxh; 58 59 uint32_t ubrdiv; 60 } s3c24xx_uart_io_t; 61 62 /** S3C24xx UART instance */ 63 typedef struct { 64 s3c24xx_uart_io_t *io; 65 indev_t *indev; 66 irq_t irq; 67 } s3c24xx_uart_t; 68 69 extern outdev_t *s3c24xx_uart_init(s3c24xx_uart_io_t *, inr_t inr); 70 extern void s3c24xx_uart_input_wire(s3c24xx_uart_t *, 71 indev_t *); 44 72 45 73 #endif -
kernel/genarch/src/drivers/s3c24xx_uart/s3c24xx_uart.c
r5a9f4d7 r571addd 40 40 #include <genarch/drivers/s3c24xx_uart/s3c24xx_uart.h> 41 41 #include <console/chardev.h> 42 #include <console/console.h> 43 #include <ddi/device.h> 42 44 #include <arch/asm.h> 43 45 #include <mm/slab.h> 44 #include <console/console.h>45 46 #include <sysinfo/sysinfo.h> 46 47 #include <str.h> 47 48 48 /* * S3C24xx UART register offsets*/49 #define S3C24XX_UTRSTAT 0x1050 #define S3C24XX_UT XH 0x2049 /* Bits in UTRSTAT register */ 50 #define S3C24XX_UTRSTAT_TX_EMPTY 0x4 51 #define S3C24XX_UTRSTAT_RDATA 0x1 51 52 52 /* Bits in UTXH register */ 53 #define S3C24XX_UTXH_TX_EMPTY 0x4 54 55 typedef struct { 56 ioport8_t *base; 57 } s3c24xx_uart_instance_t; 53 #define S3C24XX_UFSTAT_TX_FULL 0x4000 54 #define S3C24XX_UFSTAT_RX_FULL 0x0040 55 #define S3C24XX_UFSTAT_RX_COUNT 0x002f 58 56 59 57 static void s3c24xx_uart_sendb(outdev_t *dev, uint8_t byte) 60 58 { 61 s3c24xx_uart_instance_t *instance = 62 (s3c24xx_uart_instance_t *) dev->data; 63 ioport32_t *utrstat, *utxh; 59 s3c24xx_uart_t *uart = 60 (s3c24xx_uart_t *) dev->data; 64 61 65 utrstat = (ioport32_t *) (instance->base + S3C24XX_UTRSTAT); 66 utxh = (ioport32_t *) (instance->base + S3C24XX_UTXH); 67 68 /* Wait for transmitter to be empty. */ 69 while ((pio_read_32(utrstat) & S3C24XX_UTXH_TX_EMPTY) == 0) 62 /* Wait for space becoming available in Tx FIFO. */ 63 while ((pio_read_32(&uart->io->ufstat) & S3C24XX_UFSTAT_TX_FULL) != 0) 70 64 ; 71 65 72 pio_write_32( utxh, byte);66 pio_write_32(&uart->io->utxh, byte); 73 67 } 74 68 … … 86 80 } 87 81 82 static irq_ownership_t s3c24xx_uart_claim(irq_t *irq) 83 { 84 return IRQ_ACCEPT; 85 } 86 87 static void s3c24xx_uart_irq_handler(irq_t *irq) 88 { 89 s3c24xx_uart_t *uart = irq->instance; 90 91 while ((pio_read_32(&uart->io->ufstat) & S3C24XX_UFSTAT_RX_COUNT) != 0) { 92 uint32_t data = pio_read_32(&uart->io->urxh); 93 pio_read_32(&uart->io->uerstat); 94 indev_push_character(uart->indev, data & 0xff); 95 } 96 } 97 88 98 static outdev_operations_t s3c24xx_uart_ops = { 89 99 .write = s3c24xx_uart_putchar, … … 91 101 }; 92 102 93 outdev_t *s3c24xx_uart_init( ioport8_t *base)103 outdev_t *s3c24xx_uart_init(s3c24xx_uart_io_t *io, inr_t inr) 94 104 { 95 105 outdev_t *uart_dev = malloc(sizeof(outdev_t), FRAME_ATOMIC); … … 97 107 return NULL; 98 108 99 s3c24xx_uart_ instance_t *instance=100 malloc(sizeof(s3c24xx_uart_ instance_t), FRAME_ATOMIC);101 if (! instance) {109 s3c24xx_uart_t *uart = 110 malloc(sizeof(s3c24xx_uart_t), FRAME_ATOMIC); 111 if (!uart) { 102 112 free(uart_dev); 103 113 return NULL; … … 105 115 106 116 outdev_initialize("s3c24xx_uart_dev", uart_dev, &s3c24xx_uart_ops); 107 uart_dev->data = instance;117 uart_dev->data = uart; 108 118 109 instance->base = base; 119 uart->io = io; 120 uart->indev = NULL; 121 122 /* Initialize IRQ structure. */ 123 irq_initialize(&uart->irq); 124 uart->irq.devno = device_assign_devno(); 125 uart->irq.inr = inr; 126 uart->irq.claim = s3c24xx_uart_claim; 127 uart->irq.handler = s3c24xx_uart_irq_handler; 128 uart->irq.instance = uart; 129 130 /* Enable FIFO, Tx trigger level: empty, Rx trigger level: 1 byte. */ 131 pio_write_32(&uart->io->ufcon, 0x01); 132 133 /* Set RX interrupt to pulse mode */ 134 pio_write_32(&uart->io->ucon, 135 pio_read_32(&uart->io->ucon) & ~(1 << 8)); 110 136 111 137 if (!fb_exported) { … … 116 142 sysinfo_set_item_val("fb", NULL, true); 117 143 sysinfo_set_item_val("fb.kind", NULL, 3); 118 sysinfo_set_item_val("fb.address.physical", NULL, KA2PA( base));144 sysinfo_set_item_val("fb.address.physical", NULL, KA2PA(io)); 119 145 120 146 fb_exported = true; … … 124 150 } 125 151 152 void s3c24xx_uart_input_wire(s3c24xx_uart_t *uart, indev_t *indev) 153 { 154 ASSERT(uart); 155 ASSERT(indev); 156 157 uart->indev = indev; 158 irq_register(&uart->irq); 159 } 160 126 161 /** @} 127 162 */ -
uspace/Makefile
r5a9f4d7 r571addd 69 69 srv/hid/kbd \ 70 70 srv/hw/char/i8042 \ 71 srv/hw/char/s3c24xx_uart \ 71 72 srv/hw/netif/dp8390 \ 72 73 srv/net/cfg \ -
uspace/app/init/init.c
r5a9f4d7 r571addd 274 274 srv_start("/srv/cuda_adb"); 275 275 srv_start("/srv/i8042"); 276 srv_start("/srv/s3c24ser"); 276 277 srv_start("/srv/adb_ms"); 277 278 srv_start("/srv/char_ms"); -
uspace/srv/hid/kbd/Makefile
r5a9f4d7 r571addd 60 60 ifeq ($(MACHINE),gta02) 61 61 SOURCES += \ 62 port/ dummy.c \63 ctl/ pc.c62 port/chardev.c \ 63 ctl/stty.c 64 64 endif 65 65 ifeq ($(MACHINE),testarm) -
uspace/srv/hid/kbd/port/chardev.c
r5a9f4d7 r571addd 41 41 #include <kbd.h> 42 42 #include <vfs/vfs.h> 43 #include <sys/stat.h> 43 44 #include <fcntl.h> 44 45 #include <errno.h> … … 50 51 #define NAME "kbd" 51 52 53 /** List of devices to try connecting to. */ 54 static const char *in_devs[] = { 55 "/dev/char/ps2a", 56 "/dev/char/s3c24ser" 57 }; 58 59 static const int num_devs = sizeof(in_devs) / sizeof(in_devs[0]); 60 52 61 int kbd_port_init(void) 53 62 { 54 const char *input = "/dev/char/ps2a";55 63 int input_fd; 64 int i; 56 65 57 printf(NAME ": open %s\n", input); 66 input_fd = -1; 67 for (i = 0; i < num_devs; i++) { 68 struct stat s; 58 69 59 input_fd = open(input, O_RDONLY); 70 if (stat(in_devs[i], &s) == EOK) 71 break; 72 } 73 74 if (i >= num_devs) { 75 printf(NAME ": Could not find any suitable input device.\n"); 76 return -1; 77 } 78 79 input_fd = open(in_devs[i], O_RDONLY); 60 80 if (input_fd < 0) { 61 printf(NAME ": Failed opening %s (%d)\n", input, input_fd); 62 return false; 81 printf(NAME ": failed opening device %s (%d).\n", in_devs[i], 82 input_fd); 83 return -1; 63 84 } 64 85 65 86 dev_phone = fd_phone(input_fd); 66 87 if (dev_phone < 0) { 67 printf(NAME ": Failed to connectto device\n");68 return false;88 printf(NAME ": Failed connecting to device\n"); 89 return -1; 69 90 } 70 91 … … 73 94 if (ipc_connect_to_me(dev_phone, 0, 0, 0, &phonehash) != 0) { 74 95 printf(NAME ": Failed to create callback from device\n"); 75 return false;96 return -1; 76 97 } 77 98
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