Index: kernel/arch/sparc64/include/asm.h
===================================================================
--- kernel/arch/sparc64/include/asm.h	(revision 22a28a696141d62f28e48ed72d1d255ff519795c)
+++ kernel/arch/sparc64/include/asm.h	(revision 55bd76cdfcb40d7b25063357b27a0b77e7b71022)
@@ -27,5 +27,5 @@
  */
 
-/** @addtogroup sparc64	
+/** @addtogroup sparc64
  * @{
  */
@@ -43,6 +43,7 @@
 #include <arch/stack.h>
 #include <arch/barrier.h>
-
-static inline void pio_write_8(ioport8_t *port, uint8_t v)
+#include <trace.h>
+
+NO_TRACE static inline void pio_write_8(ioport8_t *port, uint8_t v)
 {
 	*port = v;
@@ -50,5 +51,5 @@
 }
 
-static inline void pio_write_16(ioport16_t *port, uint16_t v)
+NO_TRACE static inline void pio_write_16(ioport16_t *port, uint16_t v)
 {
 	*port = v;
@@ -56,5 +57,5 @@
 }
 
-static inline void pio_write_32(ioport32_t *port, uint32_t v)
+NO_TRACE static inline void pio_write_32(ioport32_t *port, uint32_t v)
 {
 	*port = v;
@@ -62,31 +63,22 @@
 }
 
-static inline uint8_t pio_read_8(ioport8_t *port)
-{
-	uint8_t rv;
-
-	rv = *port;
+NO_TRACE static inline uint8_t pio_read_8(ioport8_t *port)
+{
+	uint8_t rv = *port;
 	memory_barrier();
-
 	return rv;
 }
 
-static inline uint16_t pio_read_16(ioport16_t *port)
-{
-	uint16_t rv;
-
-	rv = *port;
+NO_TRACE static inline uint16_t pio_read_16(ioport16_t *port)
+{
+	uint16_t rv = *port;
 	memory_barrier();
-
 	return rv;
 }
 
-static inline uint32_t pio_read_32(ioport32_t *port)
-{
-	uint32_t rv;
-
-	rv = *port;
+NO_TRACE static inline uint32_t pio_read_32(ioport32_t *port)
+{
+	uint32_t rv = *port;
 	memory_barrier();
-
 	return rv;
 }
@@ -95,10 +87,14 @@
  *
  * @return Value of PSTATE register.
- */
-static inline uint64_t pstate_read(void)
-{
-	uint64_t v;
-	
-	asm volatile ("rdpr %%pstate, %0\n" : "=r" (v));
+ *
+ */
+NO_TRACE static inline uint64_t pstate_read(void)
+{
+	uint64_t v;
+	
+	asm volatile (
+		"rdpr %%pstate, %[v]\n"
+		: [v] "=r" (v)
+	);
 	
 	return v;
@@ -108,8 +104,13 @@
  *
  * @param v New value of PSTATE register.
- */
-static inline void pstate_write(uint64_t v)
-{
-	asm volatile ("wrpr %0, %1, %%pstate\n" : : "r" (v), "i" (0));
+ *
+ */
+NO_TRACE static inline void pstate_write(uint64_t v)
+{
+	asm volatile (
+		"wrpr %[v], %[zero], %%pstate\n"
+		:: [v] "r" (v),
+		   [zero] "i" (0)
+	);
 }
 
@@ -117,10 +118,14 @@
  *
  * @return Value of TICK_comapre register.
- */
-static inline uint64_t tick_compare_read(void)
-{
-	uint64_t v;
-	
-	asm volatile ("rd %%tick_cmpr, %0\n" : "=r" (v));
+ *
+ */
+NO_TRACE static inline uint64_t tick_compare_read(void)
+{
+	uint64_t v;
+	
+	asm volatile (
+		"rd %%tick_cmpr, %[v]\n"
+		: [v] "=r" (v)
+	);
 	
 	return v;
@@ -130,8 +135,13 @@
  *
  * @param v New value of TICK_comapre register.
- */
-static inline void tick_compare_write(uint64_t v)
-{
-	asm volatile ("wr %0, %1, %%tick_cmpr\n" : : "r" (v), "i" (0));
+ *
+ */
+NO_TRACE static inline void tick_compare_write(uint64_t v)
+{
+	asm volatile (
+		"wr %[v], %[zero], %%tick_cmpr\n"
+		:: [v] "r" (v),
+		   [zero] "i" (0)
+	);
 }
 
@@ -139,10 +149,14 @@
  *
  * @return Value of STICK_compare register.
- */
-static inline uint64_t stick_compare_read(void)
-{
-	uint64_t v;
-	
-	asm volatile ("rd %%asr25, %0\n" : "=r" (v));
+ *
+ */
+NO_TRACE static inline uint64_t stick_compare_read(void)
+{
+	uint64_t v;
+	
+	asm volatile (
+		"rd %%asr25, %[v]\n"
+		: [v] "=r" (v)
+	);
 	
 	return v;
@@ -152,8 +166,13 @@
  *
  * @param v New value of STICK_comapre register.
- */
-static inline void stick_compare_write(uint64_t v)
-{
-	asm volatile ("wr %0, %1, %%asr25\n" : : "r" (v), "i" (0));
+ *
+ */
+NO_TRACE static inline void stick_compare_write(uint64_t v)
+{
+	asm volatile (
+		"wr %[v], %[zero], %%asr25\n"
+		:: [v] "r" (v),
+		   [zero] "i" (0)
+	);
 }
 
@@ -161,10 +180,14 @@
  *
  * @return Value of TICK register.
- */
-static inline uint64_t tick_read(void)
-{
-	uint64_t v;
-	
-	asm volatile ("rdpr %%tick, %0\n" : "=r" (v));
+ *
+ */
+NO_TRACE static inline uint64_t tick_read(void)
+{
+	uint64_t v;
+	
+	asm volatile (
+		"rdpr %%tick, %[v]\n"
+		: [v] "=r" (v)
+	);
 	
 	return v;
@@ -174,8 +197,13 @@
  *
  * @param v New value of TICK register.
- */
-static inline void tick_write(uint64_t v)
-{
-	asm volatile ("wrpr %0, %1, %%tick\n" : : "r" (v), "i" (0));
+ *
+ */
+NO_TRACE static inline void tick_write(uint64_t v)
+{
+	asm volatile (
+		"wrpr %[v], %[zero], %%tick\n"
+		:: [v] "r" (v),
+		   [zero] "i" (0)
+	);
 }
 
@@ -183,10 +211,14 @@
  *
  * @return Value of FPRS register.
- */
-static inline uint64_t fprs_read(void)
-{
-	uint64_t v;
-	
-	asm volatile ("rd %%fprs, %0\n" : "=r" (v));
+ *
+ */
+NO_TRACE static inline uint64_t fprs_read(void)
+{
+	uint64_t v;
+	
+	asm volatile (
+		"rd %%fprs, %[v]\n"
+		: [v] "=r" (v)
+	);
 	
 	return v;
@@ -196,8 +228,13 @@
  *
  * @param v New value of FPRS register.
- */
-static inline void fprs_write(uint64_t v)
-{
-	asm volatile ("wr %0, %1, %%fprs\n" : : "r" (v), "i" (0));
+ *
+ */
+NO_TRACE static inline void fprs_write(uint64_t v)
+{
+	asm volatile (
+		"wr %[v], %[zero], %%fprs\n"
+		:: [v] "r" (v),
+		   [zero] "i" (0)
+	);
 }
 
@@ -205,11 +242,15 @@
  *
  * @return Value of SOFTINT register.
- */
-static inline uint64_t softint_read(void)
-{
-	uint64_t v;
-
-	asm volatile ("rd %%softint, %0\n" : "=r" (v));
-
+ *
+ */
+NO_TRACE static inline uint64_t softint_read(void)
+{
+	uint64_t v;
+	
+	asm volatile (
+		"rd %%softint, %[v]\n"
+		: [v] "=r" (v)
+	);
+	
 	return v;
 }
@@ -218,8 +259,13 @@
  *
  * @param v New value of SOFTINT register.
- */
-static inline void softint_write(uint64_t v)
-{
-	asm volatile ("wr %0, %1, %%softint\n" : : "r" (v), "i" (0));
+ *
+ */
+NO_TRACE static inline void softint_write(uint64_t v)
+{
+	asm volatile (
+		"wr %[v], %[zero], %%softint\n"
+		:: [v] "r" (v),
+		   [zero] "i" (0)
+	);
 }
 
@@ -229,8 +275,13 @@
  *
  * @param v New value of CLEAR_SOFTINT register.
- */
-static inline void clear_softint_write(uint64_t v)
-{
-	asm volatile ("wr %0, %1, %%clear_softint\n" : : "r" (v), "i" (0));
+ *
+ */
+NO_TRACE static inline void clear_softint_write(uint64_t v)
+{
+	asm volatile (
+		"wr %[v], %[zero], %%clear_softint\n"
+		:: [v] "r" (v),
+		   [zero] "i" (0)
+	);
 }
 
@@ -240,8 +291,13 @@
  *
  * @param v New value of SET_SOFTINT register.
- */
-static inline void set_softint_write(uint64_t v)
-{
-	asm volatile ("wr %0, %1, %%set_softint\n" : : "r" (v), "i" (0));
+ *
+ */
+NO_TRACE static inline void set_softint_write(uint64_t v)
+{
+	asm volatile (
+		"wr %[v], %[zero], %%set_softint\n"
+		:: [v] "r" (v),
+		   [zero] "i" (0)
+	);
 }
 
@@ -252,10 +308,10 @@
  *
  * @return Old interrupt priority level.
- */
-static inline ipl_t interrupts_enable(void) {
+ *
+ */
+NO_TRACE static inline ipl_t interrupts_enable(void) {
 	pstate_reg_t pstate;
-	uint64_t value;
-	
-	value = pstate_read();
+	uint64_t value = pstate_read();
+	
 	pstate.value = value;
 	pstate.ie = true;
@@ -271,10 +327,10 @@
  *
  * @return Old interrupt priority level.
- */
-static inline ipl_t interrupts_disable(void) {
+ *
+ */
+NO_TRACE static inline ipl_t interrupts_disable(void) {
 	pstate_reg_t pstate;
-	uint64_t value;
-	
-	value = pstate_read();
+	uint64_t value = pstate_read();
+	
 	pstate.value = value;
 	pstate.ie = false;
@@ -289,6 +345,7 @@
  *
  * @param ipl Saved interrupt priority level.
- */
-static inline void interrupts_restore(ipl_t ipl) {
+ *
+ */
+NO_TRACE static inline void interrupts_restore(ipl_t ipl) {
 	pstate_reg_t pstate;
 	
@@ -303,6 +360,7 @@
  *
  * @return Current interrupt priority level.
- */
-static inline ipl_t interrupts_read(void) {
+ *
+ */
+NO_TRACE static inline ipl_t interrupts_read(void) {
 	return (ipl_t) pstate_read();
 }
@@ -313,8 +371,8 @@
  *
  */
-static inline bool interrupts_disabled(void)
+NO_TRACE static inline bool interrupts_disabled(void)
 {
 	pstate_reg_t pstate;
-
+	
 	pstate.value = pstate_read();
 	return !pstate.ie;
@@ -326,10 +384,15 @@
  * The stack is assumed to be STACK_SIZE bytes long.
  * The stack must start on page boundary.
- */
-static inline uintptr_t get_stack_base(void)
+ *
+ */
+NO_TRACE static inline uintptr_t get_stack_base(void)
 {
 	uintptr_t unbiased_sp;
 	
-	asm volatile ("add %%sp, %1, %0\n" : "=r" (unbiased_sp) : "i" (STACK_BIAS));
+	asm volatile (
+		"add %%sp, %[stack_bias], %[unbiased_sp]\n"
+		: [unbiased_sp] "=r" (unbiased_sp)
+		: [stack_bias] "i" (STACK_BIAS)
+	);
 	
 	return ALIGN_DOWN(unbiased_sp, STACK_SIZE);
@@ -339,10 +402,14 @@
  *
  * @return Value of VER register.
- */
-static inline uint64_t ver_read(void)
-{
-	uint64_t v;
-	
-	asm volatile ("rdpr %%ver, %0\n" : "=r" (v));
+ *
+ */
+NO_TRACE static inline uint64_t ver_read(void)
+{
+	uint64_t v;
+	
+	asm volatile (
+		"rdpr %%ver, %[v]\n"
+		: [v] "=r" (v)
+	);
 	
 	return v;
@@ -352,10 +419,14 @@
  *
  * @return Current value in TPC.
- */
-static inline uint64_t tpc_read(void)
-{
-	uint64_t v;
-	
-	asm volatile ("rdpr %%tpc, %0\n" : "=r" (v));
+ *
+ */
+NO_TRACE static inline uint64_t tpc_read(void)
+{
+	uint64_t v;
+	
+	asm volatile (
+		"rdpr %%tpc, %[v]\n"
+		: [v] "=r" (v)
+	);
 	
 	return v;
@@ -365,10 +436,14 @@
  *
  * @return Current value in TL.
- */
-static inline uint64_t tl_read(void)
-{
-	uint64_t v;
-	
-	asm volatile ("rdpr %%tl, %0\n" : "=r" (v));
+ *
+ */
+NO_TRACE static inline uint64_t tl_read(void)
+{
+	uint64_t v;
+	
+	asm volatile (
+		"rdpr %%tl, %[v]\n"
+		: [v] "=r" (v)
+	);
 	
 	return v;
@@ -378,10 +453,14 @@
  *
  * @return Current value in TBA.
- */
-static inline uint64_t tba_read(void)
-{
-	uint64_t v;
-	
-	asm volatile ("rdpr %%tba, %0\n" : "=r" (v));
+ *
+ */
+NO_TRACE static inline uint64_t tba_read(void)
+{
+	uint64_t v;
+	
+	asm volatile (
+		"rdpr %%tba, %[v]\n"
+		: [v] "=r" (v)
+	);
 	
 	return v;
@@ -391,8 +470,13 @@
  *
  * @param v New value of TBA.
- */
-static inline void tba_write(uint64_t v)
-{
-	asm volatile ("wrpr %0, %1, %%tba\n" : : "r" (v), "i" (0));
+ *
+ */
+NO_TRACE static inline void tba_write(uint64_t v)
+{
+	asm volatile (
+		"wrpr %[v], %[zero], %%tba\n"
+		:: [v] "r" (v),
+		   [zero] "i" (0)
+	);
 }
 
@@ -400,13 +484,20 @@
  *
  * @param asi ASI determining the alternate space.
- * @param va Virtual address within the ASI.
- *
- * @return Value read from the virtual address in the specified address space.
- */
-static inline uint64_t asi_u64_read(asi_t asi, uintptr_t va)
-{
-	uint64_t v;
-	
-	asm volatile ("ldxa [%1] %2, %0\n" : "=r" (v) : "r" (va), "i" ((unsigned) asi));
+ * @param va  Virtual address within the ASI.
+ *
+ * @return Value read from the virtual address in
+ *         the specified address space.
+ *
+ */
+NO_TRACE static inline uint64_t asi_u64_read(asi_t asi, uintptr_t va)
+{
+	uint64_t v;
+	
+	asm volatile (
+		"ldxa [%[va]] %[asi], %[v]\n"
+		: [v] "=r" (v)
+		: [va] "r" (va),
+		  [asi] "i" ((unsigned int) asi)
+	);
 	
 	return v;
@@ -416,14 +507,21 @@
  *
  * @param asi ASI determining the alternate space.
- * @param va Virtual address within the ASI.
- * @param v Value to be written.
- */
-static inline void asi_u64_write(asi_t asi, uintptr_t va, uint64_t v)
-{
-	asm volatile ("stxa %0, [%1] %2\n" : :  "r" (v), "r" (va), "i" ((unsigned) asi) : "memory");
+ * @param va  Virtual address within the ASI.
+ * @param v   Value to be written.
+ *
+ */
+NO_TRACE static inline void asi_u64_write(asi_t asi, uintptr_t va, uint64_t v)
+{
+	asm volatile (
+		"stxa %[v], [%[va]] %[asi]\n"
+		:: [v] "r" (v),
+		   [va] "r" (va),
+		   [asi] "i" ((unsigned int) asi)
+		: "memory"
+	);
 }
 
 /** Flush all valid register windows to memory. */
-static inline void flushw(void)
+NO_TRACE static inline void flushw(void)
 {
 	asm volatile ("flushw\n");
@@ -431,5 +529,5 @@
 
 /** Switch to nucleus by setting TL to 1. */
-static inline void nucleus_enter(void)
+NO_TRACE static inline void nucleus_enter(void)
 {
 	asm volatile ("wrpr %g0, 1, %tl\n");
@@ -437,5 +535,5 @@
 
 /** Switch from nucleus by setting TL to 0. */
-static inline void nucleus_leave(void)
+NO_TRACE static inline void nucleus_leave(void)
 {
 	asm volatile ("wrpr %g0, %g0, %tl\n");
Index: kernel/arch/sparc64/include/atomic.h
===================================================================
--- kernel/arch/sparc64/include/atomic.h	(revision 22a28a696141d62f28e48ed72d1d255ff519795c)
+++ kernel/arch/sparc64/include/atomic.h	(revision 55bd76cdfcb40d7b25063357b27a0b77e7b71022)
@@ -39,4 +39,5 @@
 #include <typedefs.h>
 #include <preemption.h>
+#include <trace.h>
 
 /** Atomic add operation.
@@ -50,5 +51,6 @@
  *
  */
-static inline atomic_count_t atomic_add(atomic_t *val, atomic_count_t i)
+NO_TRACE static inline atomic_count_t atomic_add(atomic_t *val,
+    atomic_count_t i)
 {
 	atomic_count_t a;
@@ -72,35 +74,35 @@
 }
 
-static inline atomic_count_t atomic_preinc(atomic_t *val)
+NO_TRACE static inline atomic_count_t atomic_preinc(atomic_t *val)
 {
 	return atomic_add(val, 1) + 1;
 }
 
-static inline atomic_count_t atomic_postinc(atomic_t *val)
+NO_TRACE static inline atomic_count_t atomic_postinc(atomic_t *val)
 {
 	return atomic_add(val, 1);
 }
 
-static inline atomic_count_t atomic_predec(atomic_t *val)
+NO_TRACE static inline atomic_count_t atomic_predec(atomic_t *val)
 {
 	return atomic_add(val, -1) - 1;
 }
 
-static inline atomic_count_t atomic_postdec(atomic_t *val)
+NO_TRACE static inline atomic_count_t atomic_postdec(atomic_t *val)
 {
 	return atomic_add(val, -1);
 }
 
-static inline void atomic_inc(atomic_t *val)
+NO_TRACE static inline void atomic_inc(atomic_t *val)
 {
 	(void) atomic_add(val, 1);
 }
 
-static inline void atomic_dec(atomic_t *val)
+NO_TRACE static inline void atomic_dec(atomic_t *val)
 {
 	(void) atomic_add(val, -1);
 }
 
-static inline atomic_count_t test_and_set(atomic_t *val)
+NO_TRACE static inline atomic_count_t test_and_set(atomic_t *val)
 {
 	atomic_count_t v = 1;
@@ -117,5 +119,5 @@
 }
 
-static inline void atomic_lock_arch(atomic_t *val)
+NO_TRACE static inline void atomic_lock_arch(atomic_t *val)
 {
 	atomic_count_t tmp1 = 1;
Index: kernel/arch/sparc64/include/barrier.h
===================================================================
--- kernel/arch/sparc64/include/barrier.h	(revision 22a28a696141d62f28e48ed72d1d255ff519795c)
+++ kernel/arch/sparc64/include/barrier.h	(revision 55bd76cdfcb40d7b25063357b27a0b77e7b71022)
@@ -27,5 +27,5 @@
  */
 
-/** @addtogroup sparc64	
+/** @addtogroup sparc64
  * @{
  */
@@ -36,8 +36,14 @@
 #define KERN_sparc64_BARRIER_H_
 
+#include <trace.h>
+
 #ifdef KERNEL
+
 #include <typedefs.h>
+
 #else
+
 #include <stdint.h>
+
 #endif
 
@@ -45,31 +51,47 @@
  * Our critical section barriers are prepared for the weakest RMO memory model.
  */
-#define CS_ENTER_BARRIER() 				\
-	asm volatile (					\
-		"membar #LoadLoad | #LoadStore\n"	\
-		::: "memory"				\
-	)
-#define CS_LEAVE_BARRIER()				\
-	asm volatile ( 					\
-		"membar #StoreStore\n"			\
-		"membar #LoadStore\n"			\
-		::: "memory"				\
+#define CS_ENTER_BARRIER() \
+	asm volatile ( \
+		"membar #LoadLoad | #LoadStore\n" \
+		::: "memory" \
 	)
 
-#define memory_barrier()	\
-	asm volatile ("membar #LoadLoad | #StoreStore\n" ::: "memory")
-#define read_barrier()		\
-	asm volatile ("membar #LoadLoad\n" ::: "memory")
-#define write_barrier()		\
-	asm volatile ("membar #StoreStore\n" ::: "memory")
+#define CS_LEAVE_BARRIER() \
+	asm volatile ( \
+		"membar #StoreStore\n" \
+		"membar #LoadStore\n" \
+		::: "memory" \
+	)
 
-#define flush(a)		\
-	asm volatile ("flush %0\n" :: "r" ((a)) : "memory")
+#define memory_barrier() \
+	asm volatile ( \
+		"membar #LoadLoad | #StoreStore\n" \
+		::: "memory" \
+	)
+
+#define read_barrier() \
+	asm volatile ( \
+		"membar #LoadLoad\n" \
+		::: "memory" \
+	)
+
+#define write_barrier() \
+	asm volatile ( \
+		"membar #StoreStore\n" \
+		::: "memory" \
+	)
+
+#define flush(a) \
+	asm volatile ( \
+		"flush %[reg]\n" \
+		:: [reg] "r" ((a)) \
+		: "memory" \
+	)
 
 /** Flush Instruction pipeline. */
-static inline void flush_pipeline(void)
+NO_TRACE static inline void flush_pipeline(void)
 {
 	uint64_t pc;
-
+	
 	/*
 	 * The FLUSH instruction takes address parameter.
@@ -80,51 +102,56 @@
 	 * the %pc register will always be in the range mapped by
 	 * DTLB.
+	 *
 	 */
-	 
-        asm volatile (
-		"rd %%pc, %0\n"
-		"flush %0\n"
-		: "=&r" (pc)
+	
+	asm volatile (
+		"rd %%pc, %[pc]\n"
+		"flush %[pc]\n"
+		: [pc] "=&r" (pc)
 	);
 }
 
 /** Memory Barrier instruction. */
-static inline void membar(void)
+NO_TRACE static inline void membar(void)
 {
-	asm volatile ("membar #Sync\n");
+	asm volatile (
+		"membar #Sync\n"
+	);
 }
 
 #if defined (US)
 
-#define smc_coherence(a)	\
-{				\
-	write_barrier();	\
-	flush((a));		\
-}
+#define FLUSH_INVAL_MIN  4
 
-#define FLUSH_INVAL_MIN		4
-#define smc_coherence_block(a, l)			\
-{							\
-	unsigned long i;				\
-	write_barrier();				\
-	for (i = 0; i < (l); i += FLUSH_INVAL_MIN)	\
-		flush((void *)(a) + i);			\
-}
+#define smc_coherence(a) \
+	do { \
+		write_barrier(); \
+		flush((a)); \
+	} while (0)
+
+#define smc_coherence_block(a, l) \
+	do { \
+		unsigned long i; \
+		write_barrier(); \
+		\
+		for (i = 0; i < (l); i += FLUSH_INVAL_MIN) \
+			flush((void *)(a) + i); \
+	} while (0)
 
 #elif defined (US3)
 
-#define smc_coherence(a)	\
-{				\
-	write_barrier();	\
-	flush_pipeline();	\
-}
+#define smc_coherence(a) \
+	do { \
+		write_barrier(); \
+		flush_pipeline(); \
+	} while (0)
 
-#define smc_coherence_block(a, l)	\
-{					\
-	write_barrier();		\
-	flush_pipeline();		\
-}
+#define smc_coherence_block(a, l) \
+	do { \
+		write_barrier(); \
+		flush_pipeline(); \
+	} while (0)
 
-#endif	/* defined(US3) */
+#endif  /* defined(US3) */
 
 #endif
Index: kernel/arch/sparc64/include/cycle.h
===================================================================
--- kernel/arch/sparc64/include/cycle.h	(revision 22a28a696141d62f28e48ed72d1d255ff519795c)
+++ kernel/arch/sparc64/include/cycle.h	(revision 55bd76cdfcb40d7b25063357b27a0b77e7b71022)
@@ -36,7 +36,8 @@
 #define KERN_sparc64_CYCLE_H_
 
-#include <arch/asm.h> 
+#include <arch/asm.h>
+#include <trace.h>
 
-static inline uint64_t get_cycle(void)
+NO_TRACE static inline uint64_t get_cycle(void)
 {
 	return tick_read();
Index: kernel/arch/sparc64/include/faddr.h
===================================================================
--- kernel/arch/sparc64/include/faddr.h	(revision 22a28a696141d62f28e48ed72d1d255ff519795c)
+++ kernel/arch/sparc64/include/faddr.h	(revision 55bd76cdfcb40d7b25063357b27a0b77e7b71022)
@@ -27,5 +27,5 @@
  */
 
-/** @addtogroup sparc64	
+/** @addtogroup sparc64
  * @{
  */
@@ -38,5 +38,5 @@
 #include <typedefs.h>
 
-#define FADDR(fptr)		((uintptr_t) (fptr))
+#define FADDR(fptr)  ((uintptr_t) (fptr))
 
 #endif
Index: kernel/arch/sparc64/include/interrupt.h
===================================================================
--- kernel/arch/sparc64/include/interrupt.h	(revision 22a28a696141d62f28e48ed72d1d255ff519795c)
+++ kernel/arch/sparc64/include/interrupt.h	(revision 55bd76cdfcb40d7b25063357b27a0b77e7b71022)
@@ -39,39 +39,43 @@
 #include <typedefs.h>
 #include <arch/regdef.h>
+#include <trace.h>
 
-#define IVT_ITEMS 	15
-#define IVT_FIRST	1
+#define IVT_ITEMS  15
+#define IVT_FIRST  1
 
 /* This needs to be defined for inter-architecture API portability. */
-#define VECTOR_TLB_SHOOTDOWN_IPI	0
+#define VECTOR_TLB_SHOOTDOWN_IPI  0
 
 enum {
 	IPI_TLB_SHOOTDOWN = VECTOR_TLB_SHOOTDOWN_IPI
-};		
+};
 
 typedef struct istate {
-	uint64_t	tnpc;
-	uint64_t	tpc;
-	uint64_t	tstate;
+	uint64_t tnpc;
+	uint64_t tpc;
+	uint64_t tstate;
 } istate_t;
 
-static inline void istate_set_retaddr(istate_t *istate, uintptr_t retaddr)
+NO_TRACE static inline void istate_set_retaddr(istate_t *istate,
+    uintptr_t retaddr)
 {
 	istate->tpc = retaddr;
 }
 
-static inline int istate_from_uspace(istate_t *istate)
+NO_TRACE static inline int istate_from_uspace(istate_t *istate)
 {
 	return !(istate->tstate & TSTATE_PRIV_BIT);
 }
 
-static inline unative_t istate_get_pc(istate_t *istate)
+NO_TRACE static inline unative_t istate_get_pc(istate_t *istate)
 {
 	return istate->tpc;
 }
 
-static inline unative_t istate_get_fp(istate_t *istate)
+NO_TRACE static inline unative_t istate_get_fp(istate_t *istate)
 {
-	return 0;	/* TODO */
+	/* TODO */
+	
+	return 0;
 }
 
Index: kernel/arch/sparc64/include/mm/as.h
===================================================================
--- kernel/arch/sparc64/include/mm/as.h	(revision 22a28a696141d62f28e48ed72d1d255ff519795c)
+++ kernel/arch/sparc64/include/mm/as.h	(revision 55bd76cdfcb40d7b25063357b27a0b77e7b71022)
@@ -27,5 +27,5 @@
  */
 
-/** @addtogroup sparc64mm	
+/** @addtogroup sparc64mm
  * @{
  */
@@ -37,7 +37,11 @@
 
 #if defined (SUN4U)
+
 #include <arch/mm/sun4u/as.h>
+
 #elif defined (SUN4V)
+
 #include <arch/mm/sun4v/as.h>
+
 #endif
 
Index: kernel/arch/sparc64/include/mm/frame.h
===================================================================
--- kernel/arch/sparc64/include/mm/frame.h	(revision 22a28a696141d62f28e48ed72d1d255ff519795c)
+++ kernel/arch/sparc64/include/mm/frame.h	(revision 55bd76cdfcb40d7b25063357b27a0b77e7b71022)
@@ -27,5 +27,5 @@
  */
 
-/** @addtogroup sparc64mm	
+/** @addtogroup sparc64mm
  * @{
  */
@@ -37,7 +37,11 @@
 
 #if defined (SUN4U)
+
 #include <arch/mm/sun4u/frame.h>
+
 #elif defined (SUN4V)
+
 #include <arch/mm/sun4v/frame.h>
+
 #endif
 
Index: kernel/arch/sparc64/include/mm/sun4u/tlb.h
===================================================================
--- kernel/arch/sparc64/include/mm/sun4u/tlb.h	(revision 22a28a696141d62f28e48ed72d1d255ff519795c)
+++ kernel/arch/sparc64/include/mm/sun4u/tlb.h	(revision 55bd76cdfcb40d7b25063357b27a0b77e7b71022)
@@ -100,4 +100,5 @@
 #include <arch/barrier.h>
 #include <typedefs.h>
+#include <trace.h>
 #include <arch/register.h>
 #include <arch/cpu.h>
@@ -242,5 +243,5 @@
  * Determine the number of entries in the DMMU's small TLB. 
  */
-static inline uint16_t tlb_dsmall_size(void)
+NO_TRACE static inline uint16_t tlb_dsmall_size(void)
 {
 	return 16;
@@ -250,5 +251,5 @@
  * Determine the number of entries in each DMMU's big TLB. 
  */
-static inline uint16_t tlb_dbig_size(void)
+NO_TRACE static inline uint16_t tlb_dbig_size(void)
 {
 	return 512;
@@ -258,5 +259,5 @@
  * Determine the number of entries in the IMMU's small TLB. 
  */
-static inline uint16_t tlb_ismall_size(void)
+NO_TRACE static inline uint16_t tlb_ismall_size(void)
 {
 	return 16;
@@ -266,5 +267,5 @@
  * Determine the number of entries in the IMMU's big TLB. 
  */
-static inline uint16_t tlb_ibig_size(void)
+NO_TRACE static inline uint16_t tlb_ibig_size(void)
 {
 	if (((ver_reg_t) ver_read()).impl == IMPL_ULTRASPARCIV_PLUS)
@@ -280,5 +281,5 @@
  * @return		Current value of Primary Context Register.
  */
-static inline uint64_t mmu_primary_context_read(void)
+NO_TRACE static inline uint64_t mmu_primary_context_read(void)
 {
 	return asi_u64_read(ASI_DMMU, VA_PRIMARY_CONTEXT_REG);
@@ -289,5 +290,5 @@
  * @param v		New value of Primary Context Register.
  */
-static inline void mmu_primary_context_write(uint64_t v)
+NO_TRACE static inline void mmu_primary_context_write(uint64_t v)
 {
 	asi_u64_write(ASI_DMMU, VA_PRIMARY_CONTEXT_REG, v);
@@ -299,5 +300,5 @@
  * @return		Current value of Secondary Context Register.
  */
-static inline uint64_t mmu_secondary_context_read(void)
+NO_TRACE static inline uint64_t mmu_secondary_context_read(void)
 {
 	return asi_u64_read(ASI_DMMU, VA_SECONDARY_CONTEXT_REG);
@@ -308,5 +309,5 @@
  * @param v		New value of Primary Context Register.
  */
-static inline void mmu_secondary_context_write(uint64_t v)
+NO_TRACE static inline void mmu_secondary_context_write(uint64_t v)
 {
 	asi_u64_write(ASI_DMMU, VA_SECONDARY_CONTEXT_REG, v);
@@ -323,5 +324,5 @@
  * 			Register.
  */
-static inline uint64_t itlb_data_access_read(size_t entry)
+NO_TRACE static inline uint64_t itlb_data_access_read(size_t entry)
 {
 	itlb_data_access_addr_t reg;
@@ -337,5 +338,5 @@
  * @param value		Value to be written.
  */
-static inline void itlb_data_access_write(size_t entry, uint64_t value)
+NO_TRACE static inline void itlb_data_access_write(size_t entry, uint64_t value)
 {
 	itlb_data_access_addr_t reg;
@@ -354,5 +355,5 @@
  * 			Register.
  */
-static inline uint64_t dtlb_data_access_read(size_t entry)
+NO_TRACE static inline uint64_t dtlb_data_access_read(size_t entry)
 {
 	dtlb_data_access_addr_t reg;
@@ -368,5 +369,5 @@
  * @param value		Value to be written.
  */
-static inline void dtlb_data_access_write(size_t entry, uint64_t value)
+NO_TRACE static inline void dtlb_data_access_write(size_t entry, uint64_t value)
 {
 	dtlb_data_access_addr_t reg;
@@ -384,5 +385,5 @@
  * @return		Current value of specified IMMU TLB Tag Read Register.
  */
-static inline uint64_t itlb_tag_read_read(size_t entry)
+NO_TRACE static inline uint64_t itlb_tag_read_read(size_t entry)
 {
 	itlb_tag_read_addr_t tag;
@@ -399,5 +400,5 @@
  * @return		Current value of specified DMMU TLB Tag Read Register.
  */
-static inline uint64_t dtlb_tag_read_read(size_t entry)
+NO_TRACE static inline uint64_t dtlb_tag_read_read(size_t entry)
 {
 	dtlb_tag_read_addr_t tag;
@@ -419,5 +420,5 @@
  * 			Register.
  */
-static inline uint64_t itlb_data_access_read(int tlb, size_t entry)
+NO_TRACE static inline uint64_t itlb_data_access_read(int tlb, size_t entry)
 {
 	itlb_data_access_addr_t reg;
@@ -434,5 +435,5 @@
  * @param value		Value to be written.
  */
-static inline void itlb_data_access_write(int tlb, size_t entry,
+NO_TRACE static inline void itlb_data_access_write(int tlb, size_t entry,
 	uint64_t value)
 {
@@ -454,5 +455,5 @@
  * 			Register.
  */
-static inline uint64_t dtlb_data_access_read(int tlb, size_t entry)
+NO_TRACE static inline uint64_t dtlb_data_access_read(int tlb, size_t entry)
 {
 	dtlb_data_access_addr_t reg;
@@ -470,5 +471,5 @@
  * @param value		Value to be written.
  */
-static inline void dtlb_data_access_write(int tlb, size_t entry,
+NO_TRACE static inline void dtlb_data_access_write(int tlb, size_t entry,
 	uint64_t value)
 {
@@ -489,5 +490,5 @@
  * @return		Current value of specified IMMU TLB Tag Read Register.
  */
-static inline uint64_t itlb_tag_read_read(int tlb, size_t entry)
+NO_TRACE static inline uint64_t itlb_tag_read_read(int tlb, size_t entry)
 {
 	itlb_tag_read_addr_t tag;
@@ -506,5 +507,5 @@
  * @return		Current value of specified DMMU TLB Tag Read Register.
  */
-static inline uint64_t dtlb_tag_read_read(int tlb, size_t entry)
+NO_TRACE static inline uint64_t dtlb_tag_read_read(int tlb, size_t entry)
 {
 	dtlb_tag_read_addr_t tag;
@@ -523,5 +524,5 @@
  * @param v		Value to be written.
  */
-static inline void itlb_tag_access_write(uint64_t v)
+NO_TRACE static inline void itlb_tag_access_write(uint64_t v)
 {
 	asi_u64_write(ASI_IMMU, VA_IMMU_TAG_ACCESS, v);
@@ -533,5 +534,5 @@
  * @return		Current value of IMMU TLB Tag Access Register.
  */
-static inline uint64_t itlb_tag_access_read(void)
+NO_TRACE static inline uint64_t itlb_tag_access_read(void)
 {
 	return asi_u64_read(ASI_IMMU, VA_IMMU_TAG_ACCESS);
@@ -542,5 +543,5 @@
  * @param v		Value to be written.
  */
-static inline void dtlb_tag_access_write(uint64_t v)
+NO_TRACE static inline void dtlb_tag_access_write(uint64_t v)
 {
 	asi_u64_write(ASI_DMMU, VA_DMMU_TAG_ACCESS, v);
@@ -552,5 +553,5 @@
  * @return 		Current value of DMMU TLB Tag Access Register.
  */
-static inline uint64_t dtlb_tag_access_read(void)
+NO_TRACE static inline uint64_t dtlb_tag_access_read(void)
 {
 	return asi_u64_read(ASI_DMMU, VA_DMMU_TAG_ACCESS);
@@ -562,5 +563,5 @@
  * @param v		Value to be written.
  */
-static inline void itlb_data_in_write(uint64_t v)
+NO_TRACE static inline void itlb_data_in_write(uint64_t v)
 {
 	asi_u64_write(ASI_ITLB_DATA_IN_REG, 0, v);
@@ -572,5 +573,5 @@
  * @param v		Value to be written.
  */
-static inline void dtlb_data_in_write(uint64_t v)
+NO_TRACE static inline void dtlb_data_in_write(uint64_t v)
 {
 	asi_u64_write(ASI_DTLB_DATA_IN_REG, 0, v);
@@ -582,5 +583,5 @@
  * @return		Current content of I-SFSR register.
  */
-static inline uint64_t itlb_sfsr_read(void)
+NO_TRACE static inline uint64_t itlb_sfsr_read(void)
 {
 	return asi_u64_read(ASI_IMMU, VA_IMMU_SFSR);
@@ -591,5 +592,5 @@
  * @param v		New value of I-SFSR register.
  */
-static inline void itlb_sfsr_write(uint64_t v)
+NO_TRACE static inline void itlb_sfsr_write(uint64_t v)
 {
 	asi_u64_write(ASI_IMMU, VA_IMMU_SFSR, v);
@@ -601,5 +602,5 @@
  * @return		Current content of D-SFSR register.
  */
-static inline uint64_t dtlb_sfsr_read(void)
+NO_TRACE static inline uint64_t dtlb_sfsr_read(void)
 {
 	return asi_u64_read(ASI_DMMU, VA_DMMU_SFSR);
@@ -610,5 +611,5 @@
  * @param v		New value of D-SFSR register.
  */
-static inline void dtlb_sfsr_write(uint64_t v)
+NO_TRACE static inline void dtlb_sfsr_write(uint64_t v)
 {
 	asi_u64_write(ASI_DMMU, VA_DMMU_SFSR, v);
@@ -620,5 +621,5 @@
  * @return		Current content of D-SFAR register.
  */
-static inline uint64_t dtlb_sfar_read(void)
+NO_TRACE static inline uint64_t dtlb_sfar_read(void)
 {
 	return asi_u64_read(ASI_DMMU, VA_DMMU_SFAR);
@@ -633,5 +634,5 @@
  * @param page		Address which is on the page to be demapped.
  */
-static inline void itlb_demap(int type, int context_encoding, uintptr_t page)
+NO_TRACE static inline void itlb_demap(int type, int context_encoding, uintptr_t page)
 {
 	tlb_demap_addr_t da;
@@ -659,5 +660,5 @@
  * @param page		Address which is on the page to be demapped.
  */
-static inline void dtlb_demap(int type, int context_encoding, uintptr_t page)
+NO_TRACE static inline void dtlb_demap(int type, int context_encoding, uintptr_t page)
 {
 	tlb_demap_addr_t da;
Index: kernel/arch/sparc64/include/mm/sun4v/tlb.h
===================================================================
--- kernel/arch/sparc64/include/mm/sun4v/tlb.h	(revision 22a28a696141d62f28e48ed72d1d255ff519795c)
+++ kernel/arch/sparc64/include/mm/sun4v/tlb.h	(revision 55bd76cdfcb40d7b25063357b27a0b77e7b71022)
@@ -43,5 +43,5 @@
 
 #include <arch/mm/tte.h>
-#include <print.h>
+#include <trace.h>
 #include <arch/mm/mmu.h>
 #include <arch/mm/page.h>
@@ -88,32 +88,32 @@
  * @return	Current value of Primary Context Register.
  */
-static inline uint64_t mmu_primary_context_read(void)
+NO_TRACE static inline uint64_t mmu_primary_context_read(void)
 {
 	return asi_u64_read(ASI_PRIMARY_CONTEXT_REG, VA_PRIMARY_CONTEXT_REG);
 }
- 
+
 /** Write MMU Primary Context Register.
  *
  * @param v	New value of Primary Context Register.
  */
-static inline void mmu_primary_context_write(uint64_t v)
+NO_TRACE static inline void mmu_primary_context_write(uint64_t v)
 {
 	asi_u64_write(ASI_PRIMARY_CONTEXT_REG, VA_PRIMARY_CONTEXT_REG, v);
 }
- 
+
 /** Read MMU Secondary Context Register.
  *
  * @return	Current value of Secondary Context Register.
  */
-static inline uint64_t mmu_secondary_context_read(void)
+NO_TRACE static inline uint64_t mmu_secondary_context_read(void)
 {
 	return asi_u64_read(ASI_SECONDARY_CONTEXT_REG, VA_SECONDARY_CONTEXT_REG);
 }
- 
+
 /** Write MMU Secondary Context Register.
  *
  * @param v	New value of Secondary Context Register.
  */
-static inline void mmu_secondary_context_write(uint64_t v)
+NO_TRACE static inline void mmu_secondary_context_write(uint64_t v)
 {
 	asi_u64_write(ASI_SECONDARY_CONTEXT_REG, VA_SECONDARY_CONTEXT_REG, v);
@@ -126,5 +126,5 @@
  * @param mmu_flag	MMU_FLAG_DTLB, MMU_FLAG_ITLB or a combination of both
  */
-static inline void mmu_demap_ctx(int context, int mmu_flag) {
+NO_TRACE static inline void mmu_demap_ctx(int context, int mmu_flag) {
 	__hypercall_fast4(MMU_DEMAP_CTX, 0, 0, context, mmu_flag);
 }
@@ -137,5 +137,5 @@
  * @param mmu_flag	MMU_FLAG_DTLB, MMU_FLAG_ITLB or a combination of both
  */
-static inline void mmu_demap_page(uintptr_t vaddr, int context, int mmu_flag) {
+NO_TRACE static inline void mmu_demap_page(uintptr_t vaddr, int context, int mmu_flag) {
 	__hypercall_fast5(MMU_DEMAP_PAGE, 0, 0, vaddr, context, mmu_flag);
 }
Index: kernel/arch/sparc64/include/mm/tlb.h
===================================================================
--- kernel/arch/sparc64/include/mm/tlb.h	(revision 22a28a696141d62f28e48ed72d1d255ff519795c)
+++ kernel/arch/sparc64/include/mm/tlb.h	(revision 55bd76cdfcb40d7b25063357b27a0b77e7b71022)
@@ -27,5 +27,5 @@
  */
 
-/** @addtogroup sparc64mm	
+/** @addtogroup sparc64mm
  * @{
  */
@@ -36,9 +36,12 @@
 #define KERN_sparc64_TLB_H_
 
+#if defined (SUN4U)
 
-#if defined (SUN4U)
 #include <arch/mm/sun4u/tlb.h>
+
 #elif defined (SUN4V)
+
 #include <arch/mm/sun4v/tlb.h>
+
 #endif
 
Index: kernel/arch/sparc64/include/sun4u/asm.h
===================================================================
--- kernel/arch/sparc64/include/sun4u/asm.h	(revision 22a28a696141d62f28e48ed72d1d255ff519795c)
+++ kernel/arch/sparc64/include/sun4u/asm.h	(revision 55bd76cdfcb40d7b25063357b27a0b77e7b71022)
@@ -27,5 +27,5 @@
  */
 
-/** @addtogroup sparc64	
+/** @addtogroup sparc64
  * @{
  */
@@ -36,22 +36,27 @@
 #define KERN_sparc64_sun4u_ASM_H_
 
-extern uint64_t read_from_ag_g7(void);
-extern void write_to_ag_g6(uint64_t val);
-extern void write_to_ag_g7(uint64_t val);
-extern void write_to_ig_g6(uint64_t val);
-
+#include <trace.h>
 
 /** Read Version Register.
  *
  * @return Value of VER register.
+ *
  */
-static inline uint64_t ver_read(void)
+NO_TRACE static inline uint64_t ver_read(void)
 {
 	uint64_t v;
 	
-	asm volatile ("rdpr %%ver, %0\n" : "=r" (v));
+	asm volatile (
+		"rdpr %%ver, %[v]\n"
+		: [v] "=r" (v)
+	);
 	
 	return v;
 }
+
+extern uint64_t read_from_ag_g7(void);
+extern void write_to_ag_g6(uint64_t);
+extern void write_to_ag_g7(uint64_t);
+extern void write_to_ig_g6(uint64_t);
 
 #endif
Index: kernel/arch/sparc64/include/sun4u/cpu.h
===================================================================
--- kernel/arch/sparc64/include/sun4u/cpu.h	(revision 22a28a696141d62f28e48ed72d1d255ff519795c)
+++ kernel/arch/sparc64/include/sun4u/cpu.h	(revision 55bd76cdfcb40d7b25063357b27a0b77e7b71022)
@@ -36,19 +36,19 @@
 #define KERN_sparc64_sun4u_CPU_H_
 
-#define MANUF_FUJITSU		0x04
-#define MANUF_ULTRASPARC	0x17	/**< UltraSPARC I, UltraSPARC II */
-#define MANUF_SUN		0x3e
+#define MANUF_FUJITSU     0x04
+#define MANUF_ULTRASPARC  0x17  /**< UltraSPARC I, UltraSPARC II */
+#define MANUF_SUN         0x3e
 
-#define IMPL_ULTRASPARCI	0x10
-#define IMPL_ULTRASPARCII	0x11
-#define IMPL_ULTRASPARCII_I	0x12
-#define IMPL_ULTRASPARCII_E	0x13
-#define IMPL_ULTRASPARCIII	0x14
-#define IMPL_ULTRASPARCIII_PLUS	0x15
-#define IMPL_ULTRASPARCIII_I	0x16
-#define IMPL_ULTRASPARCIV	0x18
-#define IMPL_ULTRASPARCIV_PLUS	0x19
+#define IMPL_ULTRASPARCI         0x10
+#define IMPL_ULTRASPARCII        0x11
+#define IMPL_ULTRASPARCII_I      0x12
+#define IMPL_ULTRASPARCII_E      0x13
+#define IMPL_ULTRASPARCIII       0x14
+#define IMPL_ULTRASPARCIII_PLUS  0x15
+#define IMPL_ULTRASPARCIII_I     0x16
+#define IMPL_ULTRASPARCIV        0x18
+#define IMPL_ULTRASPARCIV_PLUS   0x19
 
-#define IMPL_SPARC64V		0x5
+#define IMPL_SPARC64V  0x5
 
 #ifndef __ASM__
@@ -58,4 +58,5 @@
 #include <arch/regdef.h>
 #include <arch/asm.h>
+#include <trace.h>
 
 #ifdef CONFIG_SMP
@@ -64,21 +65,21 @@
 
 typedef struct {
-	uint32_t mid;			/**< Processor ID as read from
-					     UPA_CONFIG/FIREPLANE_CONFIG. */
+	uint32_t mid;              /**< Processor ID as read from
+	                                UPA_CONFIG/FIREPLANE_CONFIG. */
 	ver_reg_t ver;
-	uint32_t clock_frequency;	/**< Processor frequency in Hz. */
-	uint64_t next_tick_cmpr;	/**< Next clock interrupt should be
-					     generated when the TICK register
-					     matches this value. */
+	uint32_t clock_frequency;  /**< Processor frequency in Hz. */
+	uint64_t next_tick_cmpr;   /**< Next clock interrupt should be
+	                                generated when the TICK register
+	                                matches this value. */
 } cpu_arch_t;
 
-
-/**
- * Reads the module ID (agent ID/CPUID) of the current CPU.
+/** Read the module ID (agent ID/CPUID) of the current CPU.
+ *
  */
-static inline uint32_t read_mid(void)
+NO_TRACE static inline uint32_t read_mid(void)
 {
 	uint64_t icbus_config = asi_u64_read(ASI_ICBUS_CONFIG, 0);
 	icbus_config = icbus_config >> ICBUS_CONFIG_MID_SHIFT;
+	
 #if defined (US)
 	return icbus_config & 0x1f;
@@ -91,5 +92,5 @@
 }
 
-#endif	
+#endif
 
 #endif
Index: kernel/arch/sparc64/include/sun4v/asm.h
===================================================================
--- kernel/arch/sparc64/include/sun4v/asm.h	(revision 22a28a696141d62f28e48ed72d1d255ff519795c)
+++ kernel/arch/sparc64/include/sun4v/asm.h	(revision 55bd76cdfcb40d7b25063357b27a0b77e7b71022)
@@ -27,5 +27,5 @@
  */
 
-/** @addtogroup sparc64	
+/** @addtogroup sparc64
  * @{
  */
Index: kernel/arch/sparc64/include/sun4v/cpu.h
===================================================================
--- kernel/arch/sparc64/include/sun4v/cpu.h	(revision 22a28a696141d62f28e48ed72d1d255ff519795c)
+++ kernel/arch/sparc64/include/sun4v/cpu.h	(revision 55bd76cdfcb40d7b25063357b27a0b77e7b71022)
@@ -37,8 +37,8 @@
 
 /** Maximum number of virtual processors. */
-#define MAX_NUM_STRANDS		64
+#define MAX_NUM_STRANDS  64
 
 /** Maximum number of logical processors in a processor core */
-#define MAX_CORE_STRANDS	8
+#define MAX_CORE_STRANDS  8
 
 #ifndef __ASM__
@@ -59,17 +59,13 @@
 
 typedef struct cpu_arch {
-	uint64_t id;			/**< virtual processor ID */
-	uint32_t clock_frequency;	/**< Processor frequency in Hz. */
-	uint64_t next_tick_cmpr;	/**< Next clock interrupt should be
-					     generated when the TICK register
-					     matches this value. */
-	exec_unit_t *exec_unit;		/**< Physical core. */
-	unsigned long proposed_nrdy;	/**< Proposed No. of ready threads
-					     so that cores are equally balanced. */
+	uint64_t id;                  /**< virtual processor ID */
+	uint32_t clock_frequency;     /**< Processor frequency in Hz. */
+	uint64_t next_tick_cmpr;      /**< Next clock interrupt should be
+	                                   generated when the TICK register
+	                                   matches this value. */
+	exec_unit_t *exec_unit;       /**< Physical core. */
+	unsigned long proposed_nrdy;  /**< Proposed No. of ready threads
+	                                   so that cores are equally balanced. */
 } cpu_arch_t;
-
-#endif	
-
-#ifdef __ASM__
 
 #endif