Index: kernel/arch/mips32/include/arch/mm/page.h
===================================================================
--- kernel/arch/mips32/include/arch/mm/page.h	(revision 2b95d13f98bfcaac3a7fb025f44c611b5d228c08)
+++ kernel/arch/mips32/include/arch/mm/page.h	(revision 54dee31681547ea4dfda5970a8a18590cec8441c)
@@ -27,5 +27,5 @@
  */
 
-/** @addtogroup mips32mm	
+/** @addtogroup mips32mm
  * @{
  */
@@ -70,10 +70,10 @@
  * - PTL3 has 4096 entries (12 bits)
  */
- 
+
 /* Macros describing number of entries in each level. */
-#define PTL0_ENTRIES_ARCH	64
-#define PTL1_ENTRIES_ARCH	0
-#define PTL2_ENTRIES_ARCH	0
-#define PTL3_ENTRIES_ARCH	4096
+#define PTL0_ENTRIES_ARCH  64
+#define PTL1_ENTRIES_ARCH  0
+#define PTL2_ENTRIES_ARCH  0
+#define PTL3_ENTRIES_ARCH  4096
 
 /* Macros describing size of page tables in each level. */
@@ -84,13 +84,13 @@
 
 /* Macros calculating entry indices for each level. */
-#define PTL0_INDEX_ARCH(vaddr)	((vaddr) >> 26) 
-#define PTL1_INDEX_ARCH(vaddr)	0
-#define PTL2_INDEX_ARCH(vaddr)	0
-#define PTL3_INDEX_ARCH(vaddr)	(((vaddr) >> 14) & 0xfff)
+#define PTL0_INDEX_ARCH(vaddr)  ((vaddr) >> 26)
+#define PTL1_INDEX_ARCH(vaddr)  0
+#define PTL2_INDEX_ARCH(vaddr)  0
+#define PTL3_INDEX_ARCH(vaddr)  (((vaddr) >> 14) & 0xfff)
 
 /* Set accessor for PTL0 address. */
 #define SET_PTL0_ADDRESS_ARCH(ptl0)
 
-/* Get PTE address accessors for each level. */ 
+/* Get PTE address accessors for each level. */
 #define GET_PTL1_ADDRESS_ARCH(ptl0, i) \
 	(((pte_t *) (ptl0))[(i)].pfn << 12)