Index: uspace/drv/infrastructure/rootamdm37x/rootamdm37x.c =================================================================== --- uspace/drv/infrastructure/rootamdm37x/rootamdm37x.c (revision f4c9e42b5a946132ad774ff34c173a933febc2b0) +++ uspace/drv/infrastructure/rootamdm37x/rootamdm37x.c (revision 52fc80593732a731352ed3010789c83d7fc8bb2e) @@ -164,74 +164,39 @@ /* Reset USB TLL */ - device->tll->sysconfig |= TLL_SYSCONFIG_SOFTRESET_FLAG; + pio_set_32(&device->tll->sysconfig, TLL_SYSCONFIG_SOFTRESET_FLAG, 5); ddf_msg(LVL_DEBUG2, "Waiting for USB TLL reset"); - while (!(device->tll->sysstatus & TLL_SYSSTATUS_RESET_DONE_FLAG)); + while (!(pio_read_32(&device->tll->sysstatus) & TLL_SYSSTATUS_RESET_DONE_FLAG)); ddf_msg(LVL_DEBUG, "USB TLL Reset done."); - { /* Setup idle mode (smart idle) */ - uint32_t sysc = device->tll->sysconfig; - sysc |= TLL_SYSCONFIG_CLOCKACTIVITY_FLAG | TLL_SYSCONFIG_AUTOIDLE_FLAG; - sysc = (sysc - & ~(TLL_SYSCONFIG_SIDLE_MODE_MASK << TLL_SYSCONFIG_SIDLE_MODE_SHIFT) - ) | (0x2 << TLL_SYSCONFIG_SIDLE_MODE_SHIFT); - device->tll->sysconfig = sysc; - ddf_msg(LVL_DEBUG2, "Set TLL->sysconfig (%p) to %x:%x.", - &device->tll->sysconfig, device->tll->sysconfig, sysc); - } - - { + pio_change_32(&device->tll->sysconfig, + TLL_SYSCONFIG_CLOCKACTIVITY_FLAG | TLL_SYSCONFIG_AUTOIDLE_FLAG | + TLL_SYSCONFIG_SIDLE_MODE_SMART, TLL_SYSCONFIG_SIDLE_MODE_MASK, 5); + /* Smart idle for UHH */ - uint32_t sysc = device->uhh->sysconfig; - sysc |= UHH_SYSCONFIG_CLOCKACTIVITY_FLAG | UHH_SYSCONFIG_AUTOIDLE_FLAG; - sysc = (sysc - & ~(UHH_SYSCONFIG_SIDLE_MODE_MASK << UHH_SYSCONFIG_SIDLE_MODE_SHIFT) - ) | (0x2 << UHH_SYSCONFIG_SIDLE_MODE_SHIFT); - sysc = (sysc - & ~(UHH_SYSCONFIG_MIDLE_MODE_MASK << UHH_SYSCONFIG_MIDLE_MODE_SHIFT) - ) | (0x2 << UHH_SYSCONFIG_MIDLE_MODE_SHIFT); - ddf_msg(LVL_DEBUG2, "Set UHH->sysconfig (%p) to %x.", - &device->uhh->sysconfig, device->uhh->sysconfig); - device->uhh->sysconfig = sysc; - - /* All ports are connected on BBxM */ - device->uhh->hostconfig |= (UHH_HOSTCONFIG_P1_CONNECT_STATUS_FLAG - | UHH_HOSTCONFIG_P2_CONNECT_STATUS_FLAG - | UHH_HOSTCONFIG_P3_CONNECT_STATUS_FLAG); + pio_change_32(&device->uhh->sysconfig, + UHH_SYSCONFIG_CLOCKACTIVITY_FLAG | UHH_SYSCONFIG_AUTOIDLE_FLAG | + UHH_SYSCONFIG_SIDLE_MODE_SMART, UHH_SYSCONFIG_SIDLE_MODE_MASK, 5); /* Set all ports to go through TLL(UTMI) * Direct connection can only work in HS mode */ - device->uhh->hostconfig |= (UHH_HOSTCONFIG_P1_ULPI_BYPASS_FLAG - | UHH_HOSTCONFIG_P2_ULPI_BYPASS_FLAG - | UHH_HOSTCONFIG_P3_ULPI_BYPASS_FLAG); - ddf_msg(LVL_DEBUG2, "Set UHH->hostconfig (%p) to %x.", - &device->uhh->hostconfig, device->uhh->hostconfig); - } - - device->tll->shared_conf |= TLL_SHARED_CONF_FCLK_IS_ON_FLAG; - ddf_msg(LVL_DEBUG2, "Set shared conf port (%p) to %x.", - &device->tll->shared_conf, device->tll->shared_conf); + pio_set_32(&device->uhh->hostconfig, + UHH_HOSTCONFIG_P1_ULPI_BYPASS_FLAG | + UHH_HOSTCONFIG_P2_ULPI_BYPASS_FLAG | + UHH_HOSTCONFIG_P3_ULPI_BYPASS_FLAG, 5); + + /* What is this? */ + pio_set_32(&device->tll->shared_conf, TLL_SHARED_CONF_FCLK_IS_ON_FLAG, 5); for (unsigned i = 0; i < 3; ++i) { - uint32_t ch = device->tll->channel_conf[i]; - /* Clear Channel mode and FSLS mode */ - ch &= ~(TLL_CHANNEL_CONF_CHANMODE_MASK - << TLL_CHANNEL_CONF_CHANMODE_SHIFT) - & ~(TLL_CHANNEL_CONF_FSLSMODE_MASK - << TLL_CHANNEL_CONF_FSLSMODE_SHIFT); - - /* Serial mode is the only one capable of FS/LS operation. */ - ch |= (TLL_CHANNEL_CONF_CHANMODE_UTMI_SERIAL_MODE - << TLL_CHANNEL_CONF_CHANMODE_SHIFT); - - /* Select FS/LS mode, no idea what the difference is + /* Serial mode is the only one capable of FS/LS operation. + * Select FS/LS mode, no idea what the difference is * one of bidirectional modes might be good choice * 2 = 3pin bidi phy. */ - ch |= (2 << TLL_CHANNEL_CONF_FSLSMODE_SHIFT); - - /* Write to register */ - ddf_msg(LVL_DEBUG2, "Setting port %u(%p) to %x.", - i, &device->tll->channel_conf[i], ch); - device->tll->channel_conf[i] = ch; + pio_change_32(&device->tll->channel_conf[i], + TLL_CHANNEL_CONF_CHANMODE_UTMI_SERIAL_MODE | + TLL_CHANNEL_CONF_FSLSMODE_3PIN_BIDI_PHY, + TLL_CHANNEL_CONF_CHANMODE_MASK | + TLL_CHANNEL_CONF_FSLSMODE_MASK, 5); } return EOK; Index: uspace/drv/infrastructure/rootamdm37x/uhh.h =================================================================== --- uspace/drv/infrastructure/rootamdm37x/uhh.h (revision f4c9e42b5a946132ad774ff34c173a933febc2b0) +++ uspace/drv/infrastructure/rootamdm37x/uhh.h (revision 52fc80593732a731352ed3010789c83d7fc8bb2e) @@ -42,7 +42,6 @@ typedef struct { const ioport32_t revision; -#define UHH_REVISION_MASK 0xf -#define UHH_REVISION_MINOR_SHIFT 0 -#define UHH_REVISION_MAJOR_SHIFT 4 +#define UHH_REVISION_MINOR_MASK 0x0f +#define UHH_REVISION_MAJOR_MASK 0xf0 uint32_t padd0_[3]; @@ -51,9 +50,13 @@ #define UHH_SYSCONFIG_SOFTRESET_FLAG (1 << 1) #define UHH_SYSCONFIG_ENWAKEUP_FLAG (1 << 2) +#define UHH_SYSCONFIG_SIDLE_MODE_MASK (0x3 << 3) +#define UHH_SYSCONFIG_SIDLE_MODE_FORCE (0x0 << 3) +#define UHH_SYSCONFIG_SIDLE_MODE_NO (0x1 << 3) +#define UHH_SYSCONFIG_SIDLE_MODE_SMART (0x2 << 3) #define UHH_SYSCONFIG_CLOCKACTIVITY_FLAG (1 << 8) -#define UHH_SYSCONFIG_SIDLE_MODE_MASK 0x3 -#define UHH_SYSCONFIG_SIDLE_MODE_SHIFT 3 -#define UHH_SYSCONFIG_MIDLE_MODE_MASK 0x3 -#define UHH_SYSCONFIG_MIDLE_MODE_SHIFT 12 +#define UHH_SYSCONFIG_MIDLE_MODE_MASK (0x3 << 12) +#define UHH_SYSCONFIG_MIDLE_MODE_FORCE (0x0 << 12) +#define UHH_SYSCONFIG_MIDLE_MODE_NO (0x1 << 12) +#define UHH_SYSCONFIG_MIDLE_MODE_SMART (0x2 << 12) const ioport32_t sysstatus; @@ -77,6 +80,6 @@ ioport32_t debug_csr; -#define UHH_DEBUG_CSR_EHCI_FLADJ_MASK (0x3f) -#define UHH_DEBUG_CSR_EHCI_FLADJ_SHIFT 0 +#define UHH_DEBUG_CSR_EHCI_FLADJ_MASK (0x3f << 0) +#define UHH_DEBUG_CSR_EHCI_FLADJ(x) ((x) & 0x3f) #define UHH_DEBUG_CSR_EHCI_SIMULATION_MODE_FLAG (1 << 6) #define UHH_DEBUG_CSR_OHCI_CNTSEL_FLAG (1 << 7) Index: uspace/drv/infrastructure/rootamdm37x/usbtll.h =================================================================== --- uspace/drv/infrastructure/rootamdm37x/usbtll.h (revision f4c9e42b5a946132ad774ff34c173a933febc2b0) +++ uspace/drv/infrastructure/rootamdm37x/usbtll.h (revision 52fc80593732a731352ed3010789c83d7fc8bb2e) @@ -42,7 +42,6 @@ typedef struct { const ioport32_t revision; -#define TLL_REVISION_MASK 0xf -#define TLL_REVISION_MINOR_SHIFT 0 -#define TLL_REVISION_MAJOR_SHIFT 4 +#define TLL_REVISION_MINOR_MASK 0x0f +#define TLL_REVISION_MAJOR_MASK 0xf0 uint32_t padd0_[3]; @@ -51,7 +50,9 @@ #define TLL_SYSCONFIG_SOFTRESET_FLAG (1 << 1) #define TLL_SYSCONFIG_ENWAKEUP_FLAG (1 << 2) +#define TLL_SYSCONFIG_SIDLE_MODE_MASK (0x3 << 3) +#define TLL_SYSCONFIG_SIDLE_MODE_FORCE (0x0 << 3) +#define TLL_SYSCONFIG_SIDLE_MODE_NO (0x1 << 3) +#define TLL_SYSCONFIG_SIDLE_MODE_SMART (0x2 << 3) #define TLL_SYSCONFIG_CLOCKACTIVITY_FLAG (1 << 8) -#define TLL_SYSCONFIG_SIDLE_MODE_MASK 0x3 -#define TLL_SYSCONFIG_SIDLE_MODE_SHIFT 3 ioport32_t sysstatus; @@ -72,18 +73,17 @@ #define TLL_SHARED_CONF_FCLK_IS_ON_FLAG (1 << 0) #define TLL_SHARED_CONF_FCLK_REQ_FLAG (1 << 1) +#define TLL_SHARED_CONF_USB_DIVRATIO_MASK (0x7 << 2) +#define TLL_SHARED_CONF_USB_DIVRATIO(x) (((x) & 0x7) << 2) #define TLL_SHARED_CONF_USB_180D_SDR_EN_FLAG (1 << 5) #define TLL_SHARED_CONF_USB_90D_DDR_EN_FLAG (1 << 6) -#define TLL_SHARED_CONF_USB_DIVRATIO_MASK 0x7 -#define TLL_SHARED_CONF_USB_DIVRATIO_SHIFT 2 uint32_t padd2_[3]; ioport32_t channel_conf[3]; #define TLL_CHANNEL_CONF_CHANEN_FLAG (1 << 0) -#define TLL_CHANNEL_CONF_CHANMODE_MASK 0x3 -#define TLL_CHANNEL_CONF_CHANMODE_SHIFT 1 -#define TLL_CHANNEL_CONF_CHANMODE_UTMI_ULPI_MODE 0 -#define TLL_CHANNEL_CONF_CHANMODE_UTMI_SERIAL_MODE 1 -#define TLL_CHANNEL_CONF_CHANMODE_UTMI_TRANS_MODE 2 -#define TLL_CHANNEL_CONF_CHANMODE_NO_MODE 3 +#define TLL_CHANNEL_CONF_CHANMODE_MASK (0x3 << 1) +#define TLL_CHANNEL_CONF_CHANMODE_UTMI_ULPI_MODE (0x0 << 1) +#define TLL_CHANNEL_CONF_CHANMODE_UTMI_SERIAL_MODE (0x1 << 1) +#define TLL_CHANNEL_CONF_CHANMODE_UTMI_TRANS_MODE (0x2 << 1) +#define TLL_CHANNEL_CONF_CHANMODE_NO_MODE (0x3 << 1) #define TLL_CHANNEL_CONF_UTMIISADEV_FLAG (1 << 3) #define TLL_CHANNEL_CONF_TLLATTACH_FLAG (1 << 4) @@ -101,8 +101,21 @@ #define TLL_CHANNEL_CONF_TESTTXDAT_FLAG (1 << 19) #define TLL_CHANNEL_CONF_TESTTXSE0_FLAG (1 << 20) -#define TLL_CHANNEL_CONF_FSLSMODE_MASK 0xf -#define TLL_CHANNEL_CONF_FSLSMODE_SHIFT 24 -#define TLL_CHANNEL_CONF_FSLSLINESTATE_MASK 0x3 -#define TLL_CHANNEL_CONF_FSLSLINESTATE_SHIFT 28 +#define TLL_CHANNEL_CONF_FSLSMODE_MASK (0xf << 24) +#define TLL_CHANNEL_CONF_FSLSMODE_6PIN_UNI_PHY_TX_DATSE0 (0x0 << 24) +#define TLL_CHANNEL_CONF_FSLSMODE_6PIN_UNI_PHY_TX_DPDM (0x1 << 24) +#define TLL_CHANNEL_CONF_FSLSMODE_3PIN_BIDI_PHY (0x2 << 24) +#define TLL_CHANNEL_CONF_FSLSMODE_4PIN_BIDI_PHY (0x3 << 24) +#define TLL_CHANNEL_CONF_FSLSMODE_6PIN_UNI_TLL_TX_DATSE0 (0x4 << 24) +#define TLL_CHANNEL_CONF_FSLSMODE_6PIN_UNI_TLL_TX_DPDM (0x5 << 24) +#define TLL_CHANNEL_CONF_FSLSMODE_3PIN_BIDI_TLL (0x6 << 24) +#define TLL_CHANNEL_CONF_FSLSMODE_4PIN_BIDI_TLL (0x7 << 24) +#define TLL_CHANNEL_CONF_FSLSMODE_2PIN_BIDI_TLL_DATSE0 (0xa << 24) +#define TLL_CHANNEL_CONF_FSLSMODE_2PIN_BIDI_TLL_DPDM (0xb << 24) + +#define TLL_CHANNEL_CONF_FSLSLINESTATE_MASK (0x3 << 28) +#define TLL_CHANNEL_CONF_FSLSLINESTATE_SE0 (0x0 << 28) +#define TLL_CHANNEL_CONF_FSLSLINESTATE_FS_J (0x1 << 28) +#define TLL_CHANNEL_CONF_FSLSLINESTATE_FS_K (0x2 << 28) +#define TLL_CHANNEL_CONF_FSLSLINESTATE_SE1 (0x3 << 28) /* The rest are 8bit ULPI registers */