Changeset 5265eea4 in mainline for kernel/arch/arm32/include/arch/mm/page_armv6.h

Timestamp:

2015-10-28T18:17:27Z (9 years ago)

Author:

Jakub Jermar <jakub@…>

Branches:

lfn, master, serial, ticket/834-toolchain-update, topic/msim-upgrade, topic/simplify-dev-export

Children:

77a194c, ff381a7

Parents:

0328987 (diff), 5783d10 (diff)
Note: this is a merge changeset, the changes displayed below correspond to the merge itself.
Use the (diff) links above to see all the changes relative to each parent.

Message:

Merge various ARM fixes from lp:~jakub/helenos/arm

Fix GTA02 uspace/kernel memory corruption caused by wrong TLB
invalidation. ARM920T does not have a unified TLB, so it is necessary
to purge the instruction and data TLBs separately.

Fix RaspberryPi support. Make RaspberryPi use non-shared memory
(eliminating thus a weird special case for ARMv6) and invalidate the
entire D-cache before it is re-enabled in the kernel.

Make the CP15 cache-related macros non-ARMv7-centric for ARMv6-. Define
only macros that are supported by the given CPU/architecture (partially).

Be more careful and do not assume ARMv7 features. This relates to
enabling branch predictors, prefetch buffer and various control bits
in some registers.

File:

• kernel/arch/arm32/include/arch/mm/page_armv6.h (modified) (3 diffs)

kernel/arch/arm32/include/arch/mm/page_armv6.h

@@ -156 +156 @@
 do { \
         for (unsigned i = 0; i < count; ++i) \
-                DCCMVAU_write((uintptr_t)(pt + i)); \
+                dcache_clean_mva_pou((uintptr_t)(pt + i)); \
         read_barrier(); \
 } while (0)
-
 
 /** Returns level 0 page table entry flags.
@@ -258 +257 @@
         if (flags & PAGE_CACHEABLE) {
                 /*
-                 * Write-through, write-allocate memory, see ch. B3.8.2
-                 * (p. B3-1358) of ARM Architecture reference manual.
+                 * Outer and inner write-back, write-allocate memory,
+                 * see ch. B3.8.2 (p. B3-1358) of ARM Architecture reference
+                 * manual.
+                 *
                  * Make sure the memory type is correct, and in sync with:
                  * init_boot_pt (boot/arch/arm32/src/mm.c)
@@ -278 +279 @@
         }
         
-#if defined(PROCESSOR_ARCH_armv6)
-        /* FIXME: this disables caches */
-        p->shareable = 1;
-#else
         /* Shareable is ignored for devices (non-cacheable),
          * turn it off for normal memory. */
         p->shareable = 0;
-#endif
         
         p->non_global = !(flags & PAGE_GLOBAL);