Ignore:
Timestamp:
2015-10-28T18:17:27Z (9 years ago)
Author:
Jakub Jermar <jakub@…>
Branches:
lfn, master, serial, ticket/834-toolchain-update, topic/msim-upgrade, topic/simplify-dev-export
Children:
77a194c, ff381a7
Parents:
0328987 (diff), 5783d10 (diff)
Note: this is a merge changeset, the changes displayed below correspond to the merge itself.
Use the (diff) links above to see all the changes relative to each parent.
Message:

Merge various ARM fixes from lp:~jakub/helenos/arm

Fix GTA02 uspace/kernel memory corruption caused by wrong TLB
invalidation. ARM920T does not have a unified TLB, so it is necessary
to purge the instruction and data TLBs separately.

Fix RaspberryPi support. Make RaspberryPi use non-shared memory
(eliminating thus a weird special case for ARMv6) and invalidate the
entire D-cache before it is re-enabled in the kernel.

Make the CP15 cache-related macros non-ARMv7-centric for ARMv6-. Define
only macros that are supported by the given CPU/architecture (partially).

Be more careful and do not assume ARMv7 features. This relates to
enabling branch predictors, prefetch buffer and various control bits
in some registers.

File:
1 edited

Legend:

Unmodified
Added
Removed

  • kernel/arch/arm32/include/arch/cp15.h

    r0328987 r5265eea4  
    118118};
    119119CONTROL_REG_GEN_READ(CTR, c0, 0, c0, 1);
     120
     121#if defined(PROCESSOR_ARCH_armv6) || defined(PROCESSOR_ARCH_armv7_a)
    120122CONTROL_REG_GEN_READ(TCMR, c0, 0, c0, 2);
     123
     124enum {
     125        TLBTR_SEP_FLAG = 1,
     126};
     127
    121128CONTROL_REG_GEN_READ(TLBTR, c0, 0, c0, 3);
     129#endif
     130
     131#if defined(PROCESSOR_ARCH_armv7_a)
    122132CONTROL_REG_GEN_READ(MPIDR, c0, 0, c0, 5);
    123133CONTROL_REG_GEN_READ(REVIDR, c0, 0, c0, 6);
     134#endif
    124135
    125136enum {
    … …  
    309320enum {
    310321        TTBR_ADDR_MASK = 0xffffff80,
     322#if defined(PROCESSOR_ARCH_armv6) || defined(PROCESSOR_ARCH_armv7_a)
    311323        TTBR_NOS_FLAG = 1 << 5,
    312324        TTBR_RGN_MASK = 0x3 << 3,
    … …  
    317329        TTBR_S_FLAG = 1 << 1,
    318330        TTBR_C_FLAG = 1 << 0,
     331#endif
    319332};
    320333CONTROL_REG_GEN_READ(TTBR0, c2, 0, c0, 0);
    321334CONTROL_REG_GEN_WRITE(TTBR0, c2, 0, c0, 0);
     335
     336#if defined(PROCESSOR_ARCH_armv6) || defined(PROCESSOR_ARCH_armv7_a)
    322337CONTROL_REG_GEN_READ(TTBR1, c2, 0, c0, 1);
    323338CONTROL_REG_GEN_WRITE(TTBR1, c2, 0, c0, 1);
    324339CONTROL_REG_GEN_READ(TTBCR, c2, 0, c0, 2);
    325340CONTROL_REG_GEN_WRITE(TTBCR, c2, 0, c0, 2);
    326 
     341#endif
     342
     343#if defined(PROCESSOR_ARCH_armv7)
    327344CONTROL_REG_GEN_READ(HTCR, c2, 4, c0, 2);
    328345CONTROL_REG_GEN_WRITE(HTCR, c2, 4, c0, 2);
    … …  
    339356CONTROL_REG_GEN_READ(VTTBRH, c2, 0, c2, 6);
    340357CONTROL_REG_GEN_WRITE(VTTBRH, c2, 0, c2, 6);
     358#endif
    341359
    342360CONTROL_REG_GEN_READ(DACR, c3, 0, c0, 0);
    … …  
    373391CONTROL_REG_GEN_WRITE(HPFAR, c6, 4, c0, 4);
    374392
    375 /* Cache maintenance, address translation and other */
    376 CONTROL_REG_GEN_WRITE(WFI, c7, 0, c0, 4); /* armv6 only */
    377 CONTROL_REG_GEN_WRITE(ICIALLLUIS, c7, 0, c1, 0);
    378 CONTROL_REG_GEN_WRITE(BPIALLIS, c7, 0, c1, 6);
    379 CONTROL_REG_GEN_READ(PAR, c7, 0, c4, 0);
    380 CONTROL_REG_GEN_WRITE(PAR, c7, 0, c4, 0);
    381 CONTROL_REG_GEN_READ(PARH, c7, 0, c7, 0);   /* PAE */
    382 CONTROL_REG_GEN_WRITE(PARH, c7, 0, c7, 0);   /* PAE */
    383 CONTROL_REG_GEN_WRITE(ICIALLU, c7, 0, c5, 0);
    384 CONTROL_REG_GEN_WRITE(ICIMVAU, c7, 0, c5, 1);
     393/*
     394 * Cache maintenance, address translation and other
     395 */
     396
     397#if defined(PROCESSOR_cortex_a8)
     398#define CP15_C7_MVA_ALIGN       64
     399#elif defined(PROCESSOR_arm1176)
     400#define CP15_C7_MVA_ALIGN       32
     401#elif defined(PROCESSOR_arm926ej_s)
     402#define CP15_C7_MVA_ALIGN       32
     403#elif defined(PROCESSOR_arm920t)
     404#define CP15_C7_MVA_ALIGN       32
     405#else
     406#error Unknow MVA alignment
     407#endif
     408
     409#if defined(PROCESSOR_ARCH_armv6) || defined(PROCESSOR_ARCH_armv7_a)
    385410CONTROL_REG_GEN_WRITE(CP15ISB, c7, 0, c5, 4);
    386411CONTROL_REG_GEN_WRITE(BPIALL, c7, 0, c5, 6);
    387412CONTROL_REG_GEN_WRITE(BPIMVA, c7, 0, c5, 7);
    388 
     413#endif
     414
     415#if !defined(PROCESSOR_arm920t)
     416CONTROL_REG_GEN_WRITE(DCISW, c7, 0, c6, 2);
     417#endif
     418
     419#if defined(PROCESSOR_arm920t) || !defined(PROCESSOR_ARCH_armv4)
     420CONTROL_REG_GEN_WRITE(DCCSW, c7, 0, c10, 2);
     421#endif
     422
     423CONTROL_REG_GEN_WRITE(CP15DSB, c7, 0, c10, 4);
     424
     425#if defined(PROCESSOR_ARCH_armv6) || defined(PROCESSOR_ARCH_armv7_a)
     426CONTROL_REG_GEN_WRITE(CP15DMB, c7, 0, c10, 5);
     427#endif
     428
     429#if defined(PROCESSOR_arm920t) || !defined(PROCESSOR_ARCH_armv4)
     430CONTROL_REG_GEN_WRITE(DCCISW, c7, 0, c14, 2);
     431#endif
     432
     433#if defined(PROCESSOR_ARCH_armv7_a)
     434CONTROL_REG_GEN_WRITE(ICIALLLUIS, c7, 0, c1, 0);
     435CONTROL_REG_GEN_WRITE(BPIALLIS, c7, 0, c1, 6);
     436CONTROL_REG_GEN_READ(PAR, c7, 0, c4, 0); /* Security Extensions */
     437CONTROL_REG_GEN_WRITE(PAR, c7, 0, c4, 0); /* Security Extensions */
     438CONTROL_REG_GEN_WRITE(ICIALLU, c7, 0, c5, 0);
     439CONTROL_REG_GEN_WRITE(ICIMVAU, c7, 0, c5, 1);
    389440CONTROL_REG_GEN_WRITE(DCIMVAC, c7, 0, c6, 1);
    390 CONTROL_REG_GEN_WRITE(DCISW, c7, 0, c6, 2);
    391 
    392 CONTROL_REG_GEN_WRITE(ATS1CPR, c7, 0, c8, 0);
    393 CONTROL_REG_GEN_WRITE(ATS1CPW, c7, 0, c8, 1);
    394 CONTROL_REG_GEN_WRITE(ATS1CUR, c7, 0, c8, 2);
    395 CONTROL_REG_GEN_WRITE(ATS1CUW, c7, 0, c8, 3);
    396 CONTROL_REG_GEN_WRITE(ATS12NSOPR, c7, 0, c8, 4);
    397 CONTROL_REG_GEN_WRITE(ATS12NSOPW, c7, 0, c8, 5);
    398 CONTROL_REG_GEN_WRITE(ATS12NSOUR, c7, 0, c8, 6);
    399 CONTROL_REG_GEN_WRITE(ATS12NSOUW, c7, 0, c8, 7);
    400 
    401 
     441CONTROL_REG_GEN_READ(PARH, c7, 0, c7, 0); /* PAE */
     442CONTROL_REG_GEN_WRITE(PARH, c7, 0, c7, 0); /* PAE */
     443CONTROL_REG_GEN_WRITE(ATS1CPR, c7, 0, c8, 0); /* Security Extensions */
     444CONTROL_REG_GEN_WRITE(ATS1CPW, c7, 0, c8, 1); /* Security Extensions */
     445CONTROL_REG_GEN_WRITE(ATS1CUR, c7, 0, c8, 2); /* Security Extensions */
     446CONTROL_REG_GEN_WRITE(ATS1CUW, c7, 0, c8, 3); /* Security Extensions */
     447CONTROL_REG_GEN_WRITE(ATS12NSOPR, c7, 0, c8, 4); /* Security Extensions */
     448CONTROL_REG_GEN_WRITE(ATS12NSOPW, c7, 0, c8, 5); /* Security Extensions */
     449CONTROL_REG_GEN_WRITE(ATS12NSOUR, c7, 0, c8, 6); /* Security Extensions */
     450CONTROL_REG_GEN_WRITE(ATS12NSOUW, c7, 0, c8, 7); /* Security Extensions */
     451CONTROL_REG_GEN_WRITE(ATS1HR, c7, 4, c8, 0); /* Virtualization Extensions */
     452CONTROL_REG_GEN_WRITE(ATS1HW, c7, 4, c8, 1); /* Virtualization Extensions */
    402453CONTROL_REG_GEN_WRITE(DCCMVAC, c7, 0, c10, 1);
    403 CONTROL_REG_GEN_WRITE(DCCSW, c7, 0, c10, 2);
    404 CONTROL_REG_GEN_WRITE(CP15DSB, c7, 0, c10, 4);
    405 CONTROL_REG_GEN_WRITE(CP15DMB, c7, 0, c10, 5);
    406454CONTROL_REG_GEN_WRITE(DCCMVAU, c7, 0, c11, 1);
    407 
    408 CONTROL_REG_GEN_WRITE(PFI, c7, 0, c11, 1); /* armv6 only */
    409 
    410455CONTROL_REG_GEN_WRITE(DCCIMVAC, c7, 0, c14, 1);
    411 CONTROL_REG_GEN_WRITE(DCCISW, c7, 0, c14, 2);
    412 
    413 CONTROL_REG_GEN_WRITE(ATS1HR, c7, 4, c8, 0);
    414 CONTROL_REG_GEN_WRITE(ATS1HW, c7, 4, c8, 1);
     456#else
     457
     458#if defined(PROCESSOR_arm920t) || !defined(PROCESSOR_ARCH_armv4)
     459CONTROL_REG_GEN_WRITE(WFI, c7, 0, c0, 4);
     460#endif
     461
     462CONTROL_REG_GEN_WRITE(ICIALL, c7, 0, c5, 0);
     463CONTROL_REG_GEN_WRITE(ICIMVA, c7, 0, c5, 1);
     464
     465#if !defined(PROCESSOR_ARCH_armv4)
     466CONTROL_REG_GEN_WRITE(ICISW, c7, 0, c5, 2);
     467#endif
     468
     469CONTROL_REG_GEN_WRITE(DCIALL, c7, 0, c6, 0);
     470CONTROL_REG_GEN_WRITE(DCIMVA, c7, 0, c6, 1);
     471CONTROL_REG_GEN_WRITE(CIALL, c7, 0, c7, 0);
     472CONTROL_REG_GEN_WRITE(CIMVA, c7, 0, c7, 1);
     473
     474#if !defined(PROCESSOR_ARCH_armv4)
     475CONTROL_REG_GEN_WRITE(CISW, c7, 0, c7, 2);
     476#endif
     477
     478#if defined(PROCESSOR_ARCH_armv4) || defined(PROCESSOR_ARCH_armv6)
     479CONTROL_REG_GEN_WRITE(DCCALL, c7, 0, c10, 0);
     480#endif
     481
     482CONTROL_REG_GEN_WRITE(DCCMVA, c7, 0, c10, 1);
     483
     484#if defined(PROCESSOR_ARCH_armv4) || defined(PROCESSOR_ARCH_armv6)
     485CONTROL_REG_GEN_WRITE(CCALL, c7, 0, c11, 0);
     486#endif
     487
     488CONTROL_REG_GEN_WRITE(CCMVA, c7, 0, c11, 1);
     489
     490#if !defined(PROCESSOR_ARCH_armv4)
     491CONTROL_REG_GEN_WRITE(CCSW, c7, 0, c11, 2);
     492#endif
     493
     494#if defined(PROCESSOR_arm920t) || !defined(PROCESSOR_ARCH_armv4)
     495CONTROL_REG_GEN_WRITE(PFIMVA, c7, 0, c13, 1);
     496#endif
     497
     498#if defined(PROCESSOR_ARCH_armv4) || defined(PROCESSOR_ARCH_armv6)
     499CONTROL_REG_GEN_WRITE(DCCIALL, c7, 0, c14, 0);
     500#endif
     501
     502CONTROL_REG_GEN_WRITE(DCCIMVA, c7, 0, c14, 1);
     503
     504#if defined(PROCESSOR_ARCH_armv4) || defined(PROCESSOR_ARCH_armv6)
     505CONTROL_REG_GEN_WRITE(CCIALL, c7, 0, c15, 0);
     506#endif
     507
     508CONTROL_REG_GEN_WRITE(CCIMVA, c7, 0, c15, 1);
     509
     510#if defined(PROCESSOR_ARCH_armv5) || defined(PROCESSOR_ARCH_armv6)
     511CONTROL_REG_GEN_WRITE(CCISW, c7, 0, c15, 2);
     512#endif
     513
     514#endif
    415515
    416516/* TLB maintenance */
     517#if defined(PROCESSOR_ARCH_armv7_a)
    417518CONTROL_REG_GEN_WRITE(TLBIALLIS, c8, 0, c3, 0); /* Inner shareable */
    418519CONTROL_REG_GEN_WRITE(TLBIMVAIS, c8, 0, c3, 1); /* Inner shareable */
    419520CONTROL_REG_GEN_WRITE(TLBIASIDIS, c8, 0, c3, 2); /* Inner shareable */
    420521CONTROL_REG_GEN_WRITE(TLBIMVAAIS, c8, 0, c3, 3); /* Inner shareable */
     522#endif
    421523
    422524CONTROL_REG_GEN_WRITE(ITLBIALL, c8, 0, c5, 0);
    423525CONTROL_REG_GEN_WRITE(ITLBIMVA, c8, 0, c5, 1);
     526#if defined(PROCESSOR_ARCH_armv6) || defined(PROCESSOR_ARCH_armv7_a)
    424527CONTROL_REG_GEN_WRITE(ITLBIASID, c8, 0, c5, 2);
     528#endif
    425529
    426530CONTROL_REG_GEN_WRITE(DTLBIALL, c8, 0, c6, 0);
    427531CONTROL_REG_GEN_WRITE(DTLBIMVA, c8, 0, c6, 1);
     532#if defined(PROCESSOR_ARCH_armv6) || defined(PROCESSOR_ARCH_armv7_a)
    428533CONTROL_REG_GEN_WRITE(DTLBIASID, c8, 0, c6, 2);
     534#endif
    429535
    430536CONTROL_REG_GEN_WRITE(TLBIALL, c8, 0, c7, 0);
    431537CONTROL_REG_GEN_WRITE(TLBIMVA, c8, 0, c7, 1);
     538#if defined(PROCESSOR_ARCH_armv6) || defined(PROCESSOR_ARCH_armv7_a)
    432539CONTROL_REG_GEN_WRITE(TLBIASID, c8, 0, c7, 2);
     540#endif
     541#if defined(PROCESSOR_ARCH_armv7_a)
    433542CONTROL_REG_GEN_WRITE(TLBIMVAA, c8, 0, c7, 3);
    434 
     543#endif
     544
     545#if defined(PROCESSOR_ARCH_armv7_a)
    435546CONTROL_REG_GEN_WRITE(TLBIALLHIS, c8, 4, c3, 0); /* Inner shareable */
    436547CONTROL_REG_GEN_WRITE(TLBIMVAHIS, c8, 4, c3, 1); /* Inner shareable */
    437548CONTROL_REG_GEN_WRITE(TLBIALLNSNHIS, c8, 4, c3, 4); /* Inner shareable */
    438 
     549#endif
     550
     551#if defined(PROCESSOR_ARCH_armv7_a)
    439552CONTROL_REG_GEN_WRITE(TLBIALLH, c8, 4, c7, 0);
    440553CONTROL_REG_GEN_WRITE(TLBIMVAH, c8, 4, c7, 1);
    441554CONTROL_REG_GEN_WRITE(TLBIALLNSNHS, c8, 4, c7, 4);
     555#endif
    442556
    443557/* c9 are performance monitoring resgisters */
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