Changeset 5265eea4 in mainline for kernel/arch/arm32/include/arch/cache.h

Timestamp:

2015-10-28T18:17:27Z (9 years ago)

Author:

Jakub Jermar <jakub@…>

Branches:

lfn, master, serial, ticket/834-toolchain-update, topic/msim-upgrade, topic/simplify-dev-export

Children:

77a194c, ff381a7

Parents:

0328987 (diff), 5783d10 (diff)
Note: this is a merge changeset, the changes displayed below correspond to the merge itself.
Use the (diff) links above to see all the changes relative to each parent.

Message:

Merge various ARM fixes from lp:~jakub/helenos/arm

Fix GTA02 uspace/kernel memory corruption caused by wrong TLB
invalidation. ARM920T does not have a unified TLB, so it is necessary
to purge the instruction and data TLBs separately.

Fix RaspberryPi support. Make RaspberryPi use non-shared memory
(eliminating thus a weird special case for ARMv6) and invalidate the
entire D-cache before it is re-enabled in the kernel.

Make the CP15 cache-related macros non-ARMv7-centric for ARMv6-. Define
only macros that are supported by the given CPU/architecture (partially).

Be more careful and do not assume ARMv7 features. This relates to
enabling branch predictors, prefetch buffer and various control bits
in some registers.

File:

• kernel/arch/arm32/include/arch/cache.h (modified) (2 diffs)

kernel/arch/arm32/include/arch/cache.h

@@ -37 +37 @@
 #define KERN_arm32_CACHE_H_
 
+#include <typedefs.h>
+
 unsigned dcache_levels(void);
 
@@ -43 +45 @@
 void cpu_dcache_flush(void);
 void cpu_dcache_flush_invalidate(void);
-void icache_invalidate(void);
+extern void icache_invalidate(void);
+extern void dcache_invalidate(void);
+extern void dcache_clean_mva_pou(uintptr_t);
 
 #endif