Changeset 5265eea4 in mainline for kernel/arch/arm32/include/arch/barrier.h

Timestamp:

2015-10-28T18:17:27Z (9 years ago)

Author:

Jakub Jermar <jakub@…>

Branches:

lfn, master, serial, ticket/834-toolchain-update, topic/msim-upgrade, topic/simplify-dev-export

Children:

77a194c, ff381a7

Parents:

0328987 (diff), 5783d10 (diff)
Note: this is a merge changeset, the changes displayed below correspond to the merge itself.
Use the (diff) links above to see all the changes relative to each parent.

Message:

Merge various ARM fixes from lp:~jakub/helenos/arm

Fix GTA02 uspace/kernel memory corruption caused by wrong TLB
invalidation. ARM920T does not have a unified TLB, so it is necessary
to purge the instruction and data TLBs separately.

Fix RaspberryPi support. Make RaspberryPi use non-shared memory
(eliminating thus a weird special case for ARMv6) and invalidate the
entire D-cache before it is re-enabled in the kernel.

Make the CP15 cache-related macros non-ARMv7-centric for ARMv6-. Define
only macros that are supported by the given CPU/architecture (partially).

Be more careful and do not assume ARMv7 features. This relates to
enabling branch predictors, prefetch buffer and various control bits
in some registers.

File:

• kernel/arch/arm32/include/arch/barrier.h (modified) (4 diffs)

kernel/arch/arm32/include/arch/barrier.h

@@ -38 +38 @@
 
 #ifdef KERNEL
+#include <arch/cache.h>
 #include <arch/cp15.h>
+#include <align.h>
 #else
 #include <libarch/cp15.h>
@@ -71 +73 @@
  * CP15 implementation is mandatory only for armv6+.
  */
+#if defined(PROCESSOR_ARCH_armv6) || defined(PROCESSOR_ARCH_armv7_a)
 #define memory_barrier()  CP15DMB_write(0)
-#define read_barrier()    CP15DSB_write(0)
+#else
+#define memory_barrier()  CP15DSB_write(0)
+#endif
+#define read_barrier()    CP15DSB_write(0) 
 #define write_barrier()   read_barrier()
+#if defined(PROCESSOR_ARCH_armv6) || defined(PROCESSOR_ARCH_armv7_a)
 #define inst_barrier()    CP15ISB_write(0)
+#else
+#define inst_barrier()
+#endif
 #else
 /* Older manuals mention syscalls as a way to implement cache coherency and
@@ -103 +113 @@
 
 #if defined PROCESSOR_ARCH_armv7_a | defined PROCESSOR_ARCH_armv6 | defined KERNEL
-/* Available on all supported arms,
- * invalidates entire ICache so the written value does not matter. */
 //TODO might be PL1 only on armv5-
 #define smc_coherence(a) \
 do { \
-        DCCMVAU_write((uint32_t)(a));  /* Flush changed memory */\
+        dcache_clean_mva_pou(ALIGN_DOWN((uintptr_t) a, CP15_C7_MVA_ALIGN)); \
         write_barrier();               /* Wait for completion */\
-        ICIALLU_write(0);              /* Flush ICache */\
+        icache_invalidate();\
         inst_barrier();                /* Wait for Inst refetch */\
 } while (0)
@@ -117 +125 @@
 #define smc_coherence_block(a, l) \
 do { \
-        for (uintptr_t addr = (uintptr_t)a; addr < (uintptr_t)a + l; addr += 4)\
+        for (uintptr_t addr = (uintptr_t) a; addr < (uintptr_t) a + l; \
+            addr += CP15_C7_MVA_ALIGN) \
                 smc_coherence(addr); \
 } while (0)