Changeset 5265eea4 in mainline for boot/arch/arm32/src/mm.c

Timestamp:

2015-10-28T18:17:27Z (9 years ago)

Author:

Jakub Jermar <jakub@…>

Branches:

lfn, master, serial, ticket/834-toolchain-update, topic/msim-upgrade, topic/simplify-dev-export

Children:

77a194c, ff381a7

Parents:

0328987 (diff), 5783d10 (diff)
Note: this is a merge changeset, the changes displayed below correspond to the merge itself.
Use the (diff) links above to see all the changes relative to each parent.

Message:

Merge various ARM fixes from lp:~jakub/helenos/arm

Fix GTA02 uspace/kernel memory corruption caused by wrong TLB
invalidation. ARM920T does not have a unified TLB, so it is necessary
to purge the instruction and data TLBs separately.

Fix RaspberryPi support. Make RaspberryPi use non-shared memory
(eliminating thus a weird special case for ARMv6) and invalidate the
entire D-cache before it is re-enabled in the kernel.

Make the CP15 cache-related macros non-ARMv7-centric for ARMv6-. Define
only macros that are supported by the given CPU/architecture (partially).

Be more careful and do not assume ARMv7 features. This relates to
enabling branch predictors, prefetch buffer and various control bits
in some registers.

File:

• boot/arch/arm32/src/mm.c (modified) (3 diffs)

boot/arch/arm32/src/mm.c

@@ -143 +143 @@
         pte->should_be_zero_1 = 0;
         pte->access_permission_0 = PTE_AP_USER_NO_KERNEL_RW;
-#ifdef PROCESSOR_ARCH_armv7_a
+#if defined(PROCESSOR_ARCH_armv6) || defined(PROCESSOR_ARCH_armv7_a)
         /*
          * Keeps this setting in sync with memory type attributes in:
@@ -152 +152 @@
         pte->tex = section_cacheable(frame) ? 5 : 0;
         pte->cacheable = section_cacheable(frame) ? 0 : 0;
-        pte->bufferable = section_cacheable(frame) ? 1 : 0;
+        pte->bufferable = section_cacheable(frame) ? 1 : 1;
 #else
-        pte->bufferable = 1;
+        pte->bufferable = section_cacheable(frame);
         pte->cacheable = section_cacheable(frame);
         pte->tex = 0;
@@ -189 +189 @@
          */
         uint32_t val = (uint32_t)boot_pt & TTBR_ADDR_MASK;
+#if defined(PROCESSOR_ARCH_armv6) || defined(PROCESSOR_ARCH_armv7_a)
+        // FIXME: TTBR_RGN_WBWA_CACHE is unpredictable on ARMv6
         val |= TTBR_RGN_WBWA_CACHE | TTBR_C_FLAG;
+#endif
         TTBR0_write(val);
 }