Changeset 5265eea4 in mainline for boot/arch/arm32/src/main.c
- Timestamp:
- 2015-10-28T18:17:27Z (9 years ago)
- Branches:
- lfn, master, serial, ticket/834-toolchain-update, topic/msim-upgrade, topic/simplify-dev-export
- Children:
- 77a194c, ff381a7
- Parents:
- 0328987 (diff), 5783d10 (diff)
Note: this is a merge changeset, the changes displayed below correspond to the merge itself.
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- 1 edited
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boot/arch/arm32/src/main.c
r0328987 r5265eea4 47 47 #include <errno.h> 48 48 #include <inflate.h> 49 #include <arch/cp15.h> 49 50 50 51 #define TOP2ADDR(top) (((void *) PA2KA(BOOT_OFFSET)) + (top)) … … 55 56 static inline void clean_dcache_poc(void *address, size_t size) 56 57 { 57 const uintptr_t addr = (uintptr_t)address; 58 for (uintptr_t a = addr; a < addr + size; a += 4) { 59 /* DCCMVAC - clean by address to the point of coherence */ 60 asm volatile ("mcr p15, 0, %[a], c7, c10, 1\n" :: [a]"r"(a) : ); 58 const uintptr_t addr = (uintptr_t) address; 59 60 #if !defined(PROCESSOR_ARCH_armv7_a) 61 bool sep; 62 if (MIDR_read() != CTR_read()) { 63 sep = (CTR_read() & CTR_SEP_FLAG) == CTR_SEP_FLAG; 64 } else { 65 printf("Unknown cache type.\n"); 66 halt(); 67 } 68 #endif 69 70 for (uintptr_t a = ALIGN_DOWN(addr, CP15_C7_MVA_ALIGN); a < addr + size; 71 a += CP15_C7_MVA_ALIGN) { 72 #if defined(PROCESSOR_ARCH_armv7_a) 73 DCCMVAC_write(a); 74 #else 75 if (sep) 76 DCCMVA_write(a); 77 else 78 CCMVA_write(a); 79 #endif 61 80 } 62 81 }
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