Changeset 5265eea4 in mainline for boot/arch/arm32/src/main.c


Ignore:
Timestamp:
2015-10-28T18:17:27Z (9 years ago)
Author:
Jakub Jermar <jakub@…>
Branches:
lfn, master, serial, ticket/834-toolchain-update, topic/msim-upgrade, topic/simplify-dev-export
Children:
77a194c, ff381a7
Parents:
0328987 (diff), 5783d10 (diff)
Note: this is a merge changeset, the changes displayed below correspond to the merge itself.
Use the (diff) links above to see all the changes relative to each parent.
Message:

Merge various ARM fixes from lp:~jakub/helenos/arm

Fix GTA02 uspace/kernel memory corruption caused by wrong TLB
invalidation. ARM920T does not have a unified TLB, so it is necessary
to purge the instruction and data TLBs separately.

Fix RaspberryPi support. Make RaspberryPi use non-shared memory
(eliminating thus a weird special case for ARMv6) and invalidate the
entire D-cache before it is re-enabled in the kernel.

Make the CP15 cache-related macros non-ARMv7-centric for ARMv6-. Define
only macros that are supported by the given CPU/architecture (partially).

Be more careful and do not assume ARMv7 features. This relates to
enabling branch predictors, prefetch buffer and various control bits
in some registers.

File:
1 edited

Legend:

Unmodified
Added
Removed
  • boot/arch/arm32/src/main.c

    r0328987 r5265eea4  
    4747#include <errno.h>
    4848#include <inflate.h>
     49#include <arch/cp15.h>
    4950
    5051#define TOP2ADDR(top)  (((void *) PA2KA(BOOT_OFFSET)) + (top))
     
    5556static inline void clean_dcache_poc(void *address, size_t size)
    5657{
    57         const uintptr_t addr = (uintptr_t)address;
    58         for (uintptr_t a = addr; a < addr + size; a += 4) {
    59                 /* DCCMVAC - clean by address to the point of coherence */
    60                 asm volatile ("mcr p15, 0, %[a], c7, c10, 1\n" :: [a]"r"(a) : );
     58        const uintptr_t addr = (uintptr_t) address;
     59
     60#if !defined(PROCESSOR_ARCH_armv7_a)
     61        bool sep;
     62        if (MIDR_read() != CTR_read()) {
     63                sep = (CTR_read() & CTR_SEP_FLAG) == CTR_SEP_FLAG;
     64        } else {
     65                printf("Unknown cache type.\n");
     66                halt();
     67        }
     68#endif
     69
     70        for (uintptr_t a = ALIGN_DOWN(addr, CP15_C7_MVA_ALIGN); a < addr + size;
     71            a += CP15_C7_MVA_ALIGN) {
     72#if defined(PROCESSOR_ARCH_armv7_a)
     73                DCCMVAC_write(a);
     74#else
     75                if (sep)
     76                        DCCMVA_write(a);
     77                else
     78                        CCMVA_write(a);
     79#endif
    6180        }
    6281}
Note: See TracChangeset for help on using the changeset viewer.