Changeset 5265eea4 in mainline for boot/arch/arm32/src/asm.S


Ignore:
Timestamp:
2015-10-28T18:17:27Z (9 years ago)
Author:
Jakub Jermar <jakub@…>
Branches:
lfn, master, serial, ticket/834-toolchain-update, topic/msim-upgrade, topic/simplify-dev-export
Children:
77a194c, ff381a7
Parents:
0328987 (diff), 5783d10 (diff)
Note: this is a merge changeset, the changes displayed below correspond to the merge itself.
Use the (diff) links above to see all the changes relative to each parent.
Message:

Merge various ARM fixes from lp:~jakub/helenos/arm

Fix GTA02 uspace/kernel memory corruption caused by wrong TLB
invalidation. ARM920T does not have a unified TLB, so it is necessary
to purge the instruction and data TLBs separately.

Fix RaspberryPi support. Make RaspberryPi use non-shared memory
(eliminating thus a weird special case for ARMv6) and invalidate the
entire D-cache before it is re-enabled in the kernel.

Make the CP15 cache-related macros non-ARMv7-centric for ARMv6-. Define
only macros that are supported by the given CPU/architecture (partially).

Be more careful and do not assume ARMv7 features. This relates to
enabling branch predictors, prefetch buffer and various control bits
in some registers.

File:
1 edited

Legend:

Unmodified
Added
Removed
  • boot/arch/arm32/src/asm.S

    r0328987 r5265eea4  
    7575        bic     r4, r4, #(1 << CP15_C1_DC)
    7676
    77         # Disable I-cache and Branche predictors.
     77        # Disable I-cache and Branch predictors.
    7878        bic     r4, r4, #(1 << CP15_C1_IC)
     79#ifdef PROCESSOR_ARCH_armv6
    7980        bic     r4, r4, #(1 << CP15_C1_BP)
     81#endif
    8082       
    8183        mcr     p15, 0, r4, c1, c0, 0
    8284#endif
    83 
    84 
    8585       
    86         #Wait for the operations to complete
     86        # Wait for the operations to complete
    8787#ifdef PROCESSOR_ARCH_armv7_a
    8888        dsb
    8989#else
    90         #cp15 dsb, r4 is ignored (should be zero)
     90        # cp15 dsb, r4 is ignored (should be zero)
    9191        mov r4, #0
    9292        mcr p15, 0, r4, c7, c10, 4
     
    9898        nop
    9999
    100         #Wait for the operations to complete
     100        # Wait for the operations to complete
    101101#ifdef PROCESSOR_ARCH_armv7_a
    102102        isb
    103103        nop
    104 #else
     104#elif defined(PROCESSOR_ARCH_armv6)
    105105        # cp15 isb
    106106        mcr p15, 0, r4, c7, c5, 4
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