Index: kernel/arch/amd64/src/fpu_context.c
===================================================================
--- kernel/arch/amd64/src/fpu_context.c	(revision 11b285d87da6e1d6a1d65134694b4f971f3cdebc)
+++ kernel/arch/amd64/src/fpu_context.c	(revision 4f8772d4d5ecb28999d787aebab937222f9f97d8)
@@ -57,6 +57,8 @@
 {
 	/* TODO: Zero all SSE, MMX etc. registers */
-	/* Default value of SCR register is 0x1f80,
-	 * it masks all FPU exceptions*/
+	/*
+	 * Default value of SCR register is 0x1f80,
+	 * it masks all FPU exceptions
+	 */
 	asm volatile (
 	    "fninit\n"
Index: kernel/arch/amd64/src/kseg.c
===================================================================
--- kernel/arch/amd64/src/kseg.c	(revision 11b285d87da6e1d6a1d65134694b4f971f3cdebc)
+++ kernel/arch/amd64/src/kseg.c	(revision 4f8772d4d5ecb28999d787aebab937222f9f97d8)
@@ -42,5 +42,5 @@
  * Allocate and initialize a per-CPU structure to be accessible via the
  * GS_KERNEL segment register.
- **/
+ */
 void kseg_init(void)
 {
Index: kernel/arch/amd64/src/pm.c
===================================================================
--- kernel/arch/amd64/src/pm.c	(revision 11b285d87da6e1d6a1d65134694b4f971f3cdebc)
+++ kernel/arch/amd64/src/pm.c	(revision 4f8772d4d5ecb28999d787aebab937222f9f97d8)
@@ -268,7 +268,9 @@
 		tss_p = &tss;
 	} else {
-		/* We are going to use malloc, which may return
+		/*
+		 * We are going to use malloc, which may return
 		 * non boot-mapped pointer, initialize the CR3 register
-		 * ahead of page_init */
+		 * ahead of page_init
+		 */
 		write_cr3((uintptr_t) AS_KERNEL->genarch.page_table);
 
Index: kernel/arch/amd64/src/syscall.c
===================================================================
--- kernel/arch/amd64/src/syscall.c	(revision 11b285d87da6e1d6a1d65134694b4f971f3cdebc)
+++ kernel/arch/amd64/src/syscall.c	(revision 4f8772d4d5ecb28999d787aebab937222f9f97d8)
@@ -52,5 +52,6 @@
 	/* Setup syscall entry address */
 
-	/* This is _mess_ - the 64-bit CS is argument + 16,
+	/*
+	 * This is _mess_ - the 64-bit CS is argument + 16,
 	 * the SS is argument + 8. The order is:
 	 * +0(KDATA_DES), +8(UDATA_DES), +16(UTEXT_DES)
@@ -60,5 +61,6 @@
 	    ((uint64_t) (GDT_SELECTOR(KTEXT_DES) | PL_KERNEL) << 32));
 	write_msr(AMD_MSR_LSTAR, (uint64_t)syscall_entry);
-	/* Mask RFLAGS on syscall
+	/*
+	 * Mask RFLAGS on syscall
 	 * - disable interrupts, until we exchange the stack register
 	 *   (mask the IF bit)