Index: kernel/arch/arm32/src/fpu_context.c
===================================================================
--- kernel/arch/arm32/src/fpu_context.c	(revision 37bb3e1a59cc39e53a7fefce44c427ce72f482c2)
+++ kernel/arch/arm32/src/fpu_context.c	(revision 4f843dedcb86f10b819e33487510da951391696b)
@@ -86,9 +86,8 @@
 	asm volatile (
 		"vmrs r1, fpexc\n"
-		"stmia %0!, {r1}\n"
-		"vmrs r1, fpscr\n"
-		"stmia %0!, {r1}\n"
+		"vmrs r2, fpscr\n"
+		"stmia %0!, {r1, r2}\n"
 		"vstmia %0!, {s0-s31}\n"
-		::"r" (ctx): "r1","memory"
+		::"r" (ctx): "r1","r2","memory"
 	);
 }
@@ -101,10 +100,9 @@
 {
 	asm volatile (
-		"ldmia %0!, {r1}\n"
+		"ldmia %0!, {r1, r2}\n"
 		"vmsr fpexc, r1\n"
-		"ldmia %0!, {r1}\n"
-		"vmsr fpscr, r1\n"
+		"vmsr fpscr, r2\n"
 		"vldmia %0!, {s0-s31}\n"
-		::"r" (ctx): "r1"
+		::"r" (ctx): "r1","r2"
 	);
 }
@@ -118,9 +116,8 @@
 	asm volatile (
 		"vmrs r1, fpexc\n"
-		"stmia %0!, {r1}\n"
-		"vmrs r1, fpscr\n"
-		"stmia %0!, {r1}\n"
+		"vmrs r2, fpscr\n"
+		"stmia %0!, {r1, r2}\n"
 		"vstmia %0!, {d0-d15}\n"
-		::"r" (ctx): "r1","memory"
+		::"r" (ctx): "r1","r2","memory"
 	);
 }
@@ -133,10 +130,9 @@
 {
 	asm volatile (
-		"ldmia %0!, {r1}\n"
+		"ldmia %0!, {r1, r2}\n"
 		"vmsr fpexc, r1\n"
-		"ldmia %0!, {r1}\n"
-		"vmsr fpscr, r1\n"
+		"vmsr fpscr, r2\n"
 		"vldmia %0!, {d0-d15}\n"
-		::"r" (ctx): "r1"
+		::"r" (ctx): "r1","r2"
 	);
 }
@@ -259,4 +255,10 @@
 void fpu_context_save(fpu_context_t *ctx)
 {
+	const uint32_t fpexc = fpexc_read();
+
+	if (fpexc & FPEXC_EX_FLAG) {
+		printf("EX FPU flag is on, things will fail\n");
+		//TODO implement common subarch context saving
+	}
 	if (save_context)
 		save_context(ctx);