Index: uspace/Makefile =================================================================== --- uspace/Makefile (revision b6636dc773461c14eb97c06b1348bbbf0b6499b1) +++ uspace/Makefile (revision 4bd3f45f52d8bd3feab6d541bd28616be5a25fdd) @@ -188,4 +188,9 @@ endif +ifeq ($(UARCH),arm32) + DIRS += \ + drv/infrastructure/rootamdm37x +endif + ## System libraries # Index: uspace/drv/bus/usb/ehci/ehci.ma =================================================================== --- uspace/drv/bus/usb/ehci/ehci.ma (revision b6636dc773461c14eb97c06b1348bbbf0b6499b1) +++ uspace/drv/bus/usb/ehci/ehci.ma (revision 4bd3f45f52d8bd3feab6d541bd28616be5a25fdd) @@ -1,1 +1,2 @@ +20 usb/host=ehci 10 pci/class=0c&subclass=03&progif=20 Index: uspace/drv/bus/usb/ohci/ohci.ma =================================================================== --- uspace/drv/bus/usb/ohci/ohci.ma (revision b6636dc773461c14eb97c06b1348bbbf0b6499b1) +++ uspace/drv/bus/usb/ohci/ohci.ma (revision 4bd3f45f52d8bd3feab6d541bd28616be5a25fdd) @@ -1,1 +1,2 @@ +20 usb/host=ohci 10 pci/class=0c&subclass=03&progif=10 Index: uspace/drv/bus/usb/ohci/ohci_regs.h =================================================================== --- uspace/drv/bus/usb/ohci/ohci_regs.h (revision b6636dc773461c14eb97c06b1348bbbf0b6499b1) +++ uspace/drv/bus/usb/ohci/ohci_regs.h (revision 4bd3f45f52d8bd3feab6d541bd28616be5a25fdd) @@ -245,5 +245,5 @@ #define RHPS_PRSC_FLAG (1 << 20) /* port reset status change WC */ #define RHPS_CHANGE_WC_MASK (0x1f0000) -} __attribute__((packed)) ohci_regs_t; +} ohci_regs_t; #endif /** Index: uspace/drv/infrastructure/rootamdm37x/Makefile =================================================================== --- uspace/drv/infrastructure/rootamdm37x/Makefile (revision 4bd3f45f52d8bd3feab6d541bd28616be5a25fdd) +++ uspace/drv/infrastructure/rootamdm37x/Makefile (revision 4bd3f45f52d8bd3feab6d541bd28616be5a25fdd) @@ -0,0 +1,37 @@ +# +# Copyright (c) 2012 Jan Vesely +# All rights reserved. +# +# Redistribution and use in source and binary forms, with or without +# modification, are permitted provided that the following conditions +# are met: +# +# - Redistributions of source code must retain the above copyright +# notice, this list of conditions and the following disclaimer. +# - Redistributions in binary form must reproduce the above copyright +# notice, this list of conditions and the following disclaimer in the +# documentation and/or other materials provided with the distribution. +# - The name of the author may not be used to endorse or promote products +# derived from this software without specific prior written permission. +# +# THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR +# IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES +# OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. +# IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, +# INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT +# NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF +# THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +# + +USPACE_PREFIX = ../../.. +LIBS = $(LIBDRV_PREFIX)/libdrv.a +EXTRA_CFLAGS += -I$(LIBDRV_PREFIX)/include +BINARY = rootamdm37x + +SOURCES = \ + rootamdm37x.c + +include $(USPACE_PREFIX)/Makefile.common Index: uspace/drv/infrastructure/rootamdm37x/core_cm.h =================================================================== --- uspace/drv/infrastructure/rootamdm37x/core_cm.h (revision 4bd3f45f52d8bd3feab6d541bd28616be5a25fdd) +++ uspace/drv/infrastructure/rootamdm37x/core_cm.h (revision 4bd3f45f52d8bd3feab6d541bd28616be5a25fdd) @@ -0,0 +1,193 @@ +/* + * Copyright (c) 2012 Jan Vesely + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * - Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * - Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * - The name of the author may not be used to endorse or promote products + * derived from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR + * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES + * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. + * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT + * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF + * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +/** @addtogroup amdm37xdrvcorecm + * @{ + */ +/** @file + * @brief CORE Clock Management IO register structure. + */ +#ifndef AMDM37x_CORE_CM_H +#define AMDM37x_CORE_CM_H +#include + +/* AM/DM37x TRM p.447 */ +#define CORE_CM_BASE_ADDRESS 0x48004a00 +#define CORE_CM_SIZE 8192 + +typedef struct { + ioport32_t fclken1; +#define CORE_CM_FCLKEN1_EN_MCBSP1_FLAG (1 << 9) +#define CORE_CM_FCLKEN1_EN_MCBSP5_FLAG (1 << 10) +#define CORE_CM_FCLKEN1_EN_GPT10_FLAG (1 << 11) +#define CORE_CM_FCLKEN1_EN_GPT11_FLAG (1 << 12) +#define CORE_CM_FCLKEN1_EN_UART1_FLAG (1 << 13) +#define CORE_CM_FCLKEN1_EN_UART2_FLAG (1 << 14) +#define CORE_CM_FCLKEN1_EN_I2C1_FLAG (1 << 15) +#define CORE_CM_FCLKEN1_EN_I2C2_FLAG (1 << 16) +#define CORE_CM_FCLKEN1_EN_I2C3_FLAG (1 << 17) +#define CORE_CM_FCLKEN1_EN_MCSPI1_FLAG (1 << 18) +#define CORE_CM_FCLKEN1_EN_MCSPI2_FLAG (1 << 19) +#define CORE_CM_FCLKEN1_EN_MCSPI3_FLAG (1 << 20) +#define CORE_CM_FCLKEN1_EN_MCSPI4_FLAG (1 << 21) +#define CORE_CM_FCLKEN1_EN_HDQ_FLAG (1 << 22) +#define CORE_CM_FCLKEN1_EN_MMC1_FLAG (1 << 24) +#define CORE_CM_FCLKEN1_EN_MMC2_FLAG (1 << 25) +#define CORE_CM_FCLKEN1_EN_MMC3_FLAG (1 << 30) + + uint32_t padd0_; + ioport32_t fclken3; +#define CORE_CM_FCLKEN3_EN_TS_FLAG (1 << 1) +#define CORE_CM_FCLKEN3_EN_USBTLL_FLAG (1 << 2) + + uint32_t padd1_; + ioport32_t iclken1; +#define CORE_CM_ICLKEN1_EN_SDRC_FLAG (1 << 1) +#define CORE_CM_ICLKEN1_EN_HSOTGUSB_FLAG (1 << 4) +#define CORE_CM_ICLKEN1_EN_SCMCTRL_FLAG (1 << 6) +#define CORE_CM_ICLKEN1_EN_MAILBOXES_FLAG (1 << 7) +#define CORE_CM_ICLKEN1_EN_MCBSP1_FLAG (1 << 9) +#define CORE_CM_ICLKEN1_EN_MCBSP5_FLAG (1 << 10) +#define CORE_CM_ICLKEN1_EN_GPT10_FLAG (1 << 11) +#define CORE_CM_ICLKEN1_EN_GPT11_FLAG (1 << 12) +#define CORE_CM_ICLKEN1_EN_UART1_FLAG (1 << 13) +#define CORE_CM_ICLKEN1_EN_UART2_FLAG (1 << 14) +#define CORE_CM_ICLKEN1_EN_I2C1_FLAG (1 << 15) +#define CORE_CM_ICLKEN1_EN_I2C2_FLAG (1 << 16) +#define CORE_CM_ICLKEN1_EN_I2C3_FLAG (1 << 17) +#define CORE_CM_ICLKEN1_EN_MCSPI1_FLAG (1 << 18) +#define CORE_CM_ICLKEN1_EN_MCSPI2_FLAG (1 << 19) +#define CORE_CM_ICLKEN1_EN_MCSPI3_FLAG (1 << 20) +#define CORE_CM_ICLKEN1_EN_MCSPI4_FLAG (1 << 21) +#define CORE_CM_ICLKEN1_EN_HDQ_FLAG (1 << 22) +#define CORE_CM_ICLKEN1_EN_MMC1_FLAG (1 << 24) +#define CORE_CM_ICLKEN1_EN_MMC2_FLAG (1 << 25) +#define CORE_CM_ICLKEN1_EN_ICR_FLAG (1 << 29) +#define CORE_CM_ICLKEN1_EN_MMC3_FLAG (1 << 30) + + ioport32_t reserved1; + ioport32_t iclken3; +#define CORE_CM_ICLKEN3_EN_USBTLL_FLAG (1 << 2) + + uint32_t padd2_; + const ioport32_t idlest1; +#define CORE_CM_IDLEST1_ST_SDRC_FLAG (1 << 1) +#define CORE_CM_IDLEST1_ST_SDMA_FLAG (1 << 2) +#define CORE_CM_IDLEST1_ST_HSOTGUSB_STBY_FLAG (1 << 4) +#define CORE_CM_IDLEST1_ST_HSOTGUSB_IDLE_FLAG (1 << 5) +#define CORE_CM_IDLEST1_ST_SCMCTRL_FLAG (1 << 6) +#define CORE_CM_IDLEST1_ST_MAILBOXES_FLAG (1 << 7) +#define CORE_CM_IDLEST1_ST_MCBSP1_FLAG (1 << 9) +#define CORE_CM_IDLEST1_ST_MCBSP5_FLAG (1 << 10) +#define CORE_CM_IDLEST1_ST_GPT10_FLAG (1 << 11) +#define CORE_CM_IDLEST1_ST_GPT11_FLAG (1 << 12) +#define CORE_CM_IDLEST1_ST_UART1_FLAG (1 << 13) +#define CORE_CM_IDLEST1_ST_UART2_FLAG (1 << 14) +#define CORE_CM_IDLEST1_ST_I2C1_FLAG (1 << 15) +#define CORE_CM_IDLEST1_ST_I2C2_FLAG (1 << 16) +#define CORE_CM_IDLEST1_ST_I2C3_FLAG (1 << 17) +#define CORE_CM_IDLEST1_ST_MCSPI1_FLAG (1 << 18) +#define CORE_CM_IDLEST1_ST_MCSPI2_FLAG (1 << 19) +#define CORE_CM_IDLEST1_ST_MCSPI3_FLAG (1 << 20) +#define CORE_CM_IDLEST1_ST_MCSPI4_FLAG (1 << 21) +#define CORE_CM_IDLEST1_ST_HDQ_FLAG (1 << 22) +#define CORE_CM_IDLEST1_ST_MMC1_FLAG (1 << 24) +#define CORE_CM_IDLEST1_ST_MMC2_FLAG (1 << 25) +#define CORE_CM_IDLEST1_ST_ICR_FLAG (1 << 29) +#define CORE_CM_IDLEST1_ST_MMC3_FLAG (1 << 30) + + const ioport32_t reserved2; + const ioport32_t idlest3; +#define CORE_CM_IDLEST3_ST_USBTLL_FLAG (1 << 2) + + uint32_t padd3_; + ioport32_t autoidle1; +#define CORE_CM_AUTOIDLE1_AUTO_HSOTGUSB_FLAG (1 << 4) +#define CORE_CM_AUTOIDLE1_AUTO_SCMCTRL_FLAG (1 << 6) +#define CORE_CM_AUTOIDLE1_AUTO_MAILBOXES_FLAG (1 << 7) +#define CORE_CM_AUTOIDLE1_AUTO_MCBSP1_FLAG (1 << 9) +#define CORE_CM_AUTOIDLE1_AUTO_MCBSP5_FLAG (1 << 10) +#define CORE_CM_AUTOIDLE1_AUTO_GPT10_FLAG (1 << 11) +#define CORE_CM_AUTOIDLE1_AUTO_GPT11_FLAG (1 << 12) +#define CORE_CM_AUTOIDLE1_AUTO_UART1_FLAG (1 << 13) +#define CORE_CM_AUTOIDLE1_AUTO_UART2_FLAG (1 << 14) +#define CORE_CM_AUTOIDLE1_AUTO_I2C1_FLAG (1 << 15) +#define CORE_CM_AUTOIDLE1_AUTO_I2C2_FLAG (1 << 16) +#define CORE_CM_AUTOIDLE1_AUTO_I2C3_FLAG (1 << 17) +#define CORE_CM_AUTOIDLE1_AUTO_MCSPI1_FLAG (1 << 18) +#define CORE_CM_AUTOIDLE1_AUTO_MCSPI2_FLAG (1 << 19) +#define CORE_CM_AUTOIDLE1_AUTO_MCSPI3_FLAG (1 << 20) +#define CORE_CM_AUTOIDLE1_AUTO_MCSPI4_FLAG (1 << 21) +#define CORE_CM_AUTOIDLE1_AUTO_HDQ_FLAG (1 << 22) +#define CORE_CM_AUTOIDLE1_AUTO_MMC1_FLAG (1 << 24) +#define CORE_CM_AUTOIDLE1_AUTO_MMC2_FLAG (1 << 25) +#define CORE_CM_AUTOIDLE1_AUTO_ICR_FLAG (1 << 29) +#define CORE_CM_AUTOIDLE1_AUTO_MMC3_FLAG (1 << 30) + + ioport32_t reserved3; + ioport32_t autoidle3; +#define CORE_CM_AUTOIDLE3_AUTO_USBTLL_FLAG (1 << 2) + + uint32_t padd4_; + ioport32_t clksel; +#define CORE_CM_CLKSEL_CLKSEL_L3_MASK 0x3 +#define CORE_CM_CLKSEL_CLKSEL_L3_SHIFT 0 +#define CORE_CM_CLKSEL_CLKSEL_L3_DIVIDED1 0x1 +#define CORE_CM_CLKSEL_CLKSEL_L3_DIVIDED2 0x2 +#define CORE_CM_CLKSEL_CLKSEL_L4_MASK 0x3 +#define CORE_CM_CLKSEL_CLKSEL_L4_SHIFT 2 +#define CORE_CM_CLKSEL_CLKSEL_L4_DIVIDED1 0x1 +#define CORE_CM_CLKSEL_CLKSEL_L4_DIVIDED2 0x2 +#define CORE_CM_CLKSEL_CLKSEL_96M_MASK 0x3 +#define CORE_CM_CLKSEL_CLKSEL_96M_SHIFT 2 +#define CORE_CM_CLKSEL_CLKSEL_96M_DIVIDED1 0x1 +#define CORE_CM_CLKSEL_CLKSEL_96M_DIVIDED2 0x2 +#define CORE_CM_CLKSEL_CLKSEL_GPT10_FLAG (1 << 6) +#define CORE_CM_CLKSEL_CLKSEL_GPT11_FLAG (1 << 6) + + uint32_t padd5_; + ioport32_t clkstctrl; +#define CORE_CM_CLKCTRL_CLKCTRL_L3_MASK 0x3 +#define CORE_CM_CLKCTRL_CLKCTRL_L3_SHIFT 0 +#define CORE_CM_CLKCTRL_CLKCTRL_L3_AUTO_EN 0x0 +#define CORE_CM_CLKCTRL_CLKCTRL_L3_AUTO_DIS 0x3 +#define CORE_CM_CLKCTRL_CLKCTRL_L4_MASK 0x3 +#define CORE_CM_CLKCTRL_CLKCTRL_L4_SHIFT 2 +#define CORE_CM_CLKCTRL_CLKCTRL_L4_AUTO_EN 0x0 +#define CORE_CM_CLKCTRL_CLKCTRL_L4_AUTO_DIS 0x3 + + const ioport32_t clkstst; +#define CORE_CM_CLKSTST_CLKACTIVITY_L3_FLAG (1 << 0) +#define CORE_CM_CLKSTST_CLKACTIVITY_L4_FLAG (1 << 1) + +} core_cm_regs_t; + +#endif +/** + * @} + */ Index: uspace/drv/infrastructure/rootamdm37x/rootamdm37x.c =================================================================== --- uspace/drv/infrastructure/rootamdm37x/rootamdm37x.c (revision 4bd3f45f52d8bd3feab6d541bd28616be5a25fdd) +++ uspace/drv/infrastructure/rootamdm37x/rootamdm37x.c (revision 4bd3f45f52d8bd3feab6d541bd28616be5a25fdd) @@ -0,0 +1,351 @@ +/* + * Copyright (c) 2012 Jan Vesely + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * - Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * - Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * - The name of the author may not be used to endorse or promote products + * derived from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR + * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES + * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. + * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT + * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF + * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +/** + * @defgroup root_amdm37x TI AM/DM37x platform driver. + * @brief HelenOS TI AM/DM37x platform driver. + * @{ + */ + +/** @file + */ +#define _DDF_DATA_IMPLANT + +#include +#include +#include +#include +#include +#include + +#include "uhh.h" +#include "usbtll.h" +#include "core_cm.h" +#include "usbhost_cm.h" + +#define NAME "rootamdm37x" + +typedef struct { + hw_resource_list_t hw_resources; +} rootamdm37x_fun_t; + +#define OHCI_BASE_ADDRESS 0x48064400 +#define OHCI_SIZE 1024 +#define EHCI_BASE_ADDRESS 0x48064800 +#define EHCI_SIZE 1024 + +static hw_resource_t ohci_res[] = { + { + .type = MEM_RANGE, + /* See amdm37x TRM page. 3316 for these values */ + .res.io_range = { + .address = OHCI_BASE_ADDRESS, + .size = OHCI_SIZE, + .endianness = LITTLE_ENDIAN + }, + }, + { + .type = INTERRUPT, + .res.interrupt = { .irq = 76 }, + }, +}; + +static const rootamdm37x_fun_t ohci = { + .hw_resources = { + .resources = ohci_res, + .count = sizeof(ohci_res)/sizeof(ohci_res[0]), + } +}; + +static hw_resource_t ehci_res[] = { + { + .type = MEM_RANGE, + /* See amdm37x TRM page. 3316 for these values */ + .res.io_range = { + .address = EHCI_BASE_ADDRESS, + .size = EHCI_SIZE, + .endianness = LITTLE_ENDIAN + }, + }, + { + .type = INTERRUPT, + .res.interrupt = { .irq = 77 }, + }, +}; + +static const rootamdm37x_fun_t ehci = { + .hw_resources = { + .resources = ehci_res, + .count = sizeof(ehci_res)/sizeof(ehci_res[0]), + } +}; + +static hw_resource_list_t *rootamdm37x_get_resources(ddf_fun_t *fnode); +static bool rootamdm37x_enable_interrupt(ddf_fun_t *fun); + +static hw_res_ops_t fun_hw_res_ops = { + .get_resource_list = &rootamdm37x_get_resources, + .enable_interrupt = &rootamdm37x_enable_interrupt, +}; + +static ddf_dev_ops_t rootamdm37x_fun_ops = +{ + .interfaces[HW_RES_DEV_IFACE] = &fun_hw_res_ops +}; + +static int usb_clocks(bool on) +{ + usbhost_cm_regs_t *usb_host_cm = NULL; + core_cm_regs_t *l4_core_cm = NULL; + + int ret = pio_enable((void*)USBHOST_CM_BASE_ADDRESS, USBHOST_CM_SIZE, + (void**)&usb_host_cm); + if (ret != EOK) + return ret; + + ret = pio_enable((void*)CORE_CM_BASE_ADDRESS, CORE_CM_SIZE, + (void**)&l4_core_cm); + if (ret != EOK) + return ret; + + assert(l4_core_cm); + assert(usb_host_cm); + if (on) { + l4_core_cm->iclken3 |= CORE_CM_ICLKEN3_EN_USBTLL_FLAG; + l4_core_cm->fclken3 |= CORE_CM_FCLKEN3_EN_USBTLL_FLAG; + usb_host_cm->iclken |= USBHOST_CM_ICLKEN_EN_USBHOST; + usb_host_cm->fclken |= USBHOST_CM_FCLKEN_EN_USBHOST1_FLAG; + usb_host_cm->fclken |= USBHOST_CM_FCLKEN_EN_USBHOST2_FLAG; + } else { + usb_host_cm->fclken &= ~USBHOST_CM_FCLKEN_EN_USBHOST2_FLAG; + usb_host_cm->fclken &= ~USBHOST_CM_FCLKEN_EN_USBHOST1_FLAG; + usb_host_cm->iclken &= ~USBHOST_CM_ICLKEN_EN_USBHOST; + l4_core_cm->fclken3 &= ~CORE_CM_FCLKEN3_EN_USBTLL_FLAG; + l4_core_cm->iclken3 &= ~CORE_CM_ICLKEN3_EN_USBTLL_FLAG; + } + + //TODO Unmap those registers. + + return ret; +} + +/** Initialize USB TLL port connections. + * + * Different modes are on page 3312 of the Manual Figure 22-34. + * Select mode than can operate in FS/LS. + */ +static int usb_tll_init() +{ + tll_regs_t *usb_tll = NULL; + uhh_regs_t *uhh_conf = NULL; + + int ret = pio_enable((void*)AMDM37x_USBTLL_BASE_ADDRESS, + AMDM37x_USBTLL_SIZE, (void**)&usb_tll); + if (ret != EOK) + return ret; + + ret = pio_enable((void*)AMDM37x_UHH_BASE_ADDRESS, + AMDM37x_UHH_SIZE, (void**)&uhh_conf); + if (ret != EOK) + return ret; + + /* Reset USB TLL */ + usb_tll->sysconfig |= TLL_SYSCONFIG_SOFTRESET_FLAG; + ddf_msg(LVL_DEBUG2, "Waiting for USB TLL reset"); + while (!(usb_tll->sysstatus & TLL_SYSSTATUS_RESET_DONE_FLAG)); + ddf_msg(LVL_DEBUG, "USB TLL Reset done."); + + { + /* Setup idle mode (smart idle) */ + uint32_t sysc = usb_tll->sysconfig; + sysc |= TLL_SYSCONFIG_CLOCKACTIVITY_FLAG | TLL_SYSCONFIG_AUTOIDLE_FLAG; + sysc = (sysc + & ~(TLL_SYSCONFIG_SIDLE_MODE_MASK << TLL_SYSCONFIG_SIDLE_MODE_SHIFT) + ) | (0x2 << TLL_SYSCONFIG_SIDLE_MODE_SHIFT); + usb_tll->sysconfig = sysc; + ddf_msg(LVL_DEBUG2, "Set TLL->sysconfig (%p) to %x:%x.", + &usb_tll->sysconfig, usb_tll->sysconfig, sysc); + } + + { + /* Smart idle for UHH */ + uint32_t sysc = uhh_conf->sysconfig; + sysc |= UHH_SYSCONFIG_CLOCKACTIVITY_FLAG | UHH_SYSCONFIG_AUTOIDLE_FLAG; + sysc = (sysc + & ~(UHH_SYSCONFIG_SIDLE_MODE_MASK << UHH_SYSCONFIG_SIDLE_MODE_SHIFT) + ) | (0x2 << UHH_SYSCONFIG_SIDLE_MODE_SHIFT); + sysc = (sysc + & ~(UHH_SYSCONFIG_MIDLE_MODE_MASK << UHH_SYSCONFIG_MIDLE_MODE_SHIFT) + ) | (0x2 << UHH_SYSCONFIG_MIDLE_MODE_SHIFT); + ddf_msg(LVL_DEBUG2, "Set UHH->sysconfig (%p) to %x.", + &uhh_conf->sysconfig, uhh_conf->sysconfig); + uhh_conf->sysconfig = sysc; + + /* All ports are connected on BBxM */ + uhh_conf->hostconfig |= (UHH_HOSTCONFIG_P1_CONNECT_STATUS_FLAG + | UHH_HOSTCONFIG_P2_CONNECT_STATUS_FLAG + | UHH_HOSTCONFIG_P3_CONNECT_STATUS_FLAG); + + /* Set all ports to go through TLL(UTMI) + * Direct connection can only work in HS mode */ + uhh_conf->hostconfig |= (UHH_HOSTCONFIG_P1_ULPI_BYPASS_FLAG + | UHH_HOSTCONFIG_P2_ULPI_BYPASS_FLAG + | UHH_HOSTCONFIG_P3_ULPI_BYPASS_FLAG); + ddf_msg(LVL_DEBUG2, "Set UHH->hostconfig (%p) to %x.", + &uhh_conf->hostconfig, uhh_conf->hostconfig); + } + + usb_tll->shared_conf |= TLL_SHARED_CONF_FCLK_IS_ON_FLAG; + ddf_msg(LVL_DEBUG2, "Set shared conf port (%p) to %x.", + &usb_tll->shared_conf, usb_tll->shared_conf); + + for (unsigned i = 0; i < 3; ++i) { + uint32_t ch = usb_tll->channel_conf[i]; + /* Clear Channel mode and FSLS mode */ + ch &= ~(TLL_CHANNEL_CONF_CHANMODE_MASK + << TLL_CHANNEL_CONF_CHANMODE_SHIFT) + & ~(TLL_CHANNEL_CONF_FSLSMODE_MASK + << TLL_CHANNEL_CONF_FSLSMODE_SHIFT); + + /* Serial mode is the only one capable of FS/LS operation. */ + ch |= (TLL_CHANNEL_CONF_CHANMODE_UTMI_SERIAL_MODE + << TLL_CHANNEL_CONF_CHANMODE_SHIFT); + + /* Select FS/LS mode, no idea what the difference is + * one of bidirectional modes might be good choice + * 2 = 3pin bidi phy. */ + ch |= (2 << TLL_CHANNEL_CONF_FSLSMODE_SHIFT); + + /* Write to register */ + ddf_msg(LVL_DEBUG2, "Setting port %u(%p) to %x.", + i, &usb_tll->channel_conf[i], ch); + usb_tll->channel_conf[i] = ch; + } + return EOK; +} + +static bool rootamdm37x_add_fun(ddf_dev_t *dev, const char *name, + const char *str_match_id, const rootamdm37x_fun_t *fun) +{ + ddf_msg(LVL_DEBUG, "Adding new function '%s'.", name); + + /* Create new device function. */ + ddf_fun_t *fnode = ddf_fun_create(dev, fun_inner, name); + if (fnode == NULL) + return ENOMEM; + + + /* Add match id */ + if (ddf_fun_add_match_id(fnode, str_match_id, 100) != EOK) { + // TODO This will try to free our data! + ddf_fun_destroy(fnode); + return false; + } + + /* Set provided operations to the device. */ + ddf_fun_data_implant(fnode, (void*)fun); + ddf_fun_set_ops(fnode, &rootamdm37x_fun_ops); + + /* Register function. */ + if (ddf_fun_bind(fnode) != EOK) { + ddf_msg(LVL_ERROR, "Failed binding function %s.", name); + ddf_fun_destroy(fnode); + return false; + } + + return true; +} + +/** Add the root device. + * + * @param dev Device which is root of the whole device tree + * (both of HW and pseudo devices). + * + * @return Zero on success, negative error number otherwise. + * + */ +static int rootamdm37x_dev_add(ddf_dev_t *dev) +{ + int ret = usb_clocks(true); + if (ret != EOK) { + ddf_msg(LVL_FATAL, "Failed to enable USB HC clocks!.\n"); + return ret; + } + + ret = usb_tll_init(); + if (ret != EOK) { + ddf_msg(LVL_FATAL, "Failed to init USB TLL!.\n"); + usb_clocks(false); + return ret; + } + + /* Register functions */ + if (!rootamdm37x_add_fun(dev, "ohci", "usb/host=ohci", &ohci)) + ddf_msg(LVL_ERROR, "Failed to add OHCI function for " + "BeagleBoard-xM platform."); + if (!rootamdm37x_add_fun(dev, "ehci", "usb/host=ehci", &ehci)) + ddf_msg(LVL_ERROR, "Failed to add EHCI function for " + "BeagleBoard-xM platform."); + + return EOK; +} + +/** The root device driver's standard operations. */ +static driver_ops_t rootamdm37x_ops = { + .dev_add = &rootamdm37x_dev_add +}; + +/** The root device driver structure. */ +static driver_t rootamdm37x_driver = { + .name = NAME, + .driver_ops = &rootamdm37x_ops +}; + +static hw_resource_list_t *rootamdm37x_get_resources(ddf_fun_t *fnode) +{ + rootamdm37x_fun_t *fun = ddf_fun_data_get(fnode); + assert(fun != NULL); + return &fun->hw_resources; +} + +static bool rootamdm37x_enable_interrupt(ddf_fun_t *fun) +{ + /* TODO */ + return false; +} + +int main(int argc, char *argv[]) +{ + printf("%s: HelenOS AM/DM37x(OMAP37x) platform driver\n", NAME); + ddf_log_init(NAME, LVL_ERROR); + return ddf_driver_main(&rootamdm37x_driver); +} + +/** + * @} + */ Index: uspace/drv/infrastructure/rootamdm37x/rootamdm37x.ma =================================================================== --- uspace/drv/infrastructure/rootamdm37x/rootamdm37x.ma (revision 4bd3f45f52d8bd3feab6d541bd28616be5a25fdd) +++ uspace/drv/infrastructure/rootamdm37x/rootamdm37x.ma (revision 4bd3f45f52d8bd3feab6d541bd28616be5a25fdd) @@ -0,0 +1,1 @@ +10 platform/beagleboardxm Index: uspace/drv/infrastructure/rootamdm37x/uhh.h =================================================================== --- uspace/drv/infrastructure/rootamdm37x/uhh.h (revision 4bd3f45f52d8bd3feab6d541bd28616be5a25fdd) +++ uspace/drv/infrastructure/rootamdm37x/uhh.h (revision 4bd3f45f52d8bd3feab6d541bd28616be5a25fdd) @@ -0,0 +1,93 @@ +/* + * Copyright (c) 2012 Jan Vesely + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * - Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * - Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * - The name of the author may not be used to endorse or promote products + * derived from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR + * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES + * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. + * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT + * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF + * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +/** @addtogroup amdm37xdrvuhh + * @{ + */ +/** @file + * @brief UHH IO register structure. + */ +#ifndef AMDM37x_UHH_H +#define AMDM37x_UHH_H +#include + +#define AMDM37x_UHH_BASE_ADDRESS 0x48064000 +#define AMDM37x_UHH_SIZE 1024 + +typedef struct { + const ioport32_t revision; +#define UHH_REVISION_MASK 0xf +#define UHH_REVISION_MINOR_SHIFT 0 +#define UHH_REVISION_MAJOR_SHIFT 4 + + uint32_t padd0_[3]; + ioport32_t sysconfig; +#define UHH_SYSCONFIG_AUTOIDLE_FLAG (1 << 0) +#define UHH_SYSCONFIG_SOFTRESET_FLAG (1 << 1) +#define UHH_SYSCONFIG_ENWAKEUP_FLAG (1 << 2) +#define UHH_SYSCONFIG_CLOCKACTIVITY_FLAG (1 << 8) +#define UHH_SYSCONFIG_SIDLE_MODE_MASK 0x3 +#define UHH_SYSCONFIG_SIDLE_MODE_SHIFT 3 +#define UHH_SYSCONFIG_MIDLE_MODE_MASK 0x3 +#define UHH_SYSCONFIG_MIDLE_MODE_SHIFT 12 + + const ioport32_t sysstatus; +#define UHH_SYSSTATUS_RESETDONE_FLAG (1 << 0) +#define UHH_SYSSTATUS_OHCI_RESETDONE_FLAG (1 << 1) +#define UHH_SYSSTATUS_EHCI_RESETDONE_FLAG (1 << 2) + + uint32_t padd1_[10]; + ioport32_t hostconfig; +#define UHH_HOSTCONFIG_P1_ULPI_BYPASS_FLAG (1 << 0) +#define UHH_HOSTCONFIG_AUTOPPD_ON_OVERCUR_EN_FLAG (1 << 1) +#define UHH_HOSTCONFIG_ENA_INCR4_FLAG (1 << 2) +#define UHH_HOSTCONFIG_ENA_INCR8_FLAG (1 << 3) +#define UHH_HOSTCONFIG_ENA_INCR16_FLA (1 << 4) +#define UHH_HOSTCONFIG_ENA_INCR_ALIGN_FLAG (1 << 5) +#define UHH_HOSTCONFIG_P1_CONNECT_STATUS_FLAG (1 << 8) +#define UHH_HOSTCONFIG_P2_CONNECT_STATUS_FLAG (1 << 9) +#define UHH_HOSTCONFIG_P3_CONNECT_STATUS_FLAG (1 << 10) +#define UHH_HOSTCONFIG_P2_ULPI_BYPASS_FLAG (1 << 11) +#define UHH_HOSTCONFIG_P3_ULPI_BYPASS_FLAG (1 << 12) + + ioport32_t debug_csr; +#define UHH_DEBUG_CSR_EHCI_FLADJ_MASK (0x3f) +#define UHH_DEBUG_CSR_EHCI_FLADJ_SHIFT 0 +#define UHH_DEBUG_CSR_EHCI_SIMULATION_MODE_FLAG (1 << 6) +#define UHH_DEBUG_CSR_OHCI_CNTSEL_FLAG (1 << 7) +#define UHH_DEBUG_CSR_OHCI_GLOBAL_sUSPEND_FLAG (1 << 16) +#define UHH_DEBUG_CSR_OHCI_CCS1_FLAG (1 << 17) +#define UHH_DEBUG_CSR_OHCI_CCS2_FLAG (1 << 18) +#define UHH_DEBUG_CSR_OHCI_CCS3_FLAG (1 << 19) + +} uhh_regs_t; + +#endif +/** + * @} + */ Index: uspace/drv/infrastructure/rootamdm37x/usbhost_cm.h =================================================================== --- uspace/drv/infrastructure/rootamdm37x/usbhost_cm.h (revision 4bd3f45f52d8bd3feab6d541bd28616be5a25fdd) +++ uspace/drv/infrastructure/rootamdm37x/usbhost_cm.h (revision 4bd3f45f52d8bd3feab6d541bd28616be5a25fdd) @@ -0,0 +1,82 @@ +/* + * Copyright (c) 2012 Jan Vesely + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * - Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * - Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * - The name of the author may not be used to endorse or promote products + * derived from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR + * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES + * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. + * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT + * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF + * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +/** @addtogroup amdm37xdrvusbhostcm + * @{ + */ +/** @file + * @brief USBHOST Clock Management IO register structure. + */ +#ifndef AMDM37x_USBHOST_CM_H +#define AMDM37x_USBHOST_CM_H +#include + +/* AM/DM37x TRM p.447 */ +#define USBHOST_CM_BASE_ADDRESS 0x48005400 +#define USBHOST_CM_SIZE 8192 + +typedef struct { + ioport32_t fclken; +#define USBHOST_CM_FCLKEN_EN_USBHOST1_FLAG (1 << 0) +#define USBHOST_CM_FCLKEN_EN_USBHOST2_FLAG (1 << 1) + + uint32_t padd0_[3]; + ioport32_t iclken; +#define USBHOST_CM_ICLKEN_EN_USBHOST (1 << 0) + + uint32_t padd1_[3]; + const ioport32_t idlest; +#define USBHOST_CM_IDLEST_ST_USBHOST_STDBY_FLAG (1 << 0) +#define USBHOST_CM_IDLEST_ST_USBHOST_IDLE_FLAG (1 << 1) + + uint32_t padd2_[3]; + ioport32_t autoidle; +#define USBHOST_CM_AUTOIDLE_AUTO_USBHOST_FLAG (1 << 0) + + uint32_t padd3_[4]; + ioport32_t sleepdep; +#define USBHOST_CM_SLEEPDEP_EN_MPU_FLAG (1 << 1) +#define USBHOST_CM_SLEEPDEP_EN_IVA2_FLAG (1 << 2) + + ioport32_t clkstctrl; +#define USBHOST_CM_CLKSTCTRL_CLKSTCTRL_USBHOST_MASK 0x3 +#define USBHOST_CM_CLKSTCTRL_CLKSTCTRL_USBHOST_SHIFT 0 +#define USBHOST_CM_CLKSTCTRL_CLKSTCTRL_USBHOST_AUTO_DIS 0x0 +#define USBHOST_CM_CLKSTCTRL_CLKSTCTRL_USBHOST_SUPERVISED_SLEEP 0x1 +#define USBHOST_CM_CLKSTCTRL_CLKSTCTRL_USBHOST_SUPERVISED_WAKEUP 0x2 +#define USBHOST_CM_CLKSTCTRL_CLKSTCTRL_USBHOST_AUTO_EN 0x1 + + ioport32_t clkstst; +#define USBHOST_CM_CLKSTCTRL_CLKSTST_CLKACTIVITY_USBHOST (1 << 0) +} usbhost_cm_regs_t; + +#endif +/** + * @} + */ + Index: uspace/drv/infrastructure/rootamdm37x/usbtll.h =================================================================== --- uspace/drv/infrastructure/rootamdm37x/usbtll.h (revision 4bd3f45f52d8bd3feab6d541bd28616be5a25fdd) +++ uspace/drv/infrastructure/rootamdm37x/usbtll.h (revision 4bd3f45f52d8bd3feab6d541bd28616be5a25fdd) @@ -0,0 +1,115 @@ +/* + * Copyright (c) 2012 Jan Vesely + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * - Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * - Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * - The name of the author may not be used to endorse or promote products + * derived from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR + * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES + * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. + * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT + * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF + * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +/** @addtogroup amdm37xdrvusbtll + * @{ + */ +/** @file + * @brief USBTLL IO register structure. + */ +#ifndef AMDM37x_USBTLL_H +#define AMDM37x_USBTLL_H +#include + +#define AMDM37x_USBTLL_BASE_ADDRESS 0x48062000 +#define AMDM37x_USBTLL_SIZE 4096 + +typedef struct { + const ioport32_t revision; +#define TLL_REVISION_MASK 0xf +#define TLL_REVISION_MINOR_SHIFT 0 +#define TLL_REVISION_MAJOR_SHIFT 4 + + uint32_t padd0_[3]; + ioport32_t sysconfig; +#define TLL_SYSCONFIG_AUTOIDLE_FLAG (1 << 0) +#define TLL_SYSCONFIG_SOFTRESET_FLAG (1 << 1) +#define TLL_SYSCONFIG_ENWAKEUP_FLAG (1 << 2) +#define TLL_SYSCONFIG_CLOCKACTIVITY_FLAG (1 << 8) +#define TLL_SYSCONFIG_SIDLE_MODE_MASK 0x3 +#define TLL_SYSCONFIG_SIDLE_MODE_SHIFT 3 + + ioport32_t sysstatus; +#define TLL_SYSSTATUS_RESET_DONE_FLAG (1 << 0) + + const ioport32_t irqstatus; +#define TLL_IRQSTATUS_FCLK_START_FLAG (1 << 0) +#define TLL_IRQSTATUS_FCLK_END_FLAG (1 << 1) +#define TLL_IRQSTATUS_ACCESS_ERROR_FLAG (1 << 2) + + ioport32_t irqenable; +#define TLL_IRQSTATUS_FCLK_START_EN_FLAG (1 << 0) +#define TLL_IRQSTATUS_FCLK_END_EN_FLAG (1 << 1) +#define TLL_IRQSTATUS_ACCESS_ERROR_EN_FLAG (1 << 2) + + uint32_t padd1_[4]; + ioport32_t shared_conf; +#define TLL_SHARED_CONF_FCLK_IS_ON_FLAG (1 << 0) +#define TLL_SHARED_CONF_FCLK_REQ_FLAG (1 << 1) +#define TLL_SHARED_CONF_USB_180D_SDR_EN_FLAG (1 << 5) +#define TLL_SHARED_CONF_USB_90D_DDR_EN_FLAG (1 << 6) +#define TLL_SHARED_CONF_USB_DIVRATIO_MASK 0x7 +#define TLL_SHARED_CONF_USB_DIVRATIO_SHIFT 2 + + uint32_t padd2_[3]; + ioport32_t channel_conf[3]; +#define TLL_CHANNEL_CONF_CHANEN_FLAG (1 << 0) +#define TLL_CHANNEL_CONF_CHANMODE_MASK 0x3 +#define TLL_CHANNEL_CONF_CHANMODE_SHIFT 1 +#define TLL_CHANNEL_CONF_CHANMODE_UTMI_ULPI_MODE 0 +#define TLL_CHANNEL_CONF_CHANMODE_UTMI_SERIAL_MODE 1 +#define TLL_CHANNEL_CONF_CHANMODE_UTMI_TRANS_MODE 2 +#define TLL_CHANNEL_CONF_CHANMODE_NO_MODE 3 +#define TLL_CHANNEL_CONF_UTMIISADEV_FLAG (1 << 3) +#define TLL_CHANNEL_CONF_TLLATTACH_FLAG (1 << 4) +#define TLL_CHANNEL_CONF_TLLCONNECT_FLAG (1 << 5) +#define TLL_CHANNEL_CONF_TLLFULLSPEED_FLAG (1 << 6) +#define TLL_CHANNEL_CONF_ULPIOUTCLKMODE_FLAG (1 << 7) +#define TLL_CHANNEL_CONF_ULPIDDRMODE_FLAG (1 << 8) +#define TLL_CHANNEL_CONF_UTMIAUTOIDLE_FLAG (1 << 9) +#define TLL_CHANNEL_CONF_ULPIAUTOIDLE_FLAG (1 << 10) +#define TLL_CHANNEL_CONF_ULPINOBITSTUFF_FLAG (1 << 11) +#define TLL_CHANNEL_CONF_CHRGVBUS_FLAG (1 << 15) +#define TLL_CHANNEL_CONF_DRVVBUS_FLAG (1 << 16) +#define TLL_CHANNEL_CONF_TESTEN_FLAG (1 << 17) +#define TLL_CHANNEL_CONF_TESTTXEN_FLAG (1 << 18) +#define TLL_CHANNEL_CONF_TESTTXDAT_FLAG (1 << 19) +#define TLL_CHANNEL_CONF_TESTTXSE0_FLAG (1 << 20) +#define TLL_CHANNEL_CONF_FSLSMODE_MASK 0xf +#define TLL_CHANNEL_CONF_FSLSMODE_SHIFT 24 +#define TLL_CHANNEL_CONF_FSLSLINESTATE_MASK 0x3 +#define TLL_CHANNEL_CONF_FSLSLINESTATE_SHIFT 28 + + /* The rest are 8bit ULPI registers */ +} tll_regs_t; + +#endif +/** + * @} + */ + Index: uspace/lib/c/arch/arm32/Makefile.common =================================================================== --- uspace/lib/c/arch/arm32/Makefile.common (revision b6636dc773461c14eb97c06b1348bbbf0b6499b1) +++ uspace/lib/c/arch/arm32/Makefile.common (revision 4bd3f45f52d8bd3feab6d541bd28616be5a25fdd) @@ -28,5 +28,5 @@ # -GCC_CFLAGS += -ffixed-r9 -mtp=soft -fno-omit-frame-pointer -march=armv4 -mapcs-frame +GCC_CFLAGS += -ffixed-r9 -mtp=soft -fno-omit-frame-pointer -mapcs-frame -march=$(subst _,-,$(PROCESSOR)) ENDIANESS = LE Index: uspace/lib/usbdev/include/usb/dev/request.h =================================================================== --- uspace/lib/usbdev/include/usb/dev/request.h (revision b6636dc773461c14eb97c06b1348bbbf0b6499b1) +++ uspace/lib/usbdev/include/usb/dev/request.h (revision 4bd3f45f52d8bd3feab6d541bd28616be5a25fdd) @@ -93,8 +93,8 @@ uint8_t request; /** Main parameter to the request. */ - union { + union __attribute__ ((packed)) { uint16_t value; /* FIXME: add #ifdefs according to host endianness */ - struct { + struct __attribute__ ((packed)) { uint8_t value_low; uint8_t value_high; @@ -108,4 +108,6 @@ uint16_t length; } __attribute__ ((packed)) usb_device_request_setup_packet_t; + +int assert[(sizeof(usb_device_request_setup_packet_t) == 8) ? 1: -1]; int usb_control_request_set(usb_pipe_t *,