Index: uspace/lib/c/arch/amd64/src/fibril.S
===================================================================
--- uspace/lib/c/arch/amd64/src/fibril.S	(revision c1b979a5a2332e971f29013cd230bf1a1c6f35d4)
+++ uspace/lib/c/arch/amd64/src/fibril.S	(revision 4b334fd67169af5de794ce1053c6124e2ea71cd4)
@@ -32,5 +32,5 @@
 .global context_restore
 
-#include <libarch/context_offset.h>
+#include <libarch/fibril_context.h>
 
 ## Save current CPU context
@@ -42,12 +42,20 @@
 	movq (%rsp), %rdx     # the caller's return %eip
 	
-	# in %edi is passed 1st argument
-	CONTEXT_SAVE_ARCH_CORE %rdi %rdx 
+	# in %rdi is passed 1st argument
+	movq %rdx, CONTEXT_OFFSET_PC(%rdi)
+	movq %rsp, CONTEXT_OFFSET_SP(%rdi)
+	
+	movq %rbx, CONTEXT_OFFSET_RBX(%rdi)
+	movq %rbp, CONTEXT_OFFSET_RBP(%rdi)
+	movq %r12, CONTEXT_OFFSET_R12(%rdi)
+	movq %r13, CONTEXT_OFFSET_R13(%rdi)
+	movq %r14, CONTEXT_OFFSET_R14(%rdi)
+	movq %r15, CONTEXT_OFFSET_R15(%rdi)
 	
 	# save TLS
 	movq %fs:0, %rax
-	movq %rax, OFFSET_TLS(%rdi)
+	movq %rax, CONTEXT_OFFSET_TLS(%rdi)
 	
-	xorl %eax, %eax       # context_save returns 1
+	xorl %eax, %eax                      # context_save returns 1
 	incl %eax
 	ret
@@ -60,13 +68,23 @@
 context_restore:
 	
-	CONTEXT_RESTORE_ARCH_CORE %rdi %rdx
+	movq CONTEXT_OFFSET_R15(%rdi), %r15
+	movq CONTEXT_OFFSET_R14(%rdi), %r14
+	movq CONTEXT_OFFSET_R13(%rdi), %r13
+	movq CONTEXT_OFFSET_R12(%rdi), %r12
+	movq CONTEXT_OFFSET_RBP(%rdi), %rbp
+	movq CONTEXT_OFFSET_RBX(%rdi), %rbx
+	
+	movq CONTEXT_OFFSET_SP(%rdi), %rsp   # ctx->sp -> %rsp
+	
+	movq CONTEXT_OFFSET_PC(%rdi), %rdx
 	
 	movq %rdx,(%rsp)
 	
 	# Set thread local storage
-	movq OFFSET_TLS(%rdi), %rdi  # Set arg1 to TLS addr
-	movl $1, %eax                # SYS_TLS_SET
+	movq CONTEXT_OFFSET_TLS(%rdi), %rdi  # Set arg1 to TLS addr
+	movl $1, %eax                        # SYS_TLS_SET
 	syscall
 	
-	xorl %eax, %eax              # context_restore returns 0
+	xorl %eax, %eax                      # context_restore returns 0
 	ret
+
