Index: kernel/arch/sparc64/include/barrier.h
===================================================================
--- kernel/arch/sparc64/include/barrier.h	(revision 40239b9f7eb371244007b25cde720aa2f90f7a41)
+++ kernel/arch/sparc64/include/barrier.h	(revision 4acaa7c0d4fdaf4f08ad44578e5a437a7f8dc98f)
@@ -36,4 +36,10 @@
 #define KERN_sparc64_BARRIER_H_
 
+#ifdef KERNEL
+#include <typedefs.h>
+#else
+#include <stdint.h>
+#endif
+
 /*
  * Our critical section barriers are prepared for the weakest RMO memory model.
@@ -64,4 +70,6 @@
 static inline void flush_pipeline(void)
 {
+	uint64_t pc;
+
 	/*
 	 * The FLUSH instruction takes address parameter.
@@ -70,9 +78,13 @@
 	 * The entire kernel text is mapped by a locked ITLB and
 	 * DTLB entries. Therefore, when this function is called,
-	 * the %o7 register will always be in the range mapped by
+	 * the %pc register will always be in the range mapped by
 	 * DTLB.
 	 */
 	 
-        asm volatile ("flush %o7\n");
+        asm volatile (
+		"rd %%pc, %0\n"
+		"flush %0\n"
+		: "=&r" (pc)
+	);
 }