Index: kernel/arch/ia32/include/cpu.h
===================================================================
--- kernel/arch/ia32/include/cpu.h	(revision c696ad1a6f749478b584a8ae1109c2cc4a94c62a)
+++ kernel/arch/ia32/include/cpu.h	(revision 4a537dda1680cfd9fd57ba877d36d641060c8f7f)
@@ -50,4 +50,5 @@
 #include <arch/pm.h>
 #include <arch/asm.h>
+#include <arch/cpuid.h>
 
 typedef struct {
@@ -56,4 +57,6 @@
 	unsigned int model;
 	unsigned int stepping;
+	cpuid_feature_info fi;
+
 	tss_t *tss;
 	
Index: kernel/arch/ia32/src/cpu/cpu.c
===================================================================
--- kernel/arch/ia32/src/cpu/cpu.c	(revision c696ad1a6f749478b584a8ae1109c2cc4a94c62a)
+++ kernel/arch/ia32/src/cpu/cpu.c	(revision 4a537dda1680cfd9fd57ba877d36d641060c8f7f)
@@ -92,5 +92,4 @@
 void cpu_arch_init(void)
 {
-	cpuid_feature_info fi;
 	cpuid_extended_feature_info efi;
 	cpu_info_t info;
@@ -104,13 +103,13 @@
 	cpuid(INTEL_CPUID_STANDARD, &info);
 	
-	fi.word = info.cpuid_edx;
+	CPU->arch.fi.word = info.cpuid_edx;
 	efi.word = info.cpuid_ecx;
 	
-	if (fi.bits.fxsr)
+	if (CPU->arch.fi.bits.fxsr)
 		fpu_fxsr();
 	else
 		fpu_fsr();
 	
-	if (fi.bits.sse) {
+	if (CPU->arch.fi.bits.sse) {
 		asm volatile (
 			"mov %%cr4, %[help]\n"
@@ -122,6 +121,8 @@
 	}
 	
-	/* Setup fast SYSENTER/SYSEXIT syscalls */
-	syscall_setup_cpu();
+	if (CPU->arch.fi.bits.sep) {
+		/* Setup fast SYSENTER/SYSEXIT syscalls */
+		syscall_setup_cpu();
+	}
 }
 
Index: kernel/arch/ia32/src/proc/scheduler.c
===================================================================
--- kernel/arch/ia32/src/proc/scheduler.c	(revision c696ad1a6f749478b584a8ae1109c2cc4a94c62a)
+++ kernel/arch/ia32/src/proc/scheduler.c	(revision 4a537dda1680cfd9fd57ba877d36d641060c8f7f)
@@ -61,6 +61,8 @@
 	    SP_DELTA];
 	
-	/* Set kernel stack for CP3 -> CPL0 switch via SYSENTER */
-	write_msr(IA32_MSR_SYSENTER_ESP, kstk);
+	if (CPU->arch.fi.bits.sep) {
+		/* Set kernel stack for CP3 -> CPL0 switch via SYSENTER */
+		write_msr(IA32_MSR_SYSENTER_ESP, kstk);
+	}
 	
 	/* Set kernel stack for CPL3 -> CPL0 switch via interrupt */
